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drivers: gpio: Add support for RZ/V2H

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Add support for RZ/V2H

Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
This commit is contained in:
Tien Nguyen 2025-05-12 13:48:46 +07:00 • committed by Benjamin Cabé
commit 5f69dd15a5
3 changed files with 200 additions and 26 deletions
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18
drivers/gpio/gpio_renesas_rz.c
View file

@ -297,12 +297,12 @@ static int gpio_rz_int_disable(const struct device *dev, const struct device *gp
#if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT)
volatile uint32_t *tssr = &R_INTC->TSSR0;
volatile uint32_t *titsr = &R_INTC->TITSR0;
volatile uint32_t *tscr = &R_INTC->TSCR;
struct gpio_rz_int_data *data = dev->data;
/* Get register offset base on interrupt number. */
tssr = &tssr[int_num / 4];
titsr = &titsr[int_num / 16];
GPIO_RZ_TINT_SELECT_SOURCE_REG_CLEAR(int_num);
irq_disable(GPIO_RZ_TINT_IRQ_GET(int_num));
/* Disable interrupt and clear interrupt source. */
@ -312,7 +312,7 @@ static int gpio_rz_int_disable(const struct device *dev, const struct device *gp
/* Clear interrupt detection status. */
if (data->irq_set_edge & BIT(int_num)) {
*tscr &= ~BIT(int_num);
GPIO_RZ_TINT_STATUS_REG_CLEAR(int_num);
data->irq_set_edge &= ~BIT(int_num);
}
@ -350,13 +350,18 @@ static int gpio_rz_int_enable(const struct device *gpio_int_dev, const struct de
*titsr &= ~(3U << GPIO_RZ_TITSR_OFFSET(int_num));
*titsr |= (irq_type << GPIO_RZ_TITSR_OFFSET(int_num));
/* Select interrupt source base on port and pin number. */
*tssr &= ~(0xFF << (int_num));
*tssr |= (GPIO_RZ_TSSR_VAL(gpio_config->port_num, pin)) << GPIO_RZ_TSSR_OFFSET(int_num);
/* Select TINT source(only for RZV2H) */
GPIO_RZ_TINT_SELECT_SOURCE_REG_CLEAR(int_num);
GPIO_RZ_TINT_SELECT_SOURCE_REG_SET(int_num);
if (irq_type == GPIO_RZ_INT_EDGE_RISING || irq_type == GPIO_RZ_INT_EDGE_FALLING) {
gpio_int_data->irq_set_edge |= BIT(int_num);
/* Clear interrupt status. */
R_INTC->TSCR &= ~BIT(int_num);
GPIO_RZ_TINT_STATUS_REG_CLEAR(int_num);
}
GPIO_RZ_TINT_CLEAR_PENDING(int_num);
irq_enable(GPIO_RZ_TINT_IRQ_GET(int_num));
gpio_int_data->gpio_mapping[int_num].gpio_dev = gpio_dev;
gpio_int_data->gpio_mapping[int_num].pin = pin;
@ -448,15 +453,16 @@ static void gpio_rz_isr(uint16_t irq, void *param)
#if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT)
const struct device *dev = param;
struct gpio_rz_int_data *gpio_int_data = dev->data;
volatile uint32_t *tscr = &R_INTC->TSCR;
if (!(*tscr & BIT(irq))) {
#if GPIO_RZ_TINT_SPURIOUS_HANDLE
if (!(*GPIO_RZ_TINT_STATUS_REG_GET & BIT(irq))) {
LOG_DEV_DBG(dev, "tint:%u spurious irq, status 0", irq);
return;
}
#endif /* GPIO_RZ_TINT_SPURIOUS_HANDLE */
if (gpio_int_data->irq_set_edge & BIT(irq)) {
*tscr &= ~BIT(irq);
GPIO_RZ_TINT_STATUS_REG_CLEAR(irq);
}
uint8_t pin = gpio_int_data->gpio_mapping[irq].pin;

84
drivers/gpio/gpio_renesas_rz.h
View file

@ -8,46 +8,88 @@
#define ZEPHYR_DRIVERS_GPIO_RENESAS_RZ_H_
#include "r_ioport.h"
#include <zephyr/drivers/interrupt_controller/gic.h>
#define GPIO_RZ_INT_UNSUPPORTED 0xF
#if defined(CONFIG_SOC_SERIES_RZG3S) || defined(CONFIG_SOC_SERIES_RZA3UL) || \
defined(CONFIG_SOC_SERIES_RZV2L) || defined(CONFIG_SOC_SERIES_RZG2L)
defined(CONFIG_SOC_SERIES_RZV2L) || defined(CONFIG_SOC_SERIES_RZG2L) || \
defined(CONFIG_SOC_SERIES_RZV2H)
#include <zephyr/dt-bindings/gpio/renesas-rz-gpio.h>
#if defined(CONFIG_SOC_SERIES_RZG3S)
#define GPIO_RZ_P_REG_BASE_GET (&R_GPIO->P_20)
#define GPIO_RZ_PM_REG_BASE_GET (&R_GPIO->PM_20)
#define GPIO_RZ_PFC_REG_BASE_GET (&R_GPIO->PFC_20)
#define GPIO_RZ_MAX_PORT_NUM 19
#define GPIO_RZ_TINT_IRQ_OFFSET 429
#define R_INTC R_INTC_IM33
#define GPIO_RZ_P_REG_BASE_GET (&R_GPIO->P_20)
#define GPIO_RZ_PM_REG_BASE_GET (&R_GPIO->PM_20)
#define GPIO_RZ_PFC_REG_BASE_GET (&R_GPIO->PFC_20)
#define GPIO_RZ_MAX_PORT_NUM 19
#define GPIO_RZ_TINT_IRQ_OFFSET 429
#define R_INTC R_INTC_IM33
#define GPIO_RZ_TINT_STATUS_REG_CLEAR(tint_num) (R_INTC_IM33->TSCR &= ~BIT(tint_num))
static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23, 28, 33, 38, 43,
47, 52, 56, 58, 63, 66, 70, 72, 76};
#elif defined(CONFIG_SOC_SERIES_RZA3UL)
#define GPIO_RZ_P_REG_BASE_GET (&R_GPIO->P10)
#define GPIO_RZ_PM_REG_BASE_GET (&R_GPIO->PM10)
#define GPIO_RZ_PFC_REG_BASE_GET (&R_GPIO->PFC10)
#define GPIO_RZ_MAX_PORT_NUM 19
#define GPIO_RZ_TINT_IRQ_OFFSET 476
#define R_INTC R_INTC_IA55
#define GPIO_RZ_P_REG_BASE_GET (&R_GPIO->P10)
#define GPIO_RZ_PM_REG_BASE_GET (&R_GPIO->PM10)
#define GPIO_RZ_PFC_REG_BASE_GET (&R_GPIO->PFC10)
#define GPIO_RZ_MAX_PORT_NUM 19
#define GPIO_RZ_TINT_IRQ_OFFSET 476
#define R_INTC R_INTC_IA55
#define GPIO_RZ_TINT_STATUS_REG_CLEAR(tint_num) (R_INTC_IA55->TSCR &= ~BIT(tint_num))
static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23, 28, 33, 38, 43,
47, 52, 56, 58, 63, 66, 70, 72, 76};
#elif defined(CONFIG_SOC_SERIES_RZV2H)
#define GPIO_RZ_P_REG_BASE_GET (&R_GPIO->P20)
#define GPIO_RZ_PM_REG_BASE_GET (&R_GPIO->PM20)
#define GPIO_RZ_PFC_REG_BASE_GET (&R_GPIO->PFC20)
#define GPIO_RZ_TINT_STATUS_REG_GET (&R_INTC->TSCTR)
#ifdef CONFIG_CPU_CORTEX_M
#define GPIO_RZ_TINT_IRQ_OFFSET 353
#define GPIO_RZ_TINT_SPURIOUS_HANDLE 0
#define GPIO_RZ_TINT_SELECT_SOURCE_REG_GET (&R_INTC->INTM33SEL0)
#else /* Cortex-R */
#define GPIO_RZ_TINT_IRQ_OFFSET (GIC_SPI_INT_BASE + 353)
#define GPIO_RZ_TINT_SELECT_SOURCE_REG_GET (&R_INTC->INTR8SEL0)
#endif
#define GPIO_RZ_MAX_PORT_NUM 12
#define GPIO_RZ_TINT_STATUS_REG_CLEAR(tint_num) (R_INTC->TSCLR |= BIT(tint_num))
#define GPIO_RZ_TINT_SELECT_SOURCE_REG_CLEAR(tint_num) \
GPIO_RZ_TINT_SELECT_SOURCE_REG_GET[int_num / 3] &= ~(0x3FF << ((int_num % 3) * 10));
#define GPIO_RZ_TINT_SELECT_SOURCE_REG_SET(tint_num) \
GPIO_RZ_TINT_SELECT_SOURCE_REG_GET[int_num / 3] |= (int_num << ((int_num % 3) * 10));
static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 8, 14, 16, 24, 32,
40, 48, 56, 64, 72, 80};
#elif defined(CONFIG_SOC_SERIES_RZV2L) || defined(CONFIG_SOC_SERIES_RZG2L)
#define GPIO_RZ_P_REG_BASE_GET (&R_GPIO->P10)
#define GPIO_RZ_PM_REG_BASE_GET (&R_GPIO->PM10)
#define GPIO_RZ_PFC_REG_BASE_GET (&R_GPIO->PFC10)
#define GPIO_RZ_MAX_PORT_NUM 49
#define GPIO_RZ_TINT_IRQ_OFFSET 444
#define R_INTC R_INTC_IM33
#define GPIO_RZ_P_REG_BASE_GET (&R_GPIO->P10)
#define GPIO_RZ_PM_REG_BASE_GET (&R_GPIO->PM10)
#define GPIO_RZ_PFC_REG_BASE_GET (&R_GPIO->PFC10)
#define GPIO_RZ_MAX_PORT_NUM 49
#define GPIO_RZ_TINT_IRQ_OFFSET 444
#define R_INTC R_INTC_IM33
#define GPIO_RZ_TINT_STATUS_REG_CLEAR(tint_num) (R_INTC_IM33->TSCR &= ~BIT(tint_num))
static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {
0, 2, 4, 6, 8, 10, 13, 15, 18, 21, 24, 25, 27, 29, 32, 34, 36,
38, 41, 43, 45, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72,
74, 76, 78, 80, 83, 85, 88, 91, 93, 98, 102, 106, 110, 114, 118};
#endif
#ifndef GPIO_RZ_TINT_SELECT_SOURCE_REG_CLEAR
#define GPIO_RZ_TINT_SELECT_SOURCE_REG_CLEAR(tint_num)
#define GPIO_RZ_TINT_SELECT_SOURCE_REG_SET(tint_num)
#endif
#ifndef GPIO_RZ_TINT_STATUS_REG_GET
#define GPIO_RZ_TINT_STATUS_REG_GET (&R_INTC->TSCR)
#endif
#ifndef GPIO_RZ_TINT_SPURIOUS_HANDLE
#define GPIO_RZ_TINT_SPURIOUS_HANDLE 1
#endif
#define GPIO_RZ_P_REG_GET(port, pin) (&GPIO_RZ_P_REG_BASE_GET[port])
#define GPIO_RZ_PM_REG_GET(port, pin) (&GPIO_RZ_PM_REG_BASE_GET[port])
#define GPIO_RZ_PFC_REG_GET(port, pin) (&GPIO_RZ_PFC_REG_BASE_GET[port])
@ -60,7 +102,8 @@ static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {
#define GPIO_RZ_MAX_INT_NUM 32
#define GPIO_RZ_TINT_IRQ_GET(tint_num) (tint_num + GPIO_RZ_TINT_IRQ_OFFSET)
#define GPIO_RZ_TINT_IRQ_GET(tint_num) (tint_num + GPIO_RZ_TINT_IRQ_OFFSET)
#define GPIO_RZ_TINT_CLEAR_PENDING(tint_num) R_BSP_IrqClearPending(GPIO_RZ_TINT_IRQ_GET(tint_num))
#define GPIO_RZ_INT_EDGE_RISING 0x0
#define GPIO_RZ_INT_EDGE_FALLING 0x1
@ -116,6 +159,7 @@ static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {
#define GPIO_RZ_INT_LEVEL_HIGH GPIO_RZ_INT_UNSUPPORTED
#define GPIO_RZ_INT_ENABLE (1U << 3)
#define GPIO_RZ_INT_DISABLE (~(1U << 3))
#define GPIO_RZ_TINT_CLEAR_PENDING(int_num)
#define GPIO_RZ_FLAG_GET_CONFIG(flag) (((flag >> RZTN_GPIO_DRCTL_SHIFT) & 0x33) << 8U)
#define GPIO_RZ_FLAG_SET_PFC(value) (value << 4)

124
dts/arm/renesas/rz/rzv/r9a09g057_cm33.dtsi
View file

@ -36,6 +36,130 @@
compatible = "renesas,rzv-pinctrl";
reg = <0x40410000 DT_SIZE_K(64)>;
reg-names = "pinctrl";
gpio: gpio-common {
compatible = "renesas,rz-gpio-int";
interrupts =
<353 10>, <354 10>, <355 10>, <356 10>,
<357 10>, <358 10>, <359 10>, <360 10>,
<361 10>, <362 10>, <363 10>, <364 10>,
<365 10>, <366 10>, <367 10>, <368 10>,
<369 10>, <370 10>, <371 10>, <372 10>,
<373 10>, <374 10>, <375 10>, <376 10>,
<377 10>, <378 10>, <379 10>, <380 10>,
<381 10>, <382 10>, <383 10>, <384 10>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
gpio0: gpio@0 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0x0>;
status = "disabled";
};
gpio1: gpio@100 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <6>;
reg = <0x100>;
status = "disabled";
};
gpio2: gpio@200 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <2>;
reg = <0x200>;
status = "disabled";
};
gpio3: gpio@300 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0x300>;
status = "disabled";
};
gpio4: gpio@400 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0x400>;
status = "disabled";
};
gpio5: gpio@500 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0x500>;
status = "disabled";
};
gpio6: gpio@600 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0x600>;
status = "disabled";
};
gpio7: gpio@700 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0x700>;
status = "disabled";
};
gpio8: gpio@800 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0x800>;
status = "disabled";
};
gpio9: gpio@900 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0x900>;
status = "disabled";
};
gpio10: gpio@a00 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0xa00>;
status = "disabled";
};
gpio11: gpio@b00 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <6>;
reg = <0xb00>;
status = "disabled";
};
};
};
sci0: sci0@42800c00 {