Use `DT_REG_ADDR_BY_NAME` and `DT_REG_SIZE_BY_NAME` to access register
properties from dts.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Adds addresses and names for individual CSR registers to device tree.
This way liteuart driver no longer depends on CSR data width being 8
bits.
Also when register names or their number changes, then overlay generated
by LiteX will be incompatible with one defined here.
This should make finding breaking changes easier.
I also appended `_ADDR` suffix to defines, to distinguish them from
normal values like `LITEETH_EV_RX`.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Adds addresses and names for individual CSR registers to device tree.
This way liteuart driver no longer depends on CSR data width being 8
bits.
Also when register names or their number changes, then overlay generated
by LiteX will be incompatible with one defined here.
This should make finding breaking changes easier.
I also appended `_ADDR` suffix to defines, to distinguish them from
normal values like `UART_EX_TX`.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Adds addresses and names for individual CSR registers to device tree.
This way timer driver no longer depends on CSR data width being 8 bits.
Also when register names their number changes, then overlay generated by
LiteX will be incompatible with one defined here.
This should make finding breaking changes easier.
I also updated register names to those used in current LiteX and
appended `_ADDR` suffix to defines which lacked them.
Because register `total` was renamed to `value` and `update_total` to
`update_value` I updated variables accordingly as well.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Host might send command or data immediately after EC read the
KBC input buffer (IBF gets cleared).
This change make sure EC won't get wrong event type in IBF ISR.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Move period and pulse computation to right before
the channel enable code.
That fixes the inability to disable the channel by
providing the period of 0.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
The STM32u% series of processors has a unique set of clock sources for
the FDCAN peripheral. This brings the selection in line with the
existing can_stm32fd clock selection Kconfigs.
This change was tested on a proprietary board using the STM32U5 series
which exposes the CAN pins of the SOC using a transciever on a live CAN
bus as well as on the nucleo_g474re board from ST in loopback mode.
HSE and PLL1Q tests run and all passed.
PLL2P is not currently supported by the clock drivers for STM32U5, and
as such is currently untested. When this support is added, the driver
should be able to use this clock without issue.
When changes from #42097 are merged this fix should be deprecated in
favor of using the methods outlined there.
Signed-off-by: Peter Maxwell Warasila <madmaxwell@soundcomesout.com>
Set the PCR[MUX] field to kPORT_MuxAsGpio as part of configuring a GPIO
pin. This removes the need to explicitly call pinmux_pin_set() in board
code.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Adds a log backend that maintains a ringbuffer in coordination
with cAVS HDA.
The DMA channel is expected to be given some time after the logger
starts so a seperate step to initialize the dma channel is required.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Do not default FLASH_MCUX_FLEXSPI_XIP to enabled when code is not
located in flash, this will cause issues if code is executing from ITCM,
as the zephyr_code_relocate macro will relocate the flash driver code
into itcm, and overwrite the zephyr image.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Do not query SIM card parameters if the SIM
card is not present.
This shortens the driver initialization time
significantly if a SIM card is not present.
Signed-off-by: Ryan Erickson <ryan.erickson@lairdconnect.com>
Store sensor trigger structure reference provided on `trigger_set`, and
pass reference back to client when trigger callback is invoked.
This will enable client to use `CONTAINER_OF()` inside its trigger
callback code.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Add support for missing EHL SKUs. The information about SKUs is
already public and available in Linux kernel:
https://github.com/torvalds/linux/blob/
38f80f42147ff658aff218edb0a88c37e58bf44f/drivers/edac/
igen6_edac.c#L197-L208
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Add optional PINCTRL support to the Microchip XEC PS2 driver
shared between MEC15xx and MEC172x families.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Update the Microchip XEC PS2 driver to support MEC172x.
NOTE: MEC15xx has two PS2 controllers and
MEC172x has one.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
since the flexspi driver interacts with the flash device, storing
device data in flash can cause RWW hazards when running in XIP mode.
Move all device data to RAM to limit these RWW hazards.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
since the flexspi driver interacts with the flash device, storing
device data in flash can cause RWW hazards when running in XIP mode.
Move all device data to RAM to limit these RWW hazards.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Move all device data to RAM. Since the flexspi driver accesses the
flash device that is being used for XIP, various RWW hazards can occur
if the flexspi driver is interacting with the flash device, while
running in XIP mode.
Fixes#45182
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Comparator will monitor signal though ADC channel, based on
user configuration, callback will be triggered.
This will enable comparator functionality for nuvoton MCU utilizing its
ADC threshold detection feature. Implementation is exported through
sensor trigger API. Use of CONFIG_ADC_CMP_NPCX is required.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Refactor code so that an unused variable 'adc' warning
is not generated when building for CONFIG_SOC_SERIES_STM32G4X
and not using adc1 or adc5.
Signed-off-by: Sam Hurst <sbh1187@gmail.com>
Refactor the Bosch M_CAN shared driver functions to get rid of the
front-end driver wrapper functions.
This requires flipping the relationship between shared config/data
structs and front-end config/data structs. Front-end drivers can now
store a pointer to their custom config/data structs in the .custom
fields of the can_mcan_config and can_mcan_data data structures.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rename the private header file for the Bosch M_CAN shared driver code
from can_mcan_int.h to can_mcan_priv.h to follow the common naming
scheme.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
update help text for mcux rt pinctrl peripheral driver, to clarify it
does not support RT600/RT500 parts and only RT1xxx series parts.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
add support for setting pinmux when using IOPCTL peripheral, as well as
setting pin configuration properties.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
add pincontrol headers for IOCON peripheral present on NXP iMX RT600
and RT500 SOCs, and update LPC pin control driver for iMX RT family
differences.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This modification is required to enable flash encryption.
Using hal implementation of spi_flash calls maintains
compability amongs different socs while offering
latest esp-idf enhancements.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Includes the definition of the STM32_DMA_STREAM_OFFSET
depending on the peripheral to adjust the first DMA channel
in the list of streams.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In the EC application, the system may jump between two built Zephyr
images when necessary. If we gate the eSPI clock at initialzation, it
will make the eSPI configuration which established by previous image
break and lost the communication between EC and host.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
remove existing SDMMC SPI driver, since it is replaced by the SPI mode
SD host controller driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
with the legacy USDHC driver fully removed from the tree, the
nxp,imx-usdhc binding can now be used for the new SD host controller
driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
all in tree SOCs with the USDHC peripheral have now been converted to
use the new SD host controller USDHC driver, so remove legacy NXP disk
USDHC driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add SDHC driver implementing spi mode support for SD cards. This driver
implements the standard SD host controller APIs, and sets the host
property "is_spi" to indicate to the SD subsystem the card will be
running in SPI mode.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Implement SDHC driver for NXP USDHC peripheral, supporting all api calls
available in the sdhc driver. This implementation leverages NXP's HAL,
and simply implements a shim layer over the HAL itself.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
LiteX CSRs can only be accessed on addresses aligned to 4 bytes.
That's why in 32-bit CSRs case there is bit shifting needed.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Removed register sizes from config struct, as they are known.
This allowed to remove driver specific function reading from CSR and use
`litex_write*` functions from LiteX HAL.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
