driver: spi: esp32: update flash driver to use hal
This modification is required to enable flash encryption. Using hal implementation of spi_flash calls maintains compability amongs different socs while offering latest esp-idf enhancements. Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This commit is contained in:
Sylvio Alves
Maureen Helm
parent
c2db84ee8a
commit
6c6b688b91
5 changed files with 21 additions and 700 deletions
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@ -54,7 +54,6 @@ LOG_MODULE_REGISTER(flash_esp32, CONFIG_FLASH_LOG_LEVEL);
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struct flash_esp32_dev_config {
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spi_dev_t *controller;
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esp_rom_spiflash_chip_t *chip;
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};
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struct flash_esp32_dev_data {
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@ -66,36 +65,6 @@ static const struct flash_parameters flash_esp32_parameters = {
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.erase_value = 0xff,
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};
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#if !defined(CONFIG_SOC_ESP32C3)
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#define SPI1_EXTRA_DUMMIES (g_rom_spiflash_dummy_len_plus[1])
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#else
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#define SPI1_EXTRA_DUMMIES ((uint8_t)((rom_spiflash_legacy_data->dummy_len_plus)[1]))
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#define SPI_FREAD_QIO 0
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#define SPI_FREAD_DIO 0
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#endif
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#define MAX_BUFF_ALLOC_RETRIES 5
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#define MAX_READ_CHUNK 16384
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#define MAX_WRITE_CHUNK 8192
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#define ADDRESS_MASK_24BIT 0xFFFFFF
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#define SPI_TIMEOUT_MSEC 500
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#if defined(CONFIG_SOC_ESP32)
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#define HOST_FLASH_CONTROLLER SPI0
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#define HOST_FLASH_RDSR SPI_FLASH_RDSR
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#define HOST_FLASH_FASTRD SPI_FASTRD_MODE
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#elif defined(CONFIG_SOC_ESP32S2) || defined(CONFIG_SOC_ESP32C3)
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#define HOST_FLASH_CONTROLLER SPIMEM0
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#define HOST_FLASH_RDSR SPI_MEM_FLASH_RDSR
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#define HOST_FLASH_FASTRD SPI_MEM_FASTRD_MODE
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#endif
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#if defined(CONFIG_SOC_ESP32C3)
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static esp_rom_spiflash_chip_t esp_flashchip_info;
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#else
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#define esp_flashchip_info g_rom_flashchip
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#endif
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static inline void flash_esp32_sem_take(const struct device *dev)
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{
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struct flash_esp32_dev_data *data = dev->data;
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@ -110,511 +79,12 @@ static inline void flash_esp32_sem_give(const struct device *dev)
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k_sem_give(&data->sem);
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}
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static inline int flash_esp32_wait_cmd_done(const spi_dev_t *hw)
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{
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int64_t timeout = k_uptime_get() + SPI_TIMEOUT_MSEC;
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while (!spi_flash_ll_cmd_is_done(hw)) {
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if (k_uptime_get() > timeout) {
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LOG_ERR("controller has timed out");
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return -ETIMEDOUT;
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}
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}
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return 0;
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}
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static inline bool points_to_dram(const void *ptr)
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{
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return ((intptr_t)ptr >= SOC_DRAM_LOW && (intptr_t)ptr < SOC_DRAM_HIGH);
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}
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int configure_read_mode(spi_dev_t *hw,
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uint32_t cmd,
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uint32_t addr_bitlen,
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int dummy_len,
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bool byte_cmd)
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{
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if (dummy_len) {
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spi_flash_ll_set_dummy(hw, dummy_len);
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}
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spi_flash_ll_set_addr_bitlen(hw, addr_bitlen);
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if (!byte_cmd) {
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REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, cmd);
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} else {
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spi_flash_ll_set_command(hw, (uint8_t) cmd, 8);
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}
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return 0;
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}
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static bool IRAM_ATTR flash_esp32_mapped_in_cache(uint32_t phys_page, const void **out_ptr)
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{
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int start[2], end[2];
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*out_ptr = NULL;
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/* SPI_FLASH_MMAP_DATA */
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start[0] = SOC_MMU_DROM0_PAGES_START;
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end[0] = SOC_MMU_DROM0_PAGES_END;
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/* SPI_FLASH_MMAP_INST */
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start[1] = SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE;
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end[1] = SOC_MMU_IROM0_PAGES_END;
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DPORT_INTERRUPT_DISABLE();
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for (int j = 0; j < 2; j++) {
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for (int i = start[j]; i < end[j]; i++) {
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if (DPORT_SEQUENCE_REG_READ(
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(uint32_t)&SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE[i]) ==
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SOC_MMU_PAGE_IN_FLASH(phys_page)) {
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#if !defined(CONFIG_SOC_ESP32)
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if (j == 0) { /* SPI_FLASH_MMAP_DATA */
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*out_ptr = (const void *)(SOC_MMU_VADDR0_START_ADDR +
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SPI_FLASH_MMU_PAGE_SIZE * (i - start[0]));
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} else {
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*out_ptr = (const void *)(SOC_MMU_VADDR1_FIRST_USABLE_ADDR +
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SPI_FLASH_MMU_PAGE_SIZE * (i - start[1]));
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}
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#endif
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DPORT_INTERRUPT_RESTORE();
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return true;
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}
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}
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}
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DPORT_INTERRUPT_RESTORE();
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return false;
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}
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/* Validates if flash address has corresponding cache mapping, if yes, flushes cache memories */
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static void IRAM_ATTR flash_esp32_flush_cache(size_t start_addr, size_t length)
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{
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/* align start_addr & length to full MMU pages */
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uint32_t page_start_addr = start_addr & ~(SPI_FLASH_MMU_PAGE_SIZE-1);
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length += (start_addr - page_start_addr);
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length = (length + SPI_FLASH_MMU_PAGE_SIZE - 1) & ~(SPI_FLASH_MMU_PAGE_SIZE-1);
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for (uint32_t addr = page_start_addr;
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addr < page_start_addr + length;
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addr += SPI_FLASH_MMU_PAGE_SIZE) {
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uint32_t page = addr / SPI_FLASH_MMU_PAGE_SIZE;
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if (page >= 256) {
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return;
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}
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const void *vaddr = NULL;
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if (flash_esp32_mapped_in_cache(page, &vaddr)) {
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#if defined(CONFIG_SOC_ESP32)
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#if CONFIG_ESP_SPIRAM
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esp_spiram_writeback_cache();
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#endif
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esp_rom_Cache_Flush(0);
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#ifdef CONFIG_SMP
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esp_rom_Cache_Flush(1);
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#endif
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return;
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#else /* CONFIG_SOC_ESP32 */
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if (vaddr != NULL) {
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esp_rom_Cache_Invalidate_Addr((uint32_t)vaddr,
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SPI_FLASH_MMU_PAGE_SIZE);
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}
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#endif /* CONFIG_SOC_ESP32 */
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}
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}
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return;
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}
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static int set_read_options(const struct device *dev)
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{
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const struct flash_esp32_dev_config *config = dev->config;
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spi_dev_t *hw = config->controller;
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uint32_t dummy_len = 0;
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uint32_t addr_len;
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uint8_t read_cmd;
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bool byte_cmd = true;
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uint32_t read_mode = READ_PERI_REG(PERIPHS_SPI_FLASH_CTRL);
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if ((read_mode & SPI_FREAD_QIO) && (read_mode & HOST_FLASH_FASTRD)) {
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spi_ll_enable_mosi(hw, 0);
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spi_ll_enable_miso(hw, 1);
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dummy_len = 1 + SPI1_R_QIO_DUMMY_CYCLELEN + SPI1_EXTRA_DUMMIES;
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addr_len = SPI1_R_QIO_ADDR_BITSLEN + 1;
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read_cmd = CMD_FASTRD_QIO;
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} else if (read_mode & HOST_FLASH_FASTRD) {
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spi_ll_enable_mosi(hw, 0);
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spi_ll_enable_miso(hw, 1);
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if (read_mode & SPI_FREAD_DIO) {
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read_cmd = CMD_FASTRD_DIO;
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if (SPI1_EXTRA_DUMMIES == 0) {
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spi_flash_ll_set_dummy(hw, 0);
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addr_len = SPI1_R_DIO_ADDR_BITSLEN + 1;
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} else {
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byte_cmd = false;
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dummy_len = SPI1_EXTRA_DUMMIES;
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addr_len = SPI1_R_DIO_ADDR_BITSLEN + 1;
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}
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} else {
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if ((read_mode & SPI_FREAD_QUAD)) {
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read_cmd = CMD_FASTRD_QUAD;
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} else if ((read_mode & SPI_FREAD_DUAL)) {
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read_cmd = CMD_FASTRD_DUAL;
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} else {
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read_cmd = CMD_FASTRD;
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}
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dummy_len = 1 + SPI1_R_FAST_DUMMY_CYCLELEN + SPI1_EXTRA_DUMMIES;
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addr_len = SPI1_R_FAST_ADDR_BITSLEN + 1;
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}
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} else {
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spi_ll_enable_mosi(hw, 0);
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if (SPI1_EXTRA_DUMMIES == 0) {
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spi_flash_ll_set_dummy(hw, 0);
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} else {
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dummy_len = SPI1_EXTRA_DUMMIES;
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}
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spi_ll_enable_miso(hw, 1);
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addr_len = SPI1_R_SIO_ADDR_BITSLEN + 1;
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read_cmd = CMD_READ;
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}
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return configure_read_mode(hw, read_cmd, addr_len, dummy_len, byte_cmd);
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}
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static int read_once(const struct device *dev, void *buffer, uint32_t address, uint32_t read_len)
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{
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const struct flash_esp32_dev_config *config = dev->config;
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spi_dev_t *hw = config->controller;
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int bitlen = spi_flash_ll_get_addr_bitlen(hw);
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spi_flash_ll_set_usr_address(hw, address << (bitlen - 24), bitlen);
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spi_flash_ll_set_miso_bitlen(hw, read_len * 8);
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spi_flash_ll_user_start(hw);
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int rc = flash_esp32_wait_cmd_done(hw);
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if (rc != 0) {
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return rc;
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}
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spi_flash_ll_get_buffer_data(hw, buffer, read_len);
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return 0;
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}
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static int read_data(const struct device *dev, uint8_t *buffer, uint32_t address, uint32_t length)
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{
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int rc = 0;
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rc = set_read_options(dev);
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if (rc == -ENOTSUP) {
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LOG_ERR("configure host io mode failed - unsupported");
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return rc;
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}
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while (rc == 0 && length > 0) {
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uint32_t read_len = MIN(length, SPI_FLASH_HAL_MAX_READ_BYTES);
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rc = read_once(dev, buffer, address, read_len);
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address += read_len;
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length -= read_len;
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buffer += read_len;
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}
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return rc;
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}
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static int flash_esp32_read(const struct device *dev, off_t address, void *buffer, size_t length)
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{
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const struct flash_esp32_dev_config *const cfg = dev->config;
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const spi_flash_guard_funcs_t *guard = spi_flash_guard_get();
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uint32_t chip_size = cfg->chip->chip_size;
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#if defined(CONFIG_SOC_ESP32S2) || defined(CONFIG_SOC_ESP32C3)
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_CTRL, 0);
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#endif
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if (length == 0) {
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return 0;
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}
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if (buffer == NULL || address > chip_size || address + length > chip_size) {
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return -EINVAL;
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}
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bool direct_read = points_to_dram(buffer);
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uint8_t *temp_buff = NULL;
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size_t read_chunk = MIN(MAX_READ_CHUNK, length);
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size_t temp_chunk = MAX_READ_CHUNK;
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int rc = 0;
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flash_esp32_sem_take(dev);
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if (!direct_read) {
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unsigned int retries = MAX_BUFF_ALLOC_RETRIES;
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while (temp_buff == NULL && retries--) {
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read_chunk = MIN(read_chunk, temp_chunk);
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temp_chunk >>= 1;
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read_chunk = (read_chunk + 3) & ~3;
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temp_buff = k_malloc(read_chunk);
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}
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LOG_INF("allocate temp buffer: %p (%d)", temp_buff, read_chunk);
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if (temp_buff == NULL) {
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rc = -ENOMEM;
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goto out;
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}
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}
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uint8_t *buff = (uint8_t *)buffer;
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do {
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guard->start();
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uint8_t *read_buff = (temp_buff) ? temp_buff : buffer;
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size_t read_len = MIN(read_chunk, length);
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rc = read_data(dev, read_buff, address, read_len);
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if (rc) {
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guard->end();
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break;
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}
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guard->end();
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if (temp_buff) {
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memcpy(buffer, temp_buff, read_len);
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}
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address += read_len;
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length -= read_len;
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buff += read_len;
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buffer = (void *)buff;
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} while (rc == 0 && length > 0);
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k_free(temp_buff);
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out:
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int ret = spi_flash_read(address, buffer, length);
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flash_esp32_sem_give(dev);
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return rc;
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}
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static inline void set_write_options(const struct device *dev)
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{
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const struct flash_esp32_dev_config *config = dev->config;
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spi_dev_t *hw = config->controller;
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spi_flash_ll_set_dummy(hw, 0);
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/* only single line flash write is currently supported */
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spi_flash_ll_set_addr_bitlen(hw, (1 + ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN));
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}
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static int read_status(const struct device *dev, uint32_t *status)
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{
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const struct flash_esp32_dev_config *const cfg = dev->config;
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uint32_t status_value = ESP_ROM_SPIFLASH_BUSY_FLAG;
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if (SPI1_EXTRA_DUMMIES == 0) {
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while (ESP_ROM_SPIFLASH_BUSY_FLAG ==
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(status_value & ESP_ROM_SPIFLASH_BUSY_FLAG)) {
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_STATUS, 0);
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, HOST_FLASH_RDSR);
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int rc = flash_esp32_wait_cmd_done(cfg->controller);
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if (rc != 0) {
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return rc;
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}
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status_value = READ_PERI_REG(PERIPHS_SPI_FLASH_STATUS);
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status_value &= cfg->chip->status_mask;
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}
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} else {
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while (ESP_ROM_SPIFLASH_BUSY_FLAG == (status_value & ESP_ROM_SPIFLASH_BUSY_FLAG)) {
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esp_rom_spiflash_read_user_cmd(&status_value, CMD_RDSR);
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}
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}
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*status = status_value;
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return 0;
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}
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static inline bool host_idle(spi_dev_t *hw)
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{
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#if defined(CONFIG_SOC_ESP32)
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bool idle = spi_flash_ll_host_idle(hw);
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idle &= spi_flash_ll_host_idle(&HOST_FLASH_CONTROLLER);
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#elif defined(CONFIG_SOC_ESP32S2) || defined(CONFIG_SOC_ESP32C3)
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bool idle = spimem_flash_ll_host_idle((spi_mem_dev_t *)hw);
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idle &= spimem_flash_ll_host_idle(&HOST_FLASH_CONTROLLER);
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#endif
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return idle;
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}
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static int wait_idle(const struct device *dev)
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{
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const struct flash_esp32_dev_config *const cfg = dev->config;
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uint32_t status;
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int64_t timeout = k_uptime_get() + SPI_TIMEOUT_MSEC;
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/* wait for spi control ready */
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while (!host_idle(cfg->controller)) {
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if (k_uptime_get() > timeout) {
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return -ETIMEDOUT;
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}
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}
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/* wait for flash status ready */
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if (read_status(dev, &status) != 0) {
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return -EINVAL;
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}
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return 0;
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}
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static int write_protect(const struct device *dev, bool write_protect)
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{
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const struct flash_esp32_dev_config *const cfg = dev->config;
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wait_idle(dev);
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/* enable writing */
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spi_flash_ll_set_write_protect(cfg->controller, write_protect);
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int rc = flash_esp32_wait_cmd_done(cfg->controller);
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if (rc != 0) {
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return rc;
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}
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#if !defined(CONFIG_SOC_ESP32C3)
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uint32_t flash_status = 0;
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/* make sure the flash is ready for writing */
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while (ESP_ROM_SPIFLASH_WRENABLE_FLAG != (flash_status & ESP_ROM_SPIFLASH_WRENABLE_FLAG)) {
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read_status(dev, &flash_status);
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}
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#endif
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return 0;
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}
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static int program_page(const struct device *dev, uint32_t spi_addr,
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uint32_t *addr_source, int32_t byte_length)
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{
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const struct flash_esp32_dev_config *config = dev->config;
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const uint32_t page_size = config->chip->page_size;
|
||||
spi_dev_t *hw = config->controller;
|
||||
|
||||
/* check 4byte alignment */
|
||||
if ((byte_length & 0x3) != 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* check if write in one page */
|
||||
if (page_size < ((spi_addr % page_size) + byte_length)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
wait_idle(dev);
|
||||
|
||||
uint32_t addr;
|
||||
uint32_t prog_len;
|
||||
|
||||
while (byte_length > 0) {
|
||||
if (write_protect(dev, false) != 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
addr = spi_addr & ADDRESS_MASK_24BIT;
|
||||
|
||||
if (byte_length >= ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM) {
|
||||
addr |= ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM << ESP_ROM_SPIFLASH_BYTES_LEN;
|
||||
prog_len = (uint32_t)ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM;
|
||||
spi_flash_ll_set_address(hw, addr);
|
||||
spi_flash_ll_program_page(hw, addr_source, prog_len);
|
||||
byte_length -= ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM;
|
||||
spi_addr += ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM;
|
||||
} else {
|
||||
addr |= byte_length << ESP_ROM_SPIFLASH_BYTES_LEN;
|
||||
prog_len = (uint32_t)byte_length;
|
||||
spi_flash_ll_set_address(hw, addr);
|
||||
spi_flash_ll_program_page(hw, addr_source, prog_len);
|
||||
byte_length = 0;
|
||||
}
|
||||
|
||||
addr_source += (ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM/4);
|
||||
|
||||
int rc = flash_esp32_wait_cmd_done(hw);
|
||||
|
||||
if (rc != 0) {
|
||||
return rc;
|
||||
}
|
||||
|
||||
wait_idle(dev);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int flash_esp32_write_inner(const struct device *dev,
|
||||
uint32_t address,
|
||||
const uint32_t *buffer,
|
||||
size_t length)
|
||||
{
|
||||
const struct flash_esp32_dev_config *config = dev->config;
|
||||
const uint32_t page_size = config->chip->page_size;
|
||||
const uint32_t chip_size = config->chip->chip_size;
|
||||
uint32_t prog_len, prog_num;
|
||||
|
||||
set_write_options(dev);
|
||||
|
||||
/* check program size */
|
||||
if ((address + length) > chip_size) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
prog_len = page_size - (address % page_size);
|
||||
if (length < prog_len) {
|
||||
if (program_page(dev, address, (uint32_t *)buffer, length) != 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
} else {
|
||||
if (program_page(dev, address, (uint32_t *)buffer, prog_len) != 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* whole page program */
|
||||
prog_num = (length - prog_len) / page_size;
|
||||
for (uint8_t i = 0; i < prog_num; ++i) {
|
||||
if (program_page(dev, address + prog_len,
|
||||
(uint32_t *)buffer + (prog_len >> 2),
|
||||
page_size) != 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
prog_len += page_size;
|
||||
}
|
||||
|
||||
/* remain parts to program */
|
||||
if (program_page(dev, address + prog_len,
|
||||
(uint32_t *)buffer + (prog_len >> 2),
|
||||
length - prog_len) != 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int flash_esp32_write(const struct device *dev,
|
||||
|
|
@ -622,165 +92,18 @@ static int flash_esp32_write(const struct device *dev,
|
|||
const void *buffer,
|
||||
size_t length)
|
||||
{
|
||||
const struct flash_esp32_dev_config *config = dev->config;
|
||||
const uint32_t chip_size = config->chip->chip_size;
|
||||
const spi_flash_guard_funcs_t *guard = spi_flash_guard_get();
|
||||
int rc = 0;
|
||||
|
||||
if (address + length > chip_size) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (length == 0) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
const uint8_t *srcc = (const uint8_t *) buffer;
|
||||
/*
|
||||
* Large operations are split into (up to) 3 parts:
|
||||
* - Left padding: 4 bytes up to the first 4-byte aligned destination offset.
|
||||
* - Middle part
|
||||
* - Right padding: 4 bytes from the last 4-byte aligned offset covered.
|
||||
*/
|
||||
size_t left_off = address & ~3U;
|
||||
size_t left_size = MIN(((address + 3) & ~3U) - address, length);
|
||||
size_t mid_off = left_size;
|
||||
size_t mid_size = (length - left_size) & ~3U;
|
||||
size_t right_off = left_size + mid_size;
|
||||
size_t right_size = length - mid_size - left_size;
|
||||
|
||||
flash_esp32_sem_take(dev);
|
||||
|
||||
if (left_size > 0) {
|
||||
uint32_t t = 0xffffffff;
|
||||
|
||||
memcpy(((uint8_t *) &t) + (address - left_off), srcc, left_size);
|
||||
guard->start();
|
||||
rc = flash_esp32_write_inner(dev, left_off, &t, 4);
|
||||
guard->end();
|
||||
if (rc != 0) {
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
if (mid_size > 0) {
|
||||
bool direct_write = esp_ptr_internal(srcc)
|
||||
&& esp_ptr_byte_accessible(srcc)
|
||||
&& ((uintptr_t) srcc + mid_off) % 4 == 0;
|
||||
|
||||
while (mid_size > 0 && rc == 0) {
|
||||
uint32_t write_buf[8];
|
||||
uint32_t write_size = MIN(mid_size, MAX_WRITE_CHUNK);
|
||||
const uint8_t *write_src = srcc + mid_off;
|
||||
|
||||
if (!direct_write) {
|
||||
write_size = MIN(write_size, sizeof(write_buf));
|
||||
memcpy(write_buf, write_src, write_size);
|
||||
write_src = (const uint8_t *)write_buf;
|
||||
}
|
||||
guard->start();
|
||||
rc = flash_esp32_write_inner(dev, address + mid_off,
|
||||
(const uint32_t *) write_src, write_size);
|
||||
guard->end();
|
||||
mid_size -= write_size;
|
||||
mid_off += write_size;
|
||||
}
|
||||
if (rc != 0) {
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
if (right_size > 0) {
|
||||
uint32_t t = 0xffffffff;
|
||||
|
||||
memcpy(&t, srcc + right_off, right_size);
|
||||
guard->start();
|
||||
rc = flash_esp32_write_inner(dev, address + right_off, &t, 4);
|
||||
guard->end();
|
||||
}
|
||||
|
||||
out:
|
||||
guard->start();
|
||||
flash_esp32_flush_cache(address, length);
|
||||
guard->end();
|
||||
int ret = spi_flash_write(address, buffer, length);
|
||||
flash_esp32_sem_give(dev);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int erase_sector(const struct device *dev, uint32_t start_addr)
|
||||
{
|
||||
const struct flash_esp32_dev_config *config = dev->config;
|
||||
spi_dev_t *hw = config->controller;
|
||||
int rc = write_protect(dev, false);
|
||||
|
||||
if (rc == 0) {
|
||||
rc = wait_idle(dev);
|
||||
}
|
||||
|
||||
if (rc == 0) {
|
||||
spi_flash_ll_set_addr_bitlen(hw, 24);
|
||||
spi_flash_ll_set_address(hw, start_addr & ADDRESS_MASK_24BIT);
|
||||
spi_flash_ll_erase_sector(hw);
|
||||
|
||||
rc = flash_esp32_wait_cmd_done(hw);
|
||||
if (rc) {
|
||||
return rc;
|
||||
}
|
||||
|
||||
rc = wait_idle(dev);
|
||||
if (rc) {
|
||||
LOG_ERR("waiting for host device idle state has failed");
|
||||
}
|
||||
}
|
||||
|
||||
return rc;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int flash_esp32_erase(const struct device *dev, off_t start, size_t len)
|
||||
{
|
||||
const struct flash_esp32_dev_config *config = dev->config;
|
||||
uint32_t sector_size = config->chip->sector_size;
|
||||
uint32_t chip_size = config->chip->chip_size;
|
||||
const spi_flash_guard_funcs_t *guard = spi_flash_guard_get();
|
||||
int rc = 0;
|
||||
|
||||
if (start % sector_size != 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
if (len % sector_size != 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
if (len + start > chip_size) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
flash_esp32_sem_take(dev);
|
||||
|
||||
set_write_options(dev);
|
||||
|
||||
while (len >= sector_size) {
|
||||
guard->start();
|
||||
|
||||
rc = erase_sector(dev, start);
|
||||
if (rc) {
|
||||
guard->end();
|
||||
goto out;
|
||||
}
|
||||
|
||||
start += sector_size;
|
||||
len -= sector_size;
|
||||
|
||||
guard->end();
|
||||
}
|
||||
|
||||
out:
|
||||
guard->start();
|
||||
flash_esp32_flush_cache(start, len);
|
||||
guard->end();
|
||||
|
||||
int ret = spi_flash_erase_range(start, len);
|
||||
flash_esp32_sem_give(dev);
|
||||
|
||||
return rc;
|
||||
return ret;
|
||||
}
|
||||
|
||||
#if CONFIG_FLASH_PAGE_LAYOUT
|
||||
|
|
@ -810,14 +133,6 @@ static int flash_esp32_init(const struct device *dev)
|
|||
{
|
||||
struct flash_esp32_dev_data *const dev_data = dev->data;
|
||||
|
||||
#if defined(CONFIG_SOC_ESP32C3)
|
||||
spiflash_legacy_data_t *legacy_data = rom_spiflash_legacy_data;
|
||||
|
||||
esp_flashchip_info.chip_size = legacy_data->chip.chip_size;
|
||||
esp_flashchip_info.sector_size = legacy_data->chip.sector_size;
|
||||
esp_flashchip_info.page_size = legacy_data->chip.page_size;
|
||||
#endif
|
||||
|
||||
k_sem_init(&dev_data->sem, 1, 1);
|
||||
|
||||
return 0;
|
||||
|
|
@ -837,7 +152,6 @@ static struct flash_esp32_dev_data flash_esp32_data;
|
|||
|
||||
static const struct flash_esp32_dev_config flash_esp32_config = {
|
||||
.controller = (spi_dev_t *) DT_INST_REG_ADDR(0),
|
||||
.chip = &esp_flashchip_info
|
||||
};
|
||||
|
||||
DEVICE_DT_INST_DEFINE(0, flash_esp32_init,
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue