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drivers: pinctrl: add OpenISA RV32M1 pinctrl driver

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Add OpenISA RV32M1 pinctrl driver.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This commit is contained in:
Henrik Brix Andersen 2022-05-01 22:28:29 +02:00 • committed by David Leach
commit 1dc3b237fa
5 changed files with 106 additions and 0 deletions
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1
drivers/pinctrl/CMakeLists.txt
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@ -19,3 +19,4 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_SIFIVE pinctrl_sifive.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_IOCON pinctrl_lpc_iocon.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_CC13XX_CC26XX pinctrl_cc13xx_cc26xx.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_ESP32 pinctrl_esp32.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_RV32M1 pinctrl_rv32m1.c)

1
drivers/pinctrl/Kconfig
View file

@ -44,5 +44,6 @@ source "drivers/pinctrl/Kconfig.sifive"
source "drivers/pinctrl/Kconfig.lpc_iocon"
source "drivers/pinctrl/Kconfig.cc13xx_cc26xx"
source "drivers/pinctrl/Kconfig.esp32"
source "drivers/pinctrl/Kconfig.rv32m1"
endif # PINCTRL

11
drivers/pinctrl/Kconfig.rv32m1 Normal file
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@ -0,0 +1,11 @@
# Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk>
# SPDX-License-Identifier: Apache-2.0
DT_COMPAT_OPENISA_RV32M1_PINCTRL := openisa,rv32m1-pinctrl
config PINCTRL_RV32M1
bool "RV32M1 pin controller driver"
depends on SOC_OPENISA_RV32M1_RISCV32
default $(dt_compat_enabled,$(DT_COMPAT_OPENISA_RV32M1_PINCTRL))
help
Enable the RV32M1 pin controller driver.

71
drivers/pinctrl/pinctrl_rv32m1.c Normal file
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@ -0,0 +1,71 @@
/*
* Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk>
* Copyright (c) 2022 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT openisa_rv32m1_pinmux
#include <zephyr/drivers/pinctrl.h>
#include <fsl_clock.h>
/* Port register addresses. */
static PORT_Type *ports[] = {
(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porta)),
(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portb)),
(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portc)),
(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portd)),
(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porte)),
};
#define PIN(mux) (((mux) & 0xFC00000) >> 22)
#define PORT(mux) (((mux) & 0xF0000000) >> 28)
#define PINCFG(mux) ((mux) & Z_PINCTRL_RV32M1_PCR_MASK)
struct pinctrl_rv32m1_config {
clock_ip_name_t clock_ip_name;
};
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
for (uint8_t i = 0; i < pin_cnt; i++) {
PORT_Type *base = ports[PORT(pins[i])];
uint8_t pin = PIN(pins[i]);
uint16_t mux = PINCFG(pins[i]);
base->PCR[pin] = (base->PCR[pin] & (~Z_PINCTRL_RV32M1_PCR_MASK)) | mux;
}
return 0;
}
/* RV32M1 pinmux driver binds to the same DTS nodes,
* and handles clock init. Only bind to these nodes if pinmux driver
* is disabled.
*/
#ifndef CONFIG_PINMUX
static int pinctrl_rv32m1_init(const struct device *dev)
{
const struct pinctrl_rv32m1_config *config = dev->config;
CLOCK_EnableClock(config->clock_ip_name);
return 0;
}
#define PINCTRL_RV32M1_INIT(n) \
static const struct pinctrl_rv32m1_config pinctrl_rv32m1_##n##_config = {\
.clock_ip_name = INST_DT_CLOCK_IP_NAME(n), \
}; \
\
DEVICE_DT_INST_DEFINE(n, \
&pinctrl_rv32m1_init, \
NULL, \
NULL, &pinctrl_rv32m1_##n##_config, \
PRE_KERNEL_1, \
1, \
NULL);
DT_INST_FOREACH_STATUS_OKAY(PINCTRL_RV32M1_INIT)
#endif