Refactor code so that an unused variable 'adc' warning
is not generated when building for CONFIG_SOC_SERIES_STM32G4X
and not using adc1 or adc5.
Signed-off-by: Sam Hurst <sbh1187@gmail.com>
Refactor the Bosch M_CAN shared driver functions to get rid of the
front-end driver wrapper functions.
This requires flipping the relationship between shared config/data
structs and front-end config/data structs. Front-end drivers can now
store a pointer to their custom config/data structs in the .custom
fields of the can_mcan_config and can_mcan_data data structures.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rename the private header file for the Bosch M_CAN shared driver code
from can_mcan_int.h to can_mcan_priv.h to follow the common naming
scheme.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
update help text for mcux rt pinctrl peripheral driver, to clarify it
does not support RT600/RT500 parts and only RT1xxx series parts.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
add support for setting pinmux when using IOPCTL peripheral, as well as
setting pin configuration properties.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
add pincontrol headers for IOCON peripheral present on NXP iMX RT600
and RT500 SOCs, and update LPC pin control driver for iMX RT family
differences.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This modification is required to enable flash encryption.
Using hal implementation of spi_flash calls maintains
compability amongs different socs while offering
latest esp-idf enhancements.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Includes the definition of the STM32_DMA_STREAM_OFFSET
depending on the peripheral to adjust the first DMA channel
in the list of streams.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In the EC application, the system may jump between two built Zephyr
images when necessary. If we gate the eSPI clock at initialzation, it
will make the eSPI configuration which established by previous image
break and lost the communication between EC and host.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
remove existing SDMMC SPI driver, since it is replaced by the SPI mode
SD host controller driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
with the legacy USDHC driver fully removed from the tree, the
nxp,imx-usdhc binding can now be used for the new SD host controller
driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
all in tree SOCs with the USDHC peripheral have now been converted to
use the new SD host controller USDHC driver, so remove legacy NXP disk
USDHC driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add SDHC driver implementing spi mode support for SD cards. This driver
implements the standard SD host controller APIs, and sets the host
property "is_spi" to indicate to the SD subsystem the card will be
running in SPI mode.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Implement SDHC driver for NXP USDHC peripheral, supporting all api calls
available in the sdhc driver. This implementation leverages NXP's HAL,
and simply implements a shim layer over the HAL itself.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
LiteX CSRs can only be accessed on addresses aligned to 4 bytes.
That's why in 32-bit CSRs case there is bit shifting needed.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Removed register sizes from config struct, as they are known.
This allowed to remove driver specific function reading from CSR and use
`litex_write*` functions from LiteX HAL.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Use LiteX HAL functions instead of `sys_read*` or `sys_write*`
functions.
They use them inside, but choose which one to use according to
configured CSR data width.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
With universal LiteX HAL working, there is no need to perform multibyte
reads and writes using bitwise operations.
Just use appropriate `litex_read*` or `litex_write*` function.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Use LiteX HAL functions instead of `sys_read*` or `sys_write*`
functions.
They use them inside, but choose which one to use according to
configured CSR data width.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Use LiteX HAL functions instead of `sys_read*` or `sys_write*`
functions.
They use them inside, but choose which one to use according to
configured CSR data width.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Changes signature so it takes uint32_t instead of pointer to a
register.
Later `sys_read*` and `sys_write*` functions are used, which cast
given address to volatile pointer anyway.
This required changing types of some fields in LiteX GPIO driver and
removal of two casts in clock control driver.
There was a weird assert from LiteX GPIO driver, which checked whether
size of first register in dts was a multiple of 4.
It didn't make much sense, so I removed it.
Previous dts was describing size of a register in terms of subregisters
used. New one uses size of register, so right now it is almost always
4 bytes.
Most drivers don't read register size from dts anyway, so only changes
had to be made in GPIO and clock control drivers.
Both use `litex_read` and `litex_write` to operate on `n`bytes.
Now GPIO driver calculates this `n` value in compile time from given
number of pins and stores it in `reg_size` field of config struct like
before.
Registe sizes in clock control driver are hardcoded, because they are
tied to LiteX wrapper anyway.
This makes it possible to have code, independent of CSR data width.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Make the LSE driving capability configurable for the STM32 series.
Fixes#44737.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Currently the driver only setup the ADC to read from the
internal temperature channel on init. However, it is possible
that some other application that uses the ADC can setup the
ADC to read from some other channel and therefore subsequent
stm32_temp_sample_fetch will fail to read the targeted channel.
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
The ADC should be calibrated on init, there is no requirement
to calibrate ADC again on stm32_temp_init, remove it.
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Change the default initialization priority for CAN transceiver from 70 to
45 to initialize them before the CAN controllers (with default a
initialization priority of 50).
Fixes: #45219
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This change is controlling of function parameters before
configuring the STM32_DMA_HAL_OVERRIDE mode.
Then, in case the DMA channel is not valid (wrong ID) or busy,
an error occurs before overriding the DMA channel.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fixing a bug where get_regs() was being executed before MMIO mapping
moving the declaration of reg_base after DEVICE_MMIO_MAP
Signed-off-by: Esteban Valverde <esteban.valverde.vega@intel.com>
Consolidate the initialization routines and change the include guard to
conform with the coding guidelines as a preparation for the following
commits which add support for the SPI interface.
Signed-off-by: Leonard Pollak <leonardp@tr-host.de>
This fixes the constant for the mem page and replaces a
magic number with the already defined `BME680_LEN_COEFF2` constant.
Signed-off-by: Leonard Pollak <leonardp@tr-host.de>
PWM has a single set function now, macros like PWM_USEC() can be used to
specify other units than nanoseconds. This conversion was missed during
API updates.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The pwm field in struct args_index was missed when pwm was renamed to
channel in all drivers. As a result, the PWM shell could no longer be
built.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The it8xxx2 watchdog Kconfig options are always shown, for every type
of device, they should only be shown when an it8xxx2 device is being
targeted.
Signed-off-by: Jamie McCrae <spam@helper3000.net>
Includes several driver fixes and improvement to leverage
scatter/gather mode of DMA. Loads multiple DMA blocks into TCDs.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
RX FIFO watermark setting causing issue where last 16 words received
were stuck in FIFO, and not requesting DMA to move to buffer. Fixed by
setting watermark to 0.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
driver config settings were getting overwritten by APIs that set
default settings, like SAI_GetClassicI2SConfig(). Moved config code
after those APIs.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
stream_disable()'s should not always purge buffers.
And i2s_rx_stream_disable() needs separate control for
purging in_queue and out_queue since app owns buffers
after placed in out_queue for i2s_read()
Signed-off-by: Derek Snell <derek.snell@nxp.com>
