drivers: i2s: mcux_sai: fixed SAI driver
Includes several driver fixes and improvement to leverage scatter/gather mode of DMA. Loads multiple DMA blocks into TCDs. Signed-off-by: Derek Snell <derek.snell@nxp.com>
This commit is contained in:
Derek Snell
Carles Cufí
parent
60dd576975
commit
16a09b026e
1 changed files with 314 additions and 157 deletions
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@ -33,8 +33,22 @@
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LOG_MODULE_REGISTER(LOG_DOMAIN);
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#define DT_DRV_COMPAT nxp_mcux_i2s
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#define NUM_DMA_BLOCKS_RX_PREP 3
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#define MAX_TX_DMA_BLOCKS CONFIG_DMA_TCD_QUEUE_SIZE
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#if (NUM_DMA_BLOCKS_RX_PREP >= CONFIG_DMA_TCD_QUEUE_SIZE)
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#error NUM_DMA_BLOCKS_RX_PREP must be < CONFIG_DMA_TCD_QUEUE_SIZE
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#endif
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#if defined(CONFIG_DMA_MCUX_EDMA) && (NUM_DMA_BLOCKS_RX_PREP < 3)
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#error eDMA avoids TCD coherency issue if NUM_DMA_BLOCKS_RX_PREP >= 3
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#endif
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/*
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* SAI driver uses source_gather_en/dest_scatter_en feature of DMA, and relies
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* on DMA driver managing circular list of DMA blocks. Like eDMA driver links
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* Transfer Control Descriptors (TCDs) in list, and manages the tcdpool.
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* Calling dma_reload() adds new DMA block to DMA channel already configured,
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* into the DMA driver's circular list of blocks.
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* This indicates the Tx/Rx stream.
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*
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* in_queue and out_queue are used as follows
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@ -58,9 +72,10 @@ struct stream {
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struct i2s_config cfg;
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struct dma_config dma_cfg;
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struct dma_block_config dma_block;
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uint8_t free_tx_dma_blocks;
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bool last_block;
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struct k_msgq in_queue;
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struct k_msgq out_queue;
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uint32_t stream_starving;
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};
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struct i2s_mcux_config {
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@ -97,7 +112,6 @@ struct i2s_dev_data {
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void *rx_out_msgs[CONFIG_I2S_RX_BLOCK_COUNT];
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};
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static void i2s_dma_tx_callback(const struct device *, void *,
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uint32_t, int);
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static void i2s_tx_stream_disable(const struct device *, bool drop);
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@ -148,8 +162,6 @@ static void i2s_tx_stream_disable(const struct device *dev, bool drop)
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/* Disable Tx */
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SAI_TxEnable(dev_cfg->base, false);
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strm->stream_starving = false;
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/* If Tx is disabled, reset the FIFO pointer, clear error flags */
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if ((dev_cfg->base->TCSR & I2S_TCSR_TE_MASK) == 0UL) {
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dev_cfg->base->TCSR |=
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@ -185,35 +197,82 @@ static void i2s_rx_stream_disable(const struct device *dev,
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/* Disable Rx */
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SAI_RxEnable(dev_cfg->base, false);
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/* wait for Receiver to disable */
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while (dev_cfg->base->RCSR & I2S_RCSR_RE_MASK)
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;
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/* reset the FIFO pointer and clear error flags */
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dev_cfg->base->RCSR |= (I2S_RCSR_FR_MASK | I2S_RCSR_SR_MASK);
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dev_cfg->base->RCSR &= ~I2S_RCSR_SR_MASK;
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/* purge buffers queued in the stream */
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if (in_drop || out_drop) {
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i2s_purge_stream_buffers(strm, dev_data->rx.cfg.mem_slab,
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in_drop, out_drop);
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}
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}
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strm->stream_starving = false;
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static int i2s_tx_reload_multiple_dma_blocks(const struct device *dev,
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uint8_t *blocks_queued)
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{
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struct i2s_dev_data *dev_data = dev->data;
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const struct i2s_mcux_config *dev_cfg = dev->config;
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I2S_Type *base = (I2S_Type *)dev_cfg->base;
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struct stream *strm = &dev_data->tx;
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void *buffer = NULL;
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int ret = 0;
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unsigned int key;
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/* If Rx is disabled, reset the FIFO pointer
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* and clear error flags
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*/
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if ((dev_cfg->base->RCSR & I2S_RCSR_RE_MASK) == 0UL) {
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dev_cfg->base->RCSR |=
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(I2S_RCSR_FR_MASK | I2S_RCSR_SR_MASK);
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dev_cfg->base->RCSR &= ~I2S_RCSR_SR_MASK;
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*blocks_queued = 0;
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key = irq_lock();
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/* queue additional blocks to DMA if in_queue and DMA has free blocks */
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while (strm->free_tx_dma_blocks) {
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/* get the next buffer from queue */
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ret = k_msgq_get(&strm->in_queue, &buffer, K_NO_WAIT);
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if (ret) {
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/* in_queue is empty, no more blocks to send to DMA */
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ret = 0;
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break;
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}
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/* reload the DMA */
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ret = dma_reload(dev_data->dev_dma, strm->dma_channel,
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(uint32_t)buffer,
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(uint32_t)&base->TDR[strm->start_channel],
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strm->cfg.block_size);
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if (ret != 0) {
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LOG_ERR("dma_reload() failed with error 0x%x", ret);
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break;
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}
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(strm->free_tx_dma_blocks)--;
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ret = k_msgq_put(&strm->out_queue,
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&buffer, K_NO_WAIT);
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if (ret != 0) {
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LOG_ERR("buffer %p -> out %p err %d",
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buffer, &strm->out_queue, ret);
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break;
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}
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(*blocks_queued)++;
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}
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irq_unlock(key);
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return ret;
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}
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/* This function is executed in the interrupt context */
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static void i2s_dma_tx_callback(const struct device *dma_dev,
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void *arg, uint32_t channel, int status)
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{
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const struct device *dev = (const struct device *)arg;
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const struct i2s_mcux_config *dev_cfg = dev->config;
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I2S_Type *base = (I2S_Type *)dev_cfg->base;
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const struct device *dev = (struct device *)arg;
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struct i2s_dev_data *dev_data = dev->data;
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struct stream *strm = &dev_data->tx;
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void *buffer = NULL;
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int ret;
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uint8_t blocks_queued;
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LOG_DBG("tx cb");
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@ -221,64 +280,79 @@ static void i2s_dma_tx_callback(const struct device *dma_dev,
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if (ret == 0) {
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/* transmission complete. free the buffer */
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k_mem_slab_free(strm->cfg.mem_slab, &buffer);
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(strm->free_tx_dma_blocks)++;
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} else {
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LOG_ERR("no buf in out queue for channel %u", channel);
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LOG_ERR("no buf in out_queue for channel %u", channel);
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}
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if (strm->free_tx_dma_blocks > MAX_TX_DMA_BLOCKS) {
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strm->state = I2S_STATE_ERROR;
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LOG_ERR("free_tx_dma_blocks exceeded maximum, now %d",
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strm->free_tx_dma_blocks);
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goto disabled_exit_no_drop;
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}
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/* Received a STOP trigger, terminate TX immediately */
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if (strm->last_block) {
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strm->state = I2S_STATE_READY;
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LOG_DBG("TX STOPPED last_block set");
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goto disabled_exit_no_drop;
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}
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if (ret) {
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/* k_msgq_get() returned error, and was not last_block */
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strm->state = I2S_STATE_ERROR;
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goto disabled_exit_no_drop;
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}
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switch (strm->state) {
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case I2S_STATE_RUNNING:
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/* get the next buffer from queue */
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if (strm->in_queue.used_msgs == 0) {
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LOG_DBG("tx no more in queue data");
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i2s_tx_stream_disable(dev, false);
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/* stream is starving */
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strm->stream_starving = true;
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return;
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}
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ret = k_msgq_get(&strm->in_queue, &buffer, K_NO_WAIT);
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if (ret == 0) {
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/* config the DMA */
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uint32_t data_path = dev_data->tx.start_channel;
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strm->dma_block.block_size = strm->cfg.block_size;
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strm->dma_block.dest_address =
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(uint32_t)&base->TDR[data_path];
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strm->dma_block.source_address = (uint32_t)buffer;
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dma_config(dev_data->dev_dma, strm->dma_channel,
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&strm->dma_cfg);
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ret = k_msgq_put(&strm->out_queue,
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&buffer, K_NO_WAIT);
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if (ret != 0) {
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LOG_ERR("buffer %p -> out %p err %d",
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buffer, &strm->out_queue, ret);
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}
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dma_start(dev_data->dev_dma, strm->dma_channel);
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}
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if (ret || status) {
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/*
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* DMA encountered an error (status != 0)
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* or No buffers in input queue
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*/
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LOG_ERR("DMA status %08x chan %u get ret %d",
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status, channel, ret);
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strm->state = I2S_STATE_READY;
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i2s_tx_stream_disable(dev, false);
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}
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break;
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case I2S_STATE_STOPPING:
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i2s_tx_stream_disable(dev, true);
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strm->state = I2S_STATE_READY;
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break;
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ret = i2s_tx_reload_multiple_dma_blocks(dev, &blocks_queued);
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if (ret) {
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strm->state = I2S_STATE_ERROR;
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goto disabled_exit_no_drop;
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}
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dma_start(dev_data->dev_dma, strm->dma_channel);
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if (blocks_queued ||
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(strm->free_tx_dma_blocks < MAX_TX_DMA_BLOCKS)) {
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goto enabled_exit;
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} else {
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/* all DMA blocks are free but no blocks were queued */
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if (strm->state == I2S_STATE_STOPPING) {
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/* TX queue has drained */
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strm->state = I2S_STATE_READY;
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LOG_DBG("TX stream has stopped");
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} else {
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strm->state = I2S_STATE_ERROR;
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LOG_ERR("TX Failed to reload DMA");
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}
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goto disabled_exit_no_drop;
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}
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case I2S_STATE_ERROR:
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default:
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goto disabled_exit_drop;
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}
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disabled_exit_no_drop:
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i2s_tx_stream_disable(dev, false);
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return;
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disabled_exit_drop:
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i2s_tx_stream_disable(dev, true);
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return;
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enabled_exit:
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return;
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}
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static void i2s_dma_rx_callback(const struct device *dma_dev,
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void *arg, uint32_t channel, int status)
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{
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const struct device *dev = (const struct device *)arg;
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struct device *dev = (struct device *)arg;
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const struct i2s_mcux_config *dev_cfg = dev->config;
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I2S_Type *base = (I2S_Type *)dev_cfg->base;
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struct i2s_dev_data *dev_data = dev->data;
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@ -287,21 +361,23 @@ static void i2s_dma_rx_callback(const struct device *dma_dev,
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int ret;
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LOG_DBG("RX cb");
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switch (strm->state) {
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case I2S_STATE_STOPPING:
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case I2S_STATE_RUNNING:
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/* retrieve buffer from input queue */
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ret = k_msgq_get(&strm->in_queue, &buffer, K_NO_WAIT);
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if (ret != 0) {
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LOG_ERR("get buffer from in_queue %p failed (%d)",
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&strm->in_queue, ret);
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}
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__ASSERT_NO_MSG(ret == 0);
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/* put buffer to output queue */
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ret = k_msgq_put(&strm->out_queue, &buffer, K_NO_WAIT);
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if (ret != 0) {
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LOG_ERR("buffer %p -> out_queue %p err %d",
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buffer,
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&strm->out_queue, ret);
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i2s_rx_stream_disable(dev, false, false);
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strm->state = I2S_STATE_ERROR;
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return;
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}
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if (strm->state == I2S_STATE_RUNNING) {
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/* allocate new buffer for next audio frame */
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@ -314,6 +390,21 @@ static void i2s_dma_rx_callback(const struct device *dma_dev,
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strm->state = I2S_STATE_ERROR;
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} else {
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uint32_t data_path = strm->start_channel;
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ret = dma_reload(dev_data->dev_dma,
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strm->dma_channel,
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(uint32_t)&base->RDR[data_path],
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(uint32_t)buffer,
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strm->cfg.block_size);
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if (ret != 0) {
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LOG_ERR("dma_reload() failed with error 0x%x",
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ret);
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i2s_rx_stream_disable(dev,
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false, false);
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strm->state = I2S_STATE_ERROR;
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return;
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}
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/* put buffer in input queue */
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ret = k_msgq_put(&strm->in_queue,
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&buffer, K_NO_WAIT);
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@ -323,23 +414,12 @@ static void i2s_dma_rx_callback(const struct device *dma_dev,
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ret);
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}
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strm->dma_block.block_size =
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strm->cfg.block_size;
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strm->dma_block.dest_address =
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(uint32_t)buffer;
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strm->dma_block.source_address = (uint32_t)
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&base->RDR[data_path];
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dma_config(dev_data->dev_dma,
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strm->dma_channel,
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&strm->dma_cfg);
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/* disable rx interrupt and wait for next read*/
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SAI_RxEnableDMA(dev_cfg->base,
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kSAI_FIFORequestDMAEnable, false);
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dma_start(dev_data->dev_dma,
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strm->dma_channel);
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strm->dma_channel);
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}
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} else {
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/* Received a STOP trigger */
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i2s_rx_stream_disable(dev, true, false);
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/* Received a STOP/DRAIN trigger */
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strm->state = I2S_STATE_READY;
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}
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break;
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@ -354,13 +434,15 @@ static void enable_mclk_direction(const struct device *dev, bool dir)
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const struct i2s_mcux_config *dev_cfg = dev->config;
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uint32_t offset = dev_cfg->mclk_pin_offset;
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uint32_t mask = dev_cfg->mclk_pin_mask;
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uint32_t *gpr = (uint32_t *)DT_REG_ADDR(DT_NODELABEL(iomuxcgpr)) + offset;
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uint32_t *gpr = (uint32_t *)
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(DT_REG_ADDR(DT_NODELABEL(iomuxcgpr)) + offset);
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if (dir) {
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*gpr |= mask;
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} else {
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*gpr &= ~mask;
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}
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}
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static void get_mclk_rate(const struct device *dev, uint32_t *mclk)
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@ -452,9 +534,9 @@ static int i2s_mcux_config(const struct device *dev, enum i2s_dir dir,
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memset(&config, 0, sizeof(config));
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const bool is_mclk_master = i2s_cfg->options & I2S_OPT_BIT_CLK_MASTER;
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const bool is_mclk_slave = i2s_cfg->options & I2S_OPT_BIT_CLK_SLAVE;
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enable_mclk_direction(dev, is_mclk_master);
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enable_mclk_direction(dev, !is_mclk_slave);
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get_mclk_rate(dev, &mclk);
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LOG_DBG("mclk is %d", mclk);
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@ -646,8 +728,9 @@ const struct i2s_config *i2s_mcux_config_get(const struct device *dev,
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{
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struct i2s_dev_data *dev_data = dev->data;
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if (dir == I2S_DIR_RX)
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if (dir == I2S_DIR_RX) {
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return &dev_data->rx.cfg;
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}
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return &dev_data->tx.cfg;
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}
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@ -658,7 +741,6 @@ static int i2s_tx_stream_start(const struct device *dev)
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void *buffer;
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struct i2s_dev_data *dev_data = dev->data;
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struct stream *strm = &dev_data->tx;
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uint32_t data_path = strm->start_channel;
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const struct device *dev_dma = dev_data->dev_dma;
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const struct i2s_mcux_config *dev_cfg = dev->config;
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I2S_Type *base = (I2S_Type *)dev_cfg->base;
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@ -672,11 +754,28 @@ static int i2s_tx_stream_start(const struct device *dev)
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LOG_DBG("tx stream start");
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strm->dma_block.block_size = strm->cfg.block_size;
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strm->dma_block.dest_address =
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(uint32_t)&base->RDR[data_path];
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strm->dma_block.source_address = (uint32_t)buffer;
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/* Driver keeps track of how many DMA blocks can be loaded to the DMA */
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strm->free_tx_dma_blocks = MAX_TX_DMA_BLOCKS;
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/* Configure the DMA with the first TX block */
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struct dma_block_config *blk_cfg = &strm->dma_block;
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memset(blk_cfg, 0, sizeof(struct dma_block_config));
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uint32_t data_path = strm->start_channel;
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blk_cfg->dest_address = (uint32_t)&base->TDR[data_path];
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blk_cfg->source_address = (uint32_t)buffer;
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blk_cfg->block_size = strm->cfg.block_size;
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blk_cfg->dest_scatter_en = 1;
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strm->dma_cfg.block_count = 1;
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strm->dma_cfg.head_block = &strm->dma_block;
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strm->dma_cfg.user_data = (void *)dev;
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(strm->free_tx_dma_blocks)--;
|
||||
dma_config(dev_dma, strm->dma_channel, &strm->dma_cfg);
|
||||
|
||||
/* put buffer in output queue */
|
||||
|
|
@ -686,6 +785,14 @@ static int i2s_tx_stream_start(const struct device *dev)
|
|||
return ret;
|
||||
}
|
||||
|
||||
uint8_t blocks_queued;
|
||||
|
||||
ret = i2s_tx_reload_multiple_dma_blocks(dev, &blocks_queued);
|
||||
if (ret) {
|
||||
LOG_ERR("i2s_tx_reload_multiple_dma_blocks() failed (%d)", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = dma_start(dev_dma, strm->dma_channel);
|
||||
if (ret < 0) {
|
||||
LOG_ERR("dma_start failed (%d)", ret);
|
||||
|
|
@ -693,15 +800,13 @@ static int i2s_tx_stream_start(const struct device *dev)
|
|||
}
|
||||
|
||||
/* Enable DMA enable bit */
|
||||
SAI_TxEnableDMA(dev_cfg->base, kSAI_FIFORequestDMAEnable, true);
|
||||
|
||||
/* Enable SAI Tx clock */
|
||||
SAI_TxEnable(dev_cfg->base, true);
|
||||
SAI_TxEnableDMA(base, kSAI_FIFORequestDMAEnable, true);
|
||||
|
||||
/* Enable the channel FIFO */
|
||||
dev_cfg->base->TCR3 |= I2S_TCR3_TCE(1UL << strm->start_channel);
|
||||
base->TCR3 |= I2S_TCR3_TCE(1UL << strm->start_channel);
|
||||
|
||||
strm->stream_starving = false;
|
||||
/* Enable SAI Tx clock */
|
||||
SAI_TxEnable(base, true);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -715,28 +820,80 @@ static int i2s_rx_stream_start(const struct device *dev)
|
|||
const struct device *dev_dma = dev_data->dev_dma;
|
||||
const struct i2s_mcux_config *dev_cfg = dev->config;
|
||||
I2S_Type *base = (I2S_Type *)dev_cfg->base;
|
||||
uint32_t data_path = strm->start_channel;
|
||||
uint8_t num_of_bufs;
|
||||
|
||||
/* allocate receive buffer from SLAB */
|
||||
ret = k_mem_slab_alloc(strm->cfg.mem_slab, &buffer, K_NO_WAIT);
|
||||
num_of_bufs = k_mem_slab_num_free_get(strm->cfg.mem_slab);
|
||||
|
||||
/*
|
||||
* Need at least NUM_DMA_BLOCKS_RX_PREP buffers on the RX memory slab
|
||||
* for reliable DMA reception.
|
||||
*/
|
||||
if (num_of_bufs < NUM_DMA_BLOCKS_RX_PREP) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* allocate 1st receive buffer from SLAB */
|
||||
ret = k_mem_slab_alloc(strm->cfg.mem_slab, &buffer,
|
||||
K_NO_WAIT);
|
||||
if (ret != 0) {
|
||||
LOG_DBG("buffer alloc from mem_slab failed (%d)", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
strm->dma_block.block_size = strm->cfg.block_size;
|
||||
strm->dma_block.dest_address = (uint32_t)buffer;
|
||||
strm->dma_block.source_address =
|
||||
(uint32_t)&base->RDR[data_path];
|
||||
/* Configure DMA block */
|
||||
struct dma_block_config *blk_cfg = &strm->dma_block;
|
||||
|
||||
memset(blk_cfg, 0, sizeof(struct dma_block_config));
|
||||
|
||||
uint32_t data_path = strm->start_channel;
|
||||
|
||||
blk_cfg->dest_address = (uint32_t)buffer;
|
||||
blk_cfg->source_address = (uint32_t)&base->RDR[data_path];
|
||||
blk_cfg->block_size = strm->cfg.block_size;
|
||||
|
||||
blk_cfg->source_gather_en = 1;
|
||||
|
||||
strm->dma_cfg.block_count = 1;
|
||||
strm->dma_cfg.head_block = &strm->dma_block;
|
||||
strm->dma_cfg.user_data = (void *)dev;
|
||||
|
||||
dma_config(dev_dma, strm->dma_channel, &strm->dma_cfg);
|
||||
|
||||
/* put buffer in input queue */
|
||||
ret = k_msgq_put(&strm->in_queue, &buffer, K_NO_WAIT);
|
||||
if (ret != 0) {
|
||||
LOG_ERR("failed to put buffer in output queue");
|
||||
LOG_ERR("failed to put buffer in input queue, ret1 %d", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* prep DMA for each of remaining (NUM_DMA_BLOCKS_RX_PREP-1) buffers */
|
||||
for (int i = 0; i < NUM_DMA_BLOCKS_RX_PREP - 1; i++) {
|
||||
|
||||
/* allocate receive buffer from SLAB */
|
||||
ret = k_mem_slab_alloc(strm->cfg.mem_slab, &buffer,
|
||||
K_NO_WAIT);
|
||||
if (ret != 0) {
|
||||
LOG_ERR("buffer alloc from mem_slab failed (%d)", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = dma_reload(dev_dma, strm->dma_channel,
|
||||
(uint32_t)&base->RDR[data_path],
|
||||
(uint32_t)buffer, blk_cfg->block_size);
|
||||
if (ret != 0) {
|
||||
LOG_ERR("dma_reload() failed with error 0x%x", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* put buffer in input queue */
|
||||
ret = k_msgq_put(&strm->in_queue, &buffer, K_NO_WAIT);
|
||||
if (ret != 0) {
|
||||
LOG_ERR("failed to put buffer in input queue, ret2 %d",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
LOG_DBG("Starting DMA Ch%u", strm->dma_channel);
|
||||
ret = dma_start(dev_dma, strm->dma_channel);
|
||||
if (ret < 0) {
|
||||
|
|
@ -746,15 +903,13 @@ static int i2s_rx_stream_start(const struct device *dev)
|
|||
}
|
||||
|
||||
/* Enable DMA enable bit */
|
||||
SAI_RxEnableDMA(dev_cfg->base, kSAI_FIFORequestDMAEnable, true);
|
||||
SAI_RxEnableDMA(base, kSAI_FIFORequestDMAEnable, true);
|
||||
|
||||
/* Enable the channel FIFO */
|
||||
dev_cfg->base->RCR3 |= I2S_RCR3_RCE(1UL << strm->start_channel);
|
||||
base->RCR3 |= I2S_RCR3_RCE(1UL << strm->start_channel);
|
||||
|
||||
/* Enable SAI Rx clock */
|
||||
SAI_RxEnable(dev_cfg->base, true);
|
||||
|
||||
strm->stream_starving = false;
|
||||
SAI_RxEnable(base, true);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -796,6 +951,7 @@ static int i2s_mcux_trigger(const struct device *dev, enum i2s_dir dir,
|
|||
}
|
||||
|
||||
strm->state = I2S_STATE_RUNNING;
|
||||
strm->last_block = false;
|
||||
break;
|
||||
|
||||
case I2S_TRIGGER_DROP:
|
||||
|
|
@ -805,31 +961,35 @@ static int i2s_mcux_trigger(const struct device *dev, enum i2s_dir dir,
|
|||
ret = -EIO;
|
||||
break;
|
||||
}
|
||||
if (strm->state == I2S_STATE_READY) {
|
||||
/* nothing to do in this state*/
|
||||
break;
|
||||
}
|
||||
|
||||
strm->state = I2S_STATE_READY;
|
||||
if (dir == I2S_DIR_TX) {
|
||||
i2s_tx_stream_disable(dev, true);
|
||||
} else {
|
||||
i2s_rx_stream_disable(dev, true, true);
|
||||
}
|
||||
strm->state = I2S_STATE_READY;
|
||||
break;
|
||||
case I2S_TRIGGER_DRAIN:
|
||||
|
||||
case I2S_TRIGGER_STOP:
|
||||
if (strm->state != I2S_STATE_RUNNING) {
|
||||
LOG_ERR("STOP trigger: invalid state %d", strm->state);
|
||||
ret = -EIO;
|
||||
break;
|
||||
}
|
||||
|
||||
strm->state = I2S_STATE_STOPPING;
|
||||
strm->last_block = true;
|
||||
break;
|
||||
|
||||
case I2S_TRIGGER_DRAIN:
|
||||
if (strm->state != I2S_STATE_RUNNING) {
|
||||
LOG_ERR("DRAIN/STOP trigger: invalid state %d",
|
||||
strm->state);
|
||||
ret = -EIO;
|
||||
break;
|
||||
}
|
||||
if (dir == I2S_DIR_TX && strm->in_queue.used_msgs == 0) {
|
||||
/* if the transmission is done, then go ready*/
|
||||
strm->state = I2S_STATE_READY;
|
||||
} else {
|
||||
strm->state = I2S_STATE_STOPPING;
|
||||
}
|
||||
|
||||
strm->state = I2S_STATE_STOPPING;
|
||||
break;
|
||||
|
||||
case I2S_TRIGGER_PREPARE:
|
||||
|
|
@ -859,11 +1019,10 @@ static int i2s_mcux_trigger(const struct device *dev, enum i2s_dir dir,
|
|||
static int i2s_mcux_read(const struct device *dev, void **mem_block,
|
||||
size_t *size)
|
||||
{
|
||||
const struct i2s_mcux_config *dev_cfg = dev->config;
|
||||
struct i2s_dev_data *dev_data = dev->data;
|
||||
struct stream *strm = &dev_data->rx;
|
||||
void *buffer;
|
||||
int ret = 0;
|
||||
int status, ret = 0;
|
||||
|
||||
LOG_DBG("i2s_mcux_read");
|
||||
if (strm->state == I2S_STATE_NOT_READY) {
|
||||
|
|
@ -871,26 +1030,18 @@ static int i2s_mcux_read(const struct device *dev, void **mem_block,
|
|||
return -EIO;
|
||||
}
|
||||
|
||||
ret = k_msgq_get(&strm->out_queue, &buffer,
|
||||
status = k_msgq_get(&strm->out_queue, &buffer,
|
||||
SYS_TIMEOUT_MS(strm->cfg.timeout));
|
||||
if (ret != 0) {
|
||||
LOG_DBG("need retry");
|
||||
return -EAGAIN;
|
||||
if (status != 0) {
|
||||
if (strm->state == I2S_STATE_ERROR) {
|
||||
ret = -EIO;
|
||||
} else {
|
||||
LOG_DBG("need retry");
|
||||
ret = -EAGAIN;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
switch (strm->state) {
|
||||
case I2S_STATE_STOPPING:
|
||||
i2s_rx_stream_disable(dev, true, false);
|
||||
strm->state = I2S_STATE_READY;
|
||||
break;
|
||||
case I2S_STATE_RUNNING:
|
||||
SAI_RxEnableDMA(dev_cfg->base,
|
||||
kSAI_FIFORequestDMAEnable, true);
|
||||
break;
|
||||
default:
|
||||
case I2S_STATE_READY:
|
||||
break;
|
||||
}
|
||||
*mem_block = buffer;
|
||||
*size = strm->cfg.block_size;
|
||||
return 0;
|
||||
|
|
@ -913,16 +1064,10 @@ static int i2s_mcux_write(const struct device *dev, void *mem_block,
|
|||
ret = k_msgq_put(&strm->in_queue, &mem_block,
|
||||
SYS_TIMEOUT_MS(strm->cfg.timeout));
|
||||
if (ret) {
|
||||
LOG_ERR("k_msgq_put failed %d", ret);
|
||||
LOG_DBG("k_msgq_put returned code %d", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (strm->state == I2S_STATE_RUNNING && strm->stream_starving) {
|
||||
/* in running state if the stream is off turn it on*/
|
||||
ret = i2s_tx_stream_start(dev);
|
||||
strm->stream_starving = false;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -953,8 +1098,9 @@ static void sai_driver_irq(const struct device *dev)
|
|||
}
|
||||
|
||||
/* clear IRQ sources atm */
|
||||
static void i2s_mcux_isr(const struct device *dev)
|
||||
static void i2s_mcux_isr(void *arg)
|
||||
{
|
||||
struct device *dev = (struct device *)arg;
|
||||
const struct i2s_mcux_config *dev_cfg = dev->config;
|
||||
I2S_Type *base = (I2S_Type *)dev_cfg->base;
|
||||
|
||||
|
|
@ -983,12 +1129,23 @@ static void audio_clock_settings(const struct device *dev)
|
|||
|
||||
/*Clock setting for SAI*/
|
||||
imxrt_audio_codec_pll_init(clock_name, dev_cfg->clk_src,
|
||||
dev_cfg->clk_pre_div, dev_cfg->clk_src_div);
|
||||
dev_cfg->clk_pre_div, dev_cfg->clk_src_div);
|
||||
|
||||
audioPllConfig.loopDivider = dev_cfg->pll_lp;
|
||||
audioPllConfig.postDivider = dev_cfg->pll_pd;
|
||||
audioPllConfig.numerator = dev_cfg->pll_num;
|
||||
audioPllConfig.denominator = dev_cfg->pll_den;
|
||||
#ifdef CONFIG_SOC_SERIES_IMX_RT11XX
|
||||
audioPllConfig.loopDivider = dev_cfg->pll_lp;
|
||||
audioPllConfig.postDivider = dev_cfg->pll_pd;
|
||||
audioPllConfig.numerator = dev_cfg->pll_num;
|
||||
audioPllConfig.denominator = dev_cfg->pll_den;
|
||||
audioPllConfig.ssEnable = false;
|
||||
#elif defined CONFIG_SOC_SERIES_IMX_RT10XX
|
||||
audioPllConfig.src = dev_cfg->pll_src;
|
||||
audioPllConfig.loopDivider = dev_cfg->pll_lp;
|
||||
audioPllConfig.postDivider = dev_cfg->pll_pd;
|
||||
audioPllConfig.numerator = dev_cfg->pll_num;
|
||||
audioPllConfig.denominator = dev_cfg->pll_den;
|
||||
#else
|
||||
#error Initialize SOC Series-specific clock_audio_pll_config_t
|
||||
#endif /* CONFIG_SOC_SERIES */
|
||||
|
||||
CLOCK_InitAudioPll(&audioPllConfig);
|
||||
}
|
||||
|
|
@ -1037,14 +1194,14 @@ static int i2s_mcux_initialize(const struct device *dev)
|
|||
dev_data->tx.state = I2S_STATE_NOT_READY;
|
||||
dev_data->rx.state = I2S_STATE_NOT_READY;
|
||||
|
||||
#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \
|
||||
(defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && \
|
||||
(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER))
|
||||
#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \
|
||||
(defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && \
|
||||
(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER))
|
||||
sai_master_clock_t mclkConfig = {
|
||||
#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
|
||||
.mclkOutputEnable = true,
|
||||
#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && \
|
||||
(FSL_FEATURE_SAI_HAS_NO_MCR_MICS))
|
||||
#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && \
|
||||
(FSL_FEATURE_SAI_HAS_NO_MCR_MICS))
|
||||
.mclkSource = kSAI_MclkSourceSysclk,
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -1055,7 +1212,7 @@ static int i2s_mcux_initialize(const struct device *dev)
|
|||
/* master clock configurations */
|
||||
#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \
|
||||
(defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && \
|
||||
(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER))
|
||||
(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER))
|
||||
#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && \
|
||||
(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)
|
||||
mclkConfig.mclkHz = mclk;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue