When a thread dies, at least print the pointer to it, so we can debug
better.
Change-Id: Ief6bbc0c221e2d5271c240a4b73df16413aa5e22
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
Most kernel APIs are now ready for inclusion in the API guide.
The APIs largely follow a standard template to provide users
of the API guide with a consistent look-and-feel.
Change-Id: Ib682c31f912e19f5f6d8545d74c5f675b1741058
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
This reverts commit
"kernel/arm: add comment about _is_next_thread_current"
and fixes the interrupt locking issue.
The comment would have been right if only reads were done the ready
queue, but that is not the case. It turns out that the comment was written
ignoring the fact that _is_next_thread_current() updates the next thread
cache when fetching the next thread.
Change-Id: I21c9230f85f4f87a6bbf14fd4a9eb7e19b59f8c5
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Though Cortex-M4 could optionally have a floating point unit,
the MCU in the cc3200 in fact does not have an FPU.
Enabling CPU_HAS_FPU caused applications built with CONFIG_FLOAT=y
to crash during an early call to enable_floating_point().
This patch was validated by running microPython, which is one
such application.
Change-Id: I8bfd42c456524e152cbbb983001d9540d93fbe98
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Normally, _is_next_thread_current() must be called with interrupts
locked, but the ARM interrupt exit code does not have to do that. Add
explanation why.
Change-Id: Id383b47a055fdd6fbd5afffa52772e92febde98f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Move away from legacy APIs and use unified kenrel instead.
Change-Id: Icae86beec66df1b041405cbe3455913630fc8ad1
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
There was a lot of duplication between architectures for the definition
of threads and the "nanokernel" guts. These have been consolidated.
Now, a common file kernel/unified/include/kernel_structs.h holds the
common definitions. Architectures provide two files to complement it:
kernel_arch_data.h and kernel_arch_func.h. The first one contains at
least the struct _thread_arch and struct _kernel_arch data structures,
as well as the struct _callee_saved and struct _caller_saved register
layouts. The second file contains anything that needs what is provided
by the common stuff in kernel_structs.h. Those two files are only meant
to be included in kernel_structs.h in very specific locations.
The thread data structure has been separated into three major parts:
common struct _thread_base and struct k_thread, and arch-specific struct
_thread_arch. The first and third ones are included in the second.
The struct s_NANO data structure has been split into two: common struct
_kernel and arch-specific struct _kernel_arch. The latter is included in
the former.
Offsets files have also changed: nano_offsets.h has been renamed
kernel_offsets.h and is still included by the arch-specific offsets.c.
Also, since the thread and kernel data structures are now made of
sub-structures, offsets have to be added to make up the full offset.
Some of these additions have been consolidated in shorter symbols,
available from kernel/unified/include/offsets_short.h, which includes an
arch-specific offsets_arch_short.h. Most of the code include
offsets_short.h now instead of offsets.h.
Change-Id: I084645cb7e6db8db69aeaaf162963fe157045d5a
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The unified kernel is now the only supported kernel, so this
option is unnessary. Eliminating this option also enables
the removal of some legacy code that is no longer required.
Change-Id: Ibfc339d643c8de16a2ed2009c9b468848b8b4972
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Add support for console output via the USB UART.
Note that console input via the USB UART doesnt work.
Adds a simulated poll method for UART interface exposed by USB.
Jira : ZEP-775
Change-Id: I357827ea52c027eb000baed80225f422df1f3358
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
Regardless of the number of interrupt priorities
supported, the exit of the trap handler can check
AUX_IRQ_ACT to see if it interrupted a FIRQ or IRQ.
Change-Id: I0b84d8298d3e6e437c934c01db4535fa8fe29458
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Some arduino 101 boards have old boot loader without context
restore boot flow feature. This handler will allow doing deep sleep
in those boards by jumping to the context restore code. This will
be disabled by default and can be optionally enabled by user.
Jira: ZEP-1258
Change-Id: I92e70550fd92c1cac42b3039d667fb0be8cf5bce
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Some bootloaders have power management support to restoer context
upon resume from deep sleep. In such cases, the OS startup code
should call the notification hook. Create Kconfig flags to configure
this option.
Jira: 1257
Change-Id: I9f40c5fa077c2f17dc8e9f11604c3ed17e549ed5
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
_sys_soc_resume hook is over loaded to handle to different
scenarios. It is primarily called to notify exit of kernel idling
after PM operations. It is also used to notify exit from deep sleep.
This is very confusing and also makes the implementation of the
hook function very difficult because of very different conditions
involved in the 2 different use cases. Further, users may not require
either or both use cases depending of their custom boot flow and
power state handling. To simplify, create a separate hook for the
purpose of deep sleep exit notification. Use the existing one to
only notify kernel idling exit after PM operations.
Jira: ZEP-1256
Change-Id: I96350199a0fd37f16590c8ee5302a94a3d71b8ba
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Add SoC support for ARM Beetle platform.
Beetle is an ARM Cortex-M3 based SoC used on ARM V2M Beetle Boards.
https://www.arm.com/products/tools/development-boards/versatile-express/beetle_iot_evaluation_platform.php
This patch contains:
* The base SoC platform.
* The clock_init functionality.
* The system wide pin definitions.
* The configuarion for the drivers at SoC level (IRQs, PINs and
Base Addr).
Jira: ZEP-1245
Change-Id: If15675935890711983e5ce37d49732b0462c3ec7
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
When waking up from C2LP state, the timer needs
to be reinitialized as we cannot know the time
that we spent in that state.
In order to reschedule the user application, expire it
as soon as we restart.
Change-Id: Id38a0de71e148ae8d9024a36d3983ab57b1e40d2
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
Add Low Power States support to the power shim layer
and show the usage in the quark_se sample.
States are defined as follow:
- SYS_POWER_STATE_CPU_LPS: SS2 with LPSS enabled
- SYS_POWER_STATE_CPU_LPS_1: SS2 with LPSS disabled
- SYS_POWER_STATE_CPU_LPS_2: SS1 with LPSS disabled
Jira: ZEP-994
Change-Id: Ie4b93f6e539cb53fc035be00280b66b2cb0d9fea
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
Updates x86 floating point support to reflect changes that have
been made in recent months.
* Many, many, many cosmetic changes (mostly revisions to comments).
* Elimination of unnecessary function aliases that were needed
to support the task and fiber versions of certain APIs.
* Elimination of run-time code to enable a thread's "FP regs"
option bit if the "SSE regs" option bit was set. The kernel
now recognizes that the thread is using the FPU as long as
either option bit is set. (If the thread has both option bits
enabled this is the same as if only the "SSE regs" bit is set.)
Change-Id: Ic12abc54b6fa78921749b546d8debf23e7ad232d
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
PRIMARY, SECONDARY, NANOKERNEL, MICROKERNEL init levels are now
deprecated.
New init levels introduced: PRE_KERNEL_1, PRE_KERNEL_2, POST_KERNEL
to replace them.
Most existing code has instances of PRIMARY replaced with PRE_KERNEL_1,
SECONDARY with POST_KERNEL as SECONDARY has had a longstanding bug
where the documentation specified SECONDARY ran before the kernel started
up, but actually ran afterwards.
Change-Id: I771bc634e9caf7f17dbf214a270bc9967eed7d32
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Verify the thread priorities are within the bounds when starting a new
thread and when changing the priority of a thread.
Change-Id: I007b3b249e4b80235b6439cbee44cad2f31973bb
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
A race condition would happend if a FIRQ interrupted a
return-from-interrupt from a RIRQ at the wrong moment: if a decision was
already taken which thread to context switch in and the FIRQ woke up
another thread of higher priority, the ready queue would be corrupted.
The solution is to lock interrupts at the moment the interrupt return
code starts looking at the kernel queues. Interrupts do not need to be
unlocked before exiting: the return-from-interrupt (rtie) instruction
will restore the correct interrupt locking state for the thread being
context switched in.
Change-Id: I777665c2faeca7b1f2a77ddd9ee2a520080bae88
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The bitwise AND operator was being applied to the boolean expression
"!shared_data->flags" instead of the whole expression because a
parenthesis was lacking.
This bug has been found using Coccinelle using the following spatch,
after finding a similar bug somewhere else in the code base:
@@
expression E1;
expression E2;
@@
- !E1 & E2
+ !(E1 & E2)
No other instance of this defect has been found with this spatch.
Change-Id: I6b9ca092f4015c80ddc83c31ce540a92e67cdb11
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
An implementation to flush multiple d-cache lines has been added
per the top-level cache.h API. ZEP-1153 was opened to express
the need for MORE i-cache and d-cache APIs. For example, the current
cache.h API doesn't provide a means to invalidate d-cache lines
and has nothing for i-cache.
I've also modified some of the i-cache related aux registers to have
better names so that they won't be confused with d-cache.
These changes are for
ZEP-1176.
Change-Id: If4c5410451cc40dcd5618fc871093c8febf7e061
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Symbols now use the K_ prefix which is now standard for the
unified kernel. Legacy support for these symbols is retained
to allow existing applications to build successfully.
Change-Id: I3ff12c96f729b535eecc940502892cbaa52526b6
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
This KSDK flash shim driver supports the device in the FRDM K64F
platform (enabled with this commit).
WARNING: the driver disables the system interrupts for potentially
long periods of time. This is required to avoid Read-While-Write
issues since most platforms run in XIP mode.
For more detailed information see the link below:
http://cache.freescale.com/files/32bit/doc/app_note/AN4695.pdf
Change-Id: I70f8d09080251033ce2f45be0c2eb95c19fded08
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
The uart_k20 serial driver incorrectly assumed that all instances of the
UART peripheral are driven by the system clock, when actually some
instances are driven by the bus clock (which usually runs at half the
system clock). This caused incorrect baud rate calculations for UART
instances driven by the bus clock (UART2-4).
Change-Id: I38041781cdee146912bb5167e7c71d6416b966b5
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This change is required to support unified kernel.
Change-Id: I47bd644239eb3e624c7a5cb456eedad5aca79e8e
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
The unified kernel expect the default return value from a _Swap() call
to be set to -EAGAIN by the architecture code. Cortex-M3/M4 does this in
the SVC call handler, and it was missing from the Cortex-M0/M0+ before
pending PendSV.
Change-Id: I3316901186ab409f49043eb4f1972c4b0dd9a4a2
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The pinmux configuration is done during board initialization.
This was validated using the following Zephyr apps:
- samples/hello_world
- samples/philosophers
- samples/drivers/uart
- samples/shell
UARTA0 is currently supported.
Change-Id: I85727c622d4d42183cc9f2f8b43d653e245dd17e
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Initial support is for the CC3200 SoC, comprising a network coprocessor
and Cortex-M4 MPU.
This leverages the CC3200 SDK driver peripheral library, installed
separately, or built from ext/hal/.
Jira: ZEP-1109
Change-Id: I508afc8596c165b309a4ec641c39abadc779eea3
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
The k64 SoC has multiple instances of many peripherals, but which
instances can actually be used depends upon the board design and pinmux
configuration.
Move all instance-specific default driver configurations from the SoC to
the boards (frdm_k64f and hexiwear_k64). Default driver selection
remains in the SoC (e.g., enable the KSDK I2C driver when I2C is
enabled).
This paves the way to support different driver defaults for the
frdm_k64f and hexiwear_k64 boards, but it does not yet change any of the
default values; it only changes where the default values get set.
Change-Id: Id9ed898762eb400ecefeac91ae4dce66da05622d
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds standard prefix to symbolic option that flags a thread
as essential to system operation.
Change-Id: Ia904a81ce343fdd1cd44caaaeae641d822777f9b
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
QMSI 1.3 natively supports restoring the SoC and peripherals
after sleep.
The Zephyr Power Management shim layer is updated
in order to support QMSI functions.
The following functions have been added:
void _sys_soc_set_power_state(enum power_state);
void _sys_soc_power_state_post_ops(void);
In order to fully support deep sleep, the function
_sys_soc_set_power_state now support saving and
restoring CPU context and returns to the application.
_sys_soc_set_power_state function also abstracts
QMSI cpu states and enable the application to choose
between C1/C2 or C2LP states.
The QMSI power states are mapped as follows:
SYS_SOC_POWER_STATE_CPU_LPS -> power_cpu_c2lp
SYS_SOC_POWER_STATE_CPU_LPS_1 -> power_cpu_c2
SYS_SOC_POWER_STATE_CPU_LPS_2 -> power_cpu_c1
SYS_SOC_POWER_STATE_DEEP_SLEEP -> power_soc_deep_sleep
SYS_SOC_POWER_STATE_DEEP_SLEEP_1 -> power_soc_sleep
The following functions have been removed:
void _sys_soc_set_power_policy(uint32_t pm_policy);
int _sys_soc_get_power_policy(void);
FUNC_NORETURN void _sys_soc_put_deep_sleep(void);
void _sys_soc_put_low_power_state(void);
void _sys_soc_deep_sleep_post_ops(void);
Those changes are propagated to the samples.
All calls to QMSI are removed.
Jira: ZEP-1045, ZEP-993, ZEP-1047
Change-Id: I26822727985b63be0a310cc3590a3e71b8e72c8c
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
A new shared memory has been added to the qmsi bootloader
in order to handle the restore flow and jump to
the restore trap where context is restored.
Add the new entry to the QUARK SE C1000 linker file
and new kconfig options:
- CONFIG_BSP_SHARED_RAM_ADDR to set the address of the
shared memory.
- CONFIG_BSP_SHARED_RAM_SIZE to set the size of the
shared memory.
This is only enabled with CONFIG_SYS_POWER_DEEP_SLEEP.
Jira: ZEP-1046
Change-Id: I35d924a100c5583025aa36a9741428ab51809c57
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
Enable HAS_CUBE config flag on stm32f4 family soc.h is updated to
include minimum include files from ext/hal/stm23cube
Change-Id: I35a8c33aab777167ee7029edc1b7a4f6d21fccd8
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Create HAS_CUBE config flag to control activation of STM32Cube support.
Generate fitting compilation options for STM32Cube in
/ext/hal/stm32cube/Makefile soc.h is updated to include minimum include
files from ext/hal/stm23cube
Change-Id: If58ce0a4fdb7fbf5f171dfe5f1f8eb75126a8313
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In ST CMSIS files, FLASH_BASE does not mean base address of FLASH register
Instead FLASH_R_BASE is used.
stm32f1 clock control driver is updated to be compatible with this naming.
Change-Id: Ic4fb49c60c392e15fd12c69266baf4c686bd343b
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32Cube uses SoC defines made to reflect HW heterogeneity that
should be taken into account by SW.
Aim of this commit is to adapt values used by Zephyr to the same
diversity. This will help create new SoC values only when justified
by a real hardware difference that should be taken into account
by software.
For instance, for SoC stm32f401re following define is used:
*STM32F401xE
Which means:
*Same SW could be used on STM32F401RE and STM32F401CE:
same CONFIG_SOC could be used
*Different SW should be used on STMF401RE and STM32F401RC:
different CONFIG_SOC should be used
This change focuses on stm32f4xx series.
Change-Id: I56ff4d1815d09747cf722385532eb2dcbdf37b44
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32Cube uses SoC defines made to reflect HW heterogeneity
that should be taken into account by SW.
Aim of this commit is to adapt values used by Zephyr to the same
diversity. This will help create new SoC values only when justified
by a real hardware difference that should be taken into account
by software.
For instance, for SoC stm32f103rb following define is used:
*STM32F103xB
Which means:
*Same SW could be used on STM32F103RB and STM32F103VB:
same CONFIG_SOC could be used
*Different SW should be used on STMF103RB and STM32F103R4:
different CONFIG_SOC should be used
This change focuses on stm32f1xx series.
Change-Id: I5ecfaa52952d04421b27b5e74fb71b4fc108b662
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The GPIO and AON GPIO ports are available to both the x86 and ARC
cores, but the driver always assumed only the x86 at the time of
configuring interrupts.
Use the available macros to set the correct values independently of
which core it's being built for.
Jira: ZEP-1030
Change-Id: I310afcc48780fbe1cac9dc3368a6de11bd797fda
Signed-off-by: Iván Briano <ivan.briano@intel.com>
The SoC level peripherals are accesible by both cores, while the SS
ones are only available to the sensor subsystem. Since the ARC core can
make use of both drivers at the same time, we need to be able to
differentiate their configuration values somehow.
Also disable the SoC GPIO for the ARC by default, as it still needs
more changes to be usable.
Jira: ZEP-1030
Change-Id: Ic5415c404ecd32a3e560467b6f5eaa873a515d72
Signed-off-by: Iván Briano <ivan.briano@intel.com>
