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gpio qmsi: Enable SoC level GPIO to work on ARC too

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The GPIO and AON GPIO ports are available to both the x86 and ARC
cores, but the driver always assumed only the x86 at the time of
configuring interrupts.

Use the available macros to set the correct values independently of
which core it's being built for.

Jira: ZEP-1030
Change-Id: I310afcc48780fbe1cac9dc3368a6de11bd797fda
Signed-off-by: Iván Briano <ivan.briano@intel.com>
This commit is contained in:
Iván Briano 2016-10-26 19:00:46 -02:00 • committed by Anas Nashif
commit f028973f43
2 changed files with 11 additions and 8 deletions
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2
arch/arc/soc/quark_se_c1000_ss/Kconfig.defconfig
View file

@ -83,7 +83,7 @@ endif # RTC
if GPIO
config GPIO_QMSI
def_bool n
def_bool y
if GPIO_QMSI

17
drivers/gpio/gpio_qmsi.c
View file

@ -27,6 +27,7 @@
#include "gpio_utils.h"
#include "qm_isr.h"
#include "clk.h"
#include "soc.h"
#include <power.h>
struct gpio_qmsi_config {
@ -419,18 +420,20 @@ static int gpio_qmsi_init(struct device *port)
CLK_PERIPH_GPIO_INTERRUPT |
CLK_PERIPH_GPIO_DB |
CLK_PERIPH_CLK);
IRQ_CONNECT(QM_IRQ_GPIO_0_INT, CONFIG_GPIO_QMSI_0_IRQ_PRI,
qm_gpio_0_isr, 0, IOAPIC_LEVEL | IOAPIC_HIGH);
irq_enable(QM_IRQ_GPIO_0_INT);
QM_INTERRUPT_ROUTER->gpio_0_int_mask &= ~BIT(0);
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_GPIO_0_INT),
CONFIG_GPIO_QMSI_0_IRQ_PRI, qm_gpio_0_isr, 0,
IOAPIC_LEVEL | IOAPIC_HIGH);
irq_enable(IRQ_GET_NUMBER(QM_IRQ_GPIO_0_INT));
QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->gpio_0_int_mask);
break;
#ifdef CONFIG_GPIO_QMSI_1
case QM_AON_GPIO_0:
IRQ_CONNECT(QM_IRQ_AON_GPIO_0_INT,
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_AON_GPIO_0_INT),
CONFIG_GPIO_QMSI_1_IRQ_PRI, qm_aon_gpio_0_isr,
0, IOAPIC_LEVEL | IOAPIC_HIGH);
irq_enable(QM_IRQ_AON_GPIO_0_INT);
QM_INTERRUPT_ROUTER->aon_gpio_0_int_mask &= ~BIT(0);
irq_enable(IRQ_GET_NUMBER(QM_IRQ_AON_GPIO_0_INT));
QM_IR_UNMASK_INTERRUPTS(
QM_INTERRUPT_ROUTER->aon_gpio_0_int_mask);
break;
#endif /* CONFIG_GPIO_QMSI_1 */
default: