gpio qmsi: Enable SoC level GPIO to work on ARC too
The GPIO and AON GPIO ports are available to both the x86 and ARC cores, but the driver always assumed only the x86 at the time of configuring interrupts. Use the available macros to set the correct values independently of which core it's being built for. Jira: ZEP-1030 Change-Id: I310afcc48780fbe1cac9dc3368a6de11bd797fda Signed-off-by: Iván Briano <ivan.briano@intel.com>
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2 changed files with 11 additions and 8 deletions
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@ -83,7 +83,7 @@ endif # RTC
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if GPIO
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config GPIO_QMSI
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def_bool n
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def_bool y
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if GPIO_QMSI
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@ -27,6 +27,7 @@
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#include "gpio_utils.h"
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#include "qm_isr.h"
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#include "clk.h"
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#include "soc.h"
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#include <power.h>
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struct gpio_qmsi_config {
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@ -419,18 +420,20 @@ static int gpio_qmsi_init(struct device *port)
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CLK_PERIPH_GPIO_INTERRUPT |
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CLK_PERIPH_GPIO_DB |
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CLK_PERIPH_CLK);
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IRQ_CONNECT(QM_IRQ_GPIO_0_INT, CONFIG_GPIO_QMSI_0_IRQ_PRI,
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qm_gpio_0_isr, 0, IOAPIC_LEVEL | IOAPIC_HIGH);
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irq_enable(QM_IRQ_GPIO_0_INT);
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QM_INTERRUPT_ROUTER->gpio_0_int_mask &= ~BIT(0);
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IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_GPIO_0_INT),
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CONFIG_GPIO_QMSI_0_IRQ_PRI, qm_gpio_0_isr, 0,
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IOAPIC_LEVEL | IOAPIC_HIGH);
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irq_enable(IRQ_GET_NUMBER(QM_IRQ_GPIO_0_INT));
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QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->gpio_0_int_mask);
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break;
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#ifdef CONFIG_GPIO_QMSI_1
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case QM_AON_GPIO_0:
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IRQ_CONNECT(QM_IRQ_AON_GPIO_0_INT,
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IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_AON_GPIO_0_INT),
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CONFIG_GPIO_QMSI_1_IRQ_PRI, qm_aon_gpio_0_isr,
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0, IOAPIC_LEVEL | IOAPIC_HIGH);
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irq_enable(QM_IRQ_AON_GPIO_0_INT);
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QM_INTERRUPT_ROUTER->aon_gpio_0_int_mask &= ~BIT(0);
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irq_enable(IRQ_GET_NUMBER(QM_IRQ_AON_GPIO_0_INT));
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QM_IR_UNMASK_INTERRUPTS(
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QM_INTERRUPT_ROUTER->aon_gpio_0_int_mask);
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break;
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#endif /* CONFIG_GPIO_QMSI_1 */
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default:
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