Renesas R-Car series contains a PFC (Pin Function Controller).
This module consists of registers for selecting the function of
the multiplexed pins and controls the pull-up resistor on each pin.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
GD32V SoC uses divided clock from core-clock for machine timer clock.
Add config of clock divide factor to support GD32V.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Add board support for NXP i.MX8M Plus EVK. This board has the following
features:
Processor : i.MX8M Plus Quad applications processor
Memory : 32-bit LPDDR4 w/6 GB
eMMC 5.0/5.1 w/32 GB
SD/MMC connector
QSPI w/32 MB
Connectivity : MIMO 2x2 Wi-Fi 802.11b/g/n/ac and BT 4.2
2x Ethernet (1x w/ TSN)
PCIe M.2
2x CAN FD DB9 Female connectors
USB : USB 3.0 Type C for Power
USB 3.0 Type A
USB 3.0 Type C
Debug : JTAG connector
MicroUSB for debug console
More information about this board can be found in NXP website: https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-plus-applications-processor:8MPLUSLPD4-EVK
Signed-off-by: Chris Trowbridge <chris.trowbridge@lairdconnect.com>
Create an explicit ina230 driver which is supposed to
work with 230 and 231 variants. While at it switch
to i2c_dt_spec helpers and change device-tree node
names to use - instead of _ in order to follow
convention.
Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
This commit adds a generic i2c regulator driver, and enables the NXP
PCA9420 PMIC IC using this driver. The regulator driver also exposes an
additional API in include/drivers/regulator/consumer.h, which allows
drivers to implement support for adjusting voltage levels and current
limits, if their device supports it.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
the RT685 contains an additional flexcomm peripheral, that supports
only I2C. This commit adds this peripheral to the device tree,
and enables pins and clocks for flexcomm15.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
MCUX PWM driver used hardcoded clock source. update driver to use clock
bindings to determine PWM peripheral clock frequency.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Following definitive transition to dts pinmux then pinctrl api
remove C pinmux api leftover definitions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Most of the time SPI devices use TI's frame format. But some may use
Motorola's. This is already taken care of in the SPI API and now it will
be possible to select the right format from DTS. Like:
...
frame-format = <SPI_FRAME_FORMAT_MOTOROLA>;
...
This is only meant to be used for devices supporting both formats (so
the format is not hard-coded in the driver) and selected by hardware
configuration or else. Which, in such case, it will need to use
DT_INST_PROP(<instance number>, frame-format) macro call to retrieve
the property value. Others can fully ignore it.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Add support for configuring UART/UARTE peripheral pins.
Co-authored-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add initial support for nRF pin controller driver. The implementation in
this patch does not yet support any peripheral. Only states
representation and basic driver functionality is introduced.
Note:
The nrf_pin_configure function has been marked as __unused since it may
not be used in certain scenarios until all peripherals are supported by
the pinctrl driver. For example, if only UART/E is supported but the
board does not enable UART, the function will never get called. However,
that board will likely have other peripherals that will gain support in
the future.
Thanks to Marti Bolivar for bindings documentation.
Co-authored-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Aim of this change is to remove the need for the pinmux driver
on stm32f1 series to access the base address of the pinmux owner
device.
This is achieved by a modification in the device tree pin definition.
Instead of providing a generic information on type of the remap
(such as NO_REMAP, PARTIAL_REMAP, FULL_REMAP), the remap field
encodes all the information required to perform the remap register
configuration:
-Address of the targeted remap register in AFIO peripheral
-Position of the remap configuration in the remap register
-Mask used for the remap configuration encoding
-Value of the expected remap configuration.
All the possible remap configurations are encoded and predefined
in a new stm32f1-afio.h dt-bindings include.
To match this new configuration, all stm32f1 -pinctrl.dtsi should
be regenerated to use these new remap definitions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Review pinmux macro definition to a more portable format,
in preparation for new remap information encoding on stm32f1 series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Users will have to include dt-bindings/spi/spi.h in order to use the
relevant flags fol this property. For instance:
...
duplex = <SPI_HALF_DUPLEX>;
....
By default all SPI device are configured to be full duplex so the
property is optional. This property makes sense only for devices that
can be configured on either modes. Which, in such case, it will need to
use DT_INST_PROP(<instance number>, duplex) macro call to retrieve the
property value. Others can fully ignore it.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This joins all clock control handling to same source
by using hal clock functions. It also brings ESP32C3
clock support.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add support for the Xilinx Zynq-7000 SoC family to this driver. This
includes some SoC-specific register accesses when setting an updated
TX clock divider, also, the device tree binding now supports higher
MDC clock divisor values when the current target SoC is a Zynq rather
than a ZynqMP.
With regards to the use of this driver in a QEMU simulation of the
Zynq-7000, the Kconfig file is modified so that the driver is not
enabled unless QEMU networking is set to Ethernet mode.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
The pin macros were used in the pre-DT pinmux era to configure the
mapping between a pin and its configuration.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
interrupt controller, also places its relevant
peripheral sources allowing drivers to use the
DT macros instead of espressif headers.
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
This commit adds support for the Legend 2.5" boards (legend25_ssd and
legend25_hdd) based on the STM32F070CB MCU. These boards can be found in
the Seagate FireCuda Gaming Drive, Gaming Drive for Xbox, SSD Gaming
Drive for Xbox, and Gaming Drive for PlayStation devices. Both boards
contain the following hardware components:
- A B1414 LED strip connected to the PA7 pin (SPI MOSI)
- A SPI flash (FM25F005) connected on SPI2 bus
The Legend 2.5" HDD board also contains an activity LED connected on
TIM3 CH3
Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
Add a macro for encoding interrupt source information: GIRQ number,
GIRQ bit position, GIRQ aggregated NVIC connection, and source
direct NVIC connection.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
This driver supports the TI INA230 and INA231 Bidirectional Current
and Power Monitors. The devices work on the I2C interface and are
created from DT nodes with a compatible property matching "ti,ina23x".
The following datasheets were referenced while developing the driver:
https://www.ti.com/product/INA230https://www.ti.com/product/INA231
Twister passed:
twister -T tests/drivers/build_all/sensor/
Testing was performed on the stm32g071b_disco board with the following:
Load: ~170 ohms
Voltage: 5V
Measured Values:
Voltage: 5.1 V
Current: 0.032 A
Power: 0.157 W
Signed-off-by: Sam Hurst <sbh1187@gmail.com>
Add driver implementation and header files for a MEC172x
aggregated interrupt driver. Enable the parent(ECIA) node
to have the driver initialize interrupt hardware for use.
Enable child nodes for those GIRQs used for aggregation.
Refer to chip documention for the list of GIRQs restricted
to aggregation and those which support direct mode.
Add chip level device tree node for MEC172x EC interrupt
aggregator parent and GIRQ children. Each child node contains
a list of sources representing the source bit position in the
GIRQ registers.
Add DT bindings for ECIA and GIRQ nodes.
Add build file(s) and configuration items for the MEC172x ECIA
aggregated interrupt driver. Add and enable the MEC172x interrupt
driver on the MEC172x evaluation board(EVB). Enable parent node to
initialize ECIA hardware. Child nodes are left disabled until a
future driver needs them.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
All the macro for dma-cells are now in the
include/drivers/dma/dma_stm32.h header file.
So the include/dt-bindings/dma/stm32_dma.h is no more
useful and removed from #include.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Implement a clock control driver for Microchip MEC172x handling
configuring the 32 KHz input sources for the PLL and peripheral-32k
clock domains. MEC172x differs from MEC152x. MEC152x had one 32K source
for both PLL and peripherals. MEC172x allows the two domains to use
independent 32 KHz sources. Device tree updated to provide addresses
of hardware used by the driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
There is a name clash when using G4 series LL TIM driver depending on
the inclusion order of the LL TIM and pinmux headers. If the LL headers
are included after pinmux is included, AF1 and AF2 definitions used by
pinmux clash with the AF1 and AF2 TIMx register names.
In order to solve this problem with minimum impact, the following has
been done:
1. Prefix the AFx and ANALOG definitions with STM32
2. In order to avoid changing all *-pinctrl.dtsi files, the STM32_PINMUX
macro contatenates STM32_ with the provided mode.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add support for the Xilinx GEM Ethernet controller, which is integrated
in both the Xilinx Zynq and ZynqMP (UltraScale) SoC families. The driver
supports the management of a PHY attached to the respective GEM's MDIO
interface.
This driver was developed with ultimately the Zynq-7000 series in mind,
but at the time being, it is limited to use in conjunction with the
ZynqMP RPU (Cortex-R5) cores. The differences are minor when it comes
to the adjustment of the TX clock frequency derived from the current
link speed reported by the PHY, but for use in conjunction with the
Zynq-7000, some larger adjustments will have to be made when it comes
to the placement of the DMA memory area, as this involves the confi-
guration of the MMU in Cortex-A CPUs.
The driver was developed under the qemu_cortex_r5 target. The Marvell
88E1111 PHY simulated by QEMU is supported by the driver.
Limitations currently exist when it comes to timestamping or VLAN
support and other minor things. Those haven't been implemented yet,
although they are supported by the hardware. In order to be fully
supported by the ZynqMP APU, 64-bit DMA address descriptor format
support will be added.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
Add GPIO_flag values for GPIO DTS creation that
allows for pins that do not use the default
voltage. IT8xxx2 supports setting voltage
levels for each pin. The default for this SoC
is 3P3 but they can be set individually to
1P8.
This will be used, for example:
i2c_c_scl {
gpios = <&gpioc 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
enum-name = "GPIO_I2C_C_SCL";
label = "I2C_C_SCL";
};
Signed-off-by: Denis Brockus <dbrockus@google.com>
