Commit graph

1037 commits

Author SHA1 Message Date
Carlo Caione
a61290e1a3 arch: arm64: Add support for qemu_cortex_a53 board
This patch introduces support for the qemu_cortex_a53 board emulated
using QEMU (virt platform) adding SoC, board and DTS files.

| ./scripts/sanitycheck -p qemu_cortex_a53
|
| Total complete:  190/ 190  100%  skipped:   40, failed:    0
| 150 of 150 tests passed (100.00%), 0 failed,
|     40 skipped with 0 warnings in 580.93 seconds

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2020-02-01 08:08:43 -05:00
Ivo Clarysse
0c8a99582e dts: arm: stm32f4: add CAN_2 controller
Add the CAN controller device tree node for CAN_2 of the STM32F4 SoC
series.

Signed-off-by: Ivo Clarysse <ivo@bcdevices.com>
2020-01-30 14:27:28 -05:00
Christian Taedcke
fbbf68d63c soc: silabs_exx32: Support all gpio ports on efm32jg and efm32pg
This commit adds the remaining gpio ports I, J and K to the device
tree and dts_fixup headers of the EFM32JG12B and EFM32PG12B SoCs.

Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
2020-01-30 09:15:53 -06:00
Benjamin Valentin
6fd08da96a soc: atmel_sam0: remove CONFIG_ENTROPY_NAME from dts_fixup.h
It's not needed anymore and causes build failures.

Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
2020-01-30 08:44:30 -06:00
Benjamin Valentin
9f548b94cd soc: atmel_sam0: remove obsolete include
`cortex_m/exc.h` is not needed anymore and ceased to exist.

Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
2020-01-30 08:44:30 -06:00
Francois Ramu
4ef62a2db7 soc: arm: st_stm32: configure stm32g431 series
This patch cleans the defconfig of the STM32G431
     device from STMicroelectronics.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2020-01-30 08:30:15 -06:00
Francois Ramu
fafd20ca93 soc: arm: st_stm32: add stm32g474 series
This patch introduces the support of the STM32G474
     device from STMicroelectronics.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2020-01-30 08:30:15 -06:00
Christian Taedcke
4ead400d79 arm: exx32: Add Silabs EFM32JG12B soc files
The Silicon Labs EFM32 Jade Gecko MCU includes:

    * Cortex-M3 core at 40MHz
    * up to 1024KB of flash and 256KB of RAM
    * multiple low power peripherals

This is basically the same as the EFM32 Pearl Gecko, but with an ARM
Cortex-M3 core instead of a Cortex-M4F.

Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
2020-01-30 07:06:54 -06:00
Scott Branden
54ce0b2d34 arm: Add Broadcom Valkyrie SoC support
Add initial support for Broadcom Valkyrie SoC as part of Zephyr.

Signed-off-by: Scott Branden <scott.branden@broadcom.com>
2020-01-30 03:54:01 -06:00
Henrik Brix Andersen
be3cb485eb soc: arm: nxp: kinetis: disable watchdog init if bootloader is enabled
Disable the early watchdog initialization for the NXP Kinetis series
if the application is to be chain-loaded by mcuboot.

The early watchdog initialization must only take place once and needs
to happen within a SoC specific number of CPU clock cycles after
reset.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-01-29 15:12:24 -06:00
Henrik Brix Andersen
282d85c3f4 soc: arm: nxp: kinetis: unify CONFIG_WDOG_INIT Kconfig option
Move CONFIG_WDOG_INIT for the NXP Kinetis series to the top-level
Kinetis Kconfig file and enable it where needed.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-01-29 15:12:24 -06:00
Henrik Brix Andersen
9523f792da soc: nxp: kinetis: kw4xz: move watchdog init to z_arm_watchdog_init
Move the NXP Kinetis KW4xZ watchdog initialization code to
z_arm_watchdog_init() and make it optional based on CONFIG_WDOG_INIT.

This brings the KW4xZ in line with the other NXP Kinetis series SoC
implementations.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-01-29 15:12:24 -06:00
Henrik Brix Andersen
f9f7379549 soc: nxp: kinetis: kl2x: move watchdog init to z_arm_watchdog_init
Move the NXP Kinetis KL2x watchdog initialization code to
z_arm_watchdog_init() and make it optional based on
CONFIG_WDOG_INIT.

This brings the KL2x in line with the other NXP Kinetis series SoC
implementations.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-01-29 15:12:24 -06:00
Kwon Tae-young
271bd8bcea soc: stm32l1: Add support for STM32 IWDG
The driver for STM32's independent watchdog already exists and is
compatible with the stm32l1 SoC. Enable the independent watchdog
for the stm32l1 series for use with this driver.

Signed-off-by: Kwon Tae-young <tykwon@m2i.co.kr>
2020-01-29 11:20:57 -06:00
Ulf Magnusson
1b394ad153 soc: ti_simplelink: kconfig: Refactor CCFG flash block handling
Instead of having TI_CCFG_PRESENT as a symbol that's only defined in
soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.defconfig.series and y when
SOC_SERIES_CC13X2_CC26X2 is enabled, turn it into a helper symbol that's
selected by SOC_SERIES_CC13X2_CC26X2.

This avoids having a symbol that's only defined in a Kconfig.defconfig
file, which is confusing. It also makes things a bit more generic, in
case other boards with CCFGs are added.

Also rename it to HAS_TI_CCFG to be consistent with other helper
symbols, and add a help text.

Flagged by scripts/kconfig/lint.py.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2020-01-29 09:41:46 -06:00
Krzysztof Chruscinski
510102dd71 soc: arm: nordic_nrf: nrf52: Add workaround for anomaly 132
Added delay before starting low frequency clock for the first time to
ensure that anomaly conditions are not met. Delay is configurable and
might be disabled.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2020-01-29 15:38:55 +01:00
Andrzej Głąbek
01648cc099 Revert "soc: nrf5340: Fix busy waiting on nRF5340 application core"
This reverts commit 49bd19f3f2,
as the patch it contains is no longer needed after nrfx is updated
to version 2.1.0.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2020-01-29 15:00:45 +01:00
Andrzej Głąbek
7899b1f5b6 modules: hal_nordic: Update nrfx to version 2.1.0
Update the hal_nordic module revision, to switch to nrfx 2.1.0.

Because the list of peripherals for nRF5340 has changed as follows:
- SPIM2 has been renamed to SPIM4
- SPIM2-3, SPIS2-3, TWIM2-3, TWIS2-3, and UARTE2-3 have been added
a couple of related corrections needed to be applied in dts and Kconfig
files, plus the spi_nrfx_spim driver has been extended with the support
for SPIM4.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2020-01-29 15:00:45 +01:00
Henrik Brix Andersen
5a82424767 dts: arm: stm32f3: add can controller
Add the CAN controller device tree node for CAN_1 of the STM32F3 SoC
series.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-01-29 09:47:27 +01:00
Sarvesh Patkar
4f2c107389 drivers: flash: stm32: Update flash driver implementation
Remove soc/arm/st_stm32/stm32YY/flash_registers.h files.
Change register accesses in stm32 flash drivers to use FLASH_TypeDef
from modules/hal/stm32/stm32cube/stm32YYxx/soc/stm32xxxxxx.h.

Fixes #16235

Signed-off-by: Sarvesh Patkar <psarvesh314@gmail.com>
2020-01-28 15:30:12 -06:00
Francois Ramu
25700ace0a soc: arm: stm32: define the heap size when enabling dma feature
when DMA IP is enabled on stm32 series,
the heap size must be configured to large value
because of dma channels configuration.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2020-01-28 12:58:44 -06:00
Jose Alberto Meza
592e0afdf3 soc: arm: microchip: Update fixup for priorities
Avoid exposing unnecessary details for eSPI IRQ priorities.

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2020-01-28 20:13:36 +02:00
Jonas Eriksson
3e64e751b6 soc: stm32f1: Add support for stm32f1xx SoCs
Define stm32f100xx family, tested using stm32vl_disco
(stm32f100rb).

Signed-off-by: Jonas Eriksson <jonas@upto.se>
2020-01-28 08:30:52 -06:00
Ulf Magnusson
cf89ba33ea global: Fix up leading/trailing blank lines in files
To make the updated test in
https://github.com/zephyrproject-rtos/ci-tools/pull/121 clean, though it
only checks modified files.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2020-01-27 17:41:55 -06:00
Peter Bigot
02ae343100 treewide: use full path to uart.h header
The build infrastructure should not be adding the drivers subdirectory
to the include path.  Fix the legacy uses that depended on that
addition.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2020-01-26 17:52:12 +01:00
Peter Bigot
5e470ec3bf treewide: use full path to gpio/gpio_mmio32.h header
The build infrastructure should not be adding the drivers subdirectory
to the include path.  Fix the legacy uses that depended on that
addition.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2020-01-26 17:52:12 +01:00
Henrik Brix Andersen
cd28b0b6d2 soc: arm: nxp: ke1xf: remove unused SPI dts fixups
Remove unused SPI device tree fixups from the NXP KE1xF SoC.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-01-24 21:31:25 -05:00
Ulf Magnusson
d28e1f6bcb kconfig: Turn pointless 'menuconfig's into 'config's
Same deal as in commit 677f1e6 ("config: Turn pointless/confusing
'menuconfig's into 'config's"), for a newly-introduced stuff.

Also clean up headers to be consistent with recent cleanups.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2020-01-24 21:30:17 -05:00
Oane Kingma
e91da4ae45 soc/arm/silabs_exx32: Add support for EFM32GG11B SoC
This commit adds support for the Silicon Labs EFM32GG11B
series of SoCs.

Signed-off-by: Oane Kingma <o.kingma@interay.com>
2020-01-24 10:28:33 -06:00
Benjamin Valentin
2539a1751d soc: atmel_sam0: update dts_fixup.h for TRNG
Update dts_fixup.h to re-use the SAM TRNG driver.

Signed-off-by: Benjamin Valentin <benpicco@googlemail.com>
2020-01-23 12:40:59 +01:00
Øyvind Rønningstad
05f0d85b6a extensions.cmake: Replace TEXT_START with ROM_START
In zephyr_linker_sources().
This is done since the point of the location is to place things at given
offsets. This can only be done consistenly if the linker code is placed
into the _first_ section.

All uses of TEXT_START are replaced with ROM_START.

ROM_START is only supported in some arches, as some arches have several
custom sections before text. These don't currently have ROM_START or
TEXT_START available, but that could be added with a bit of refactoring
in their linker script.

No SORT_KEYs are changed.

This also fixes an error introduced when TEXT_START was added, where
TEXT_SECTION_OFFSET was applied to riscv's common linker.ld instead of
to openisa_rv32m1's specific linker.ld.

Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
2020-01-23 03:22:59 -08:00
Ulf Magnusson
77743741e6 soc: psoc6: kconfig: Do not select CPU_CORTEX_M_HAS_DWT on Cortex-M0
CPU_CORTEX_M_HAS_DWT depends on

    !CPU_CORTEX_M0 && !CPU_CORTEX_M0PLUS

, but SOC_SERIES_PSOC62 unconditionally selects it, even for
SOC_PSOC6_M0. This forces CPU_CORTEX_M_HAS_DWT on on Cortex-M0.

Fix it by moving the selects for CPU capabilities to the more specific
SOC_PSOC6_{M0,M4} symbols. This seems more readable than adding a
condition to the 'select CPU_CORTEX_M_HAS_DWT'.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2020-01-23 09:39:01 +01:00
Robert Lubos
65ec2d9701 boards: nrf52811_pca10056: Enable nRF 802.15.4 driver by default
nrf52811_pca10056 board should enable nRF 802.15.4 radio driver
automatically when 802.15.4 subsystem is enabled, as other Nordic
802.15.4-compliant boards do.

Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
2020-01-22 14:58:40 +01:00
Henrik Brix Andersen
75549fc560 soc: arm: nxp: kinetis: k6x: enable RTC device
Enable the RTC counter present in the NXP K6x SoC if CONFIG_COUNTER is
enabled. Add the needed dts fixup for the RTC device.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-01-22 06:27:30 -06:00
Antony Pavlov
fc1cdf233d soc: arm: stm32l1: Add STM32L152Xe stuff
The STM32L151 and STM32L152 differ in that
the STM32L152 features an LCD controller.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
2020-01-20 18:08:43 -06:00
Ioannis Glaropoulos
7fee3efd99 soc: arm: remove explicit selection of already selected symbols
CPU_CORTEX_M_HAS_SYSTICK and CPU_CORTEX_M_HAS_VTOR do not need
to be explicitely selected in SoC/Boards definitions of
platforms implementing the Cortex-M mainline architecture; they
are already selected by ARMV7_M_ARM8_M_MAINLINE Kconfig symbol.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-01-20 17:23:42 -05:00
Ioannis Glaropoulos
1d60bca3fe soc: arm: arm: Select CPU DWT feature symbol for ARM Cortex-M SoCs
The Data Watchpoint and Trace (DWT) is an optional debug unit
for the Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+)
that provides watchpoints, data tracing and system profiling
capabilities. We select it for the ARM Cortex-M SoCs
- Beetle
- Musca A, Musca B
since it is present in these SoCs.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-01-20 14:05:47 +01:00
Stephanos Ioannidis
155c1f5ffe soc: arm: ti_simplelink: Select CPU DWT feature symbol
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-20 14:05:47 +01:00
Stephanos Ioannidis
4cef583dc7 soc: arm: ti_lm3s6965: Select CPU DWT feature symbol
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-20 14:05:47 +01:00
Stephanos Ioannidis
88d79a49d2 soc: arm: st_stm32: Select CPU DWT feature symbol
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-20 14:05:47 +01:00
Stephanos Ioannidis
f9453832aa soc: arm: silabs_exx32: Select CPU DWT feature symbol
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-20 14:05:47 +01:00
Stephanos Ioannidis
d658883a7c soc: arm: nxp_lpc: Select CPU DWT feature symbol
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-20 14:05:47 +01:00
Stephanos Ioannidis
09843584ec soc: arm: nxp_kinetis: Select CPU DWT feature symbol
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-20 14:05:47 +01:00
Stephanos Ioannidis
16bb973044 soc: arm: nxp_imx: Select CPU DWT feature symbol
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-20 14:05:47 +01:00
Stephanos Ioannidis
8095cafaa1 soc: arm: nordic_nrf: Select CPU DWT feature symbol
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-20 14:05:47 +01:00
Stephanos Ioannidis
3d7deff3fb soc: arm: microchip_mec: Select CPU DWT feature symbol
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-20 14:05:47 +01:00
Stephanos Ioannidis
02090592ab soc: arm: psoc6: Select CPU DWT feature symbol
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-20 14:05:47 +01:00
Stephanos Ioannidis
d32546fb7e soc: arm: atmel_sam: Select CPU DWT feature symbol
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-20 14:05:47 +01:00
Kumar Gala
b1602c8e39 arm: Removed support for CC2650
The SoC, driver, and board support for the CC2650 and CC2650 Sensortag
aren't currently supported and we are removing them as such.  If anyone
is interesting in supporting this platform we can easily recovery it
from git.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-01-18 09:27:55 -06:00
Ulf Magnusson
4e85006ba4 dts: Rename generated_dts_board*.{h,conf} to devicetree*.{h,conf}
generated_dts_board.h is pretty redundant and confusing as a name. Call
it devicetree.h instead.

dts.h would be another option, but DTS stands for "devicetree source"
and is the source code format, so it's a bit confusing too.

The replacement was done by grepping for 'generated_dts_board' and
'GENERATED_DTS_BOARD'.

Two build diagram and input-output SVG files were updated as well, along
with misc. documentation.

hal_ti, mcuboot, and ci-tools updates are included too, in the west.yml
update.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2020-01-17 17:57:59 +01:00