Commit graph

1037 commits

Author SHA1 Message Date
Kieran Levin
acac1584bc drivers: serial: add dts peripherals to stm32g0
Added device tree nodes and associated headers for
defined uarts on the stm32g0 and stm32g07x 8x parts.

Tested with uart on stm32g071rb disco board with usart3 going to stlink.
Using shell.

Signed-off-by: Kieran Levin <ktl@frame.work>
2020-03-26 22:45:01 +01:00
Kumar Gala
1a0ba4c6ec soc: microchip_mec: Convert to new DT_INST macros
Convert older DT_INST_ macro use the new include/devicetree.h
DT_INST macro APIs.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-26 16:31:52 -05:00
Kumar Gala
3b24ab418a soc: st_stm32: Convert to new DT_INST macros
Convert older DT_INST_ macro use the new include/devicetree.h
DT_INST macro APIs.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-26 12:22:12 -05:00
Kieran Levin
1b3410e197 soc: kconfig: move Kconfig.defconfig.stm32g071rb
use series designator instead

Signed-off-by: Kieran Levin <ktl@frame.work>
2020-03-26 09:39:10 -05:00
Kumar Gala
64bd0951e4 soc: silabs: Convert to new DT_INST macros
Convert older DT_INST_ macro use the new include/devicetree.h
DT_INST macro APIs.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-26 05:26:23 -05:00
Stephanos Ioannidis
a033683783 arch: arm: aarch32: Rename cortex_r to cortex_a_r
This commit renames the `cortex_r` directory under the AArch32 to
`cortex_a_r`, in preparation for the AArch32 Cortex-A support.

The rationale for this renaming is that the Cortex-A and Cortex-R share
the same base design and the difference between them, other than the
MPU vs. MMU, is minimal.

Since most of the architecture port code and configurations will be
shared between the Cortex-A and Cortex-R architectures, it is
advantageous to have them together in the same directory.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-03-26 11:20:36 +01:00
Kumar Gala
ecaf368f9d soc: cc13x2_cc26x2: Convert to new DT_INST macros
Convert older DT_INST_ macro use the new include/devicetree.h
DT_INST macro APIs.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-26 05:20:19 -05:00
Kumar Gala
6143a628dd soc: nxp_lpc: Convert to new DT_INST macros
Convert older DT_INST_ macro use the new include/devicetree.h
DT_INST macro APIs.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-26 03:40:09 -05:00
Kumar Gala
9acb2f9f1b soc: nxp_imx: Convert to new DT_INST macros
Convert older DT_INST_ macro use the new include/devicetree.h
DT_INST macro APIs.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-26 03:40:09 -05:00
Kumar Gala
d267ad1b22 soc: nxp_kinetis: Convert to new DT_INST macros
Convert older DT_INST_ macro use the new include/devicetree.h
DT_INST macro APIs.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-26 03:40:09 -05:00
Vincent Wan
b591bc0b94 soc: cc13x2_cc26x2: set SYS_PM_STATE_LOCK when power management is enabled
When power management is enabled, SYS_PM_STATE_LOCK is necessary
in order to prevent the power policy from automatically entering
certain sleep states.

Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
2020-03-25 16:21:33 -04:00
Kumar Gala
9ede3c9a97 drivers: serial: uart_pl011: remove shared irq support
The shared irq support isn't needed in this driver.  We just need to
deal with the fact that some SoCs have only a single interrupt line and
some have three interrupts.  We can just ifdef that based on
DT_NUM_IRQS.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-25 08:34:40 -05:00
Giancarlo Stasi
2f3c3a65fd soc: arm: st_stm32: add support for STM32L462xE
Add support for the STM32L462xE SoC (AES not yet supported).

Signed-off-by: Giancarlo Stasi <giancarlo.stasi.co@gmail.com>
2020-03-25 09:38:30 +01:00
Tomasz Bursztyka
e68cec3614 soc: stm32: Add flash dts fixup for stm32f4
This was a simple missing macro, that prevented flash_shell to build
for stm32f4 based boards (which is weird, CI should have caught that
much earlier)

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-03-25 03:25:54 -05:00
Piotr Mienkowski
8a9df52943 drivers: gpio_gecko: convert to DT_INST defines
Convert the driver to use DT_INST_ defines, update all dependent dts,
soc and board files.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2020-03-24 10:14:21 -05:00
Piotr Mienkowski
bdcfa4f375 soc: silabs_exx32: Add support for SiLabs EFR32BG13P SoC
This commit adds support for Silicon Labs EFR32BG13P (Blue Gecko) SoC.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2020-03-20 14:40:42 -05:00
Armand Ciejak
f00843feff drivers: eth: eth_mcux: Add 2nd Ethernet controller to RT1060 device tree
Add eth1 in dtsi and defines for the second controller in fixup.

Signed-off-by: Armand Ciejak <armandciejak@users.noreply.github.com>
2020-03-20 10:55:04 +01:00
Parthiban Nallathambi
b2d020bdbf soc: arm: nxp: kinetis: k6x: add K66F support
Add MK66F18 series support with MK66FN2M0VMD18 part.

Signed-off-by: Parthiban Nallathambi <pn@denx.de>
2020-03-19 15:58:08 -05:00
Parthiban Nallathambi
7dcffb6ccd soc: arm: nxp: kinetis: k6x: move clock defines
Rename the clock defines from k64 to K6X. This allows
inclusion of K66 series MCU's support without much
re-defines. Clock divider defaults to K64 series.

Signed-off-by: Parthiban Nallathambi <pn@denx.de>
2020-03-19 15:58:08 -05:00
Pooja Karanjekar
b49501e3c9 drivers: entropy: gecko: add entropy driver based on GECKO TRNG
Add entropy driver based on GECKO TRNG module along with device
tree support for EFM32PG and EFR32MG SOCs.

Signed-off-by: Pooja Karanjekar <pooja.karanjekar@lemonbeat.com>
2020-03-19 15:45:01 -05:00
Carles Cufi
4b37a8f3a4 Revert "global: Replace BUILD_ASSERT_MSG() with BUILD_ASSERT()"
This reverts commit 8739517107.

Pull Request #23437 was merged by mistake with an invalid manifest.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2020-03-19 18:45:13 +01:00
Oleg Zhurakivskyy
8739517107 global: Replace BUILD_ASSERT_MSG() with BUILD_ASSERT()
Replace all occurences of BUILD_ASSERT_MSG() with BUILD_ASSERT()
as a result of merging BUILD_ASSERT() and BUILD_ASSERT_MSG().

Signed-off-by: Oleg Zhurakivskyy <oleg.zhurakivskyy@intel.com>
2020-03-19 15:47:53 +01:00
Erwan Gouriou
d65e54da5e soc: stm32l4: Factorize includes declarations for GPIO driver
Group #include declarations for CONFIG_GPIO_STM32


Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-03-19 15:27:09 +01:00
Takumi Ando
8d106d198e drivers: adc: Add STM32L1X ADC support
Add ADC driver support for STM32L1X SoC series.

Signed-off-by: Takumi Ando <takumi@t15.red>
2020-03-19 03:10:39 -05:00
Takumi Ando
5eb7862f7f soc: arm: stm32: Revert changes for ADC fixups
We need to define DT_ADC_1_NAME to use
generic ADC subsystems(ex. adc_shell).

Signed-off-by: Takumi Ando <takumi@t15.red>
2020-03-19 03:10:39 -05:00
Gerard Marull-Paretas
39b1f6cbba drivers: i2c: stm32: add support for H7 series
Enable I2C driver for STM32 H7 series.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-03-18 15:48:48 -05:00
Stephanos Ioannidis
4d778b789a soc: arm: xilinx_zynqmp: Use CMSIS-Core(R)
This commit updates the `xilinx_zynqmp` SoC initialisation code to use
the CMSIS-Core(R) features.

In addition, it also defines the Core IP revision value for the SoC as
specified in the Zynq UltraScale+ Device Technical Reference Manual.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-03-18 15:47:21 -05:00
Erwan Gouriou
9367c6ad3f drivers/usb: usb_dc_stm32: Convert to DT_INST
Convert usb_stm32 driver to use of DT_INST macros.

Since driver is compatible with 3 different dt compatibles and
compatible string is included in DT_INST macros, I've kept the
DT_USB_ compatible agnostic macros based on DT_INST ones, which
allowed to remove fixup definitions.
Use of DT_USB symbols is now limited to usb_dc_stm32.

Additionally, compatible "st,stm32-otgfs" is removed from list
of compatibles for usbotg_hs ips.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-03-17 11:03:10 -06:00
Erwan Gouriou
6275513051 drivers: serial: uart_stm32: convert to DT_INST defines
Convert driver to use DT_INST_ defines.
In the process, we've removed all UART/USART/LPUART code in
device instanciation code which had no impact.
Since all uart/usart/lpuart nodes declare compatibility with
st,stm32uart, DT_INST_X_ST_STM32_UART_FOO could be used.

Removed DT_UART fixup macros.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-03-17 11:03:10 -06:00
Erwan Gouriou
c2f19dc52e drivers: spi: spi_stm32: convert to DT_INST defines
Convert driver to use DT_INST_ defines.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-03-17 11:03:10 -06:00
Erwan Gouriou
ac516aa888 drivers: pwm: pmw_stm32: convert to DT_INST defines
Convert driver to use DT_INST_ defines.
Removed DT_FLASH_DEV fixup macros.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-03-17 11:03:10 -06:00
Erwan Gouriou
22af564f19 drivers: flash: flash_stm32: convert to DT_INST defines
Convert driver to use DT_INST_ defines.
Removed DT_FLASH_DEV fixup macros, except DT_FLASH_DEV_NAME
used in applications.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-03-17 11:03:10 -06:00
Erwan Gouriou
f289a6f3be drivers: counter: rtc_stm32: convert to DT_INST defines
Convert driver to use DT_INST_ defines.
Removed DT_RTC_0 fixup macros but keep DT_RTC_NAME_0 as it is
still in use across RTC users.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-03-17 11:03:10 -06:00
Erwan Gouriou
0c9b537edf drivers: adc: adc_stm32: convert to DT_INST defines
Convert driver to use DT_INST_ defines.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-03-17 11:03:10 -06:00
Kumar Gala
c44a4d84e0 drivers: watchdog: wwdg_stm32: convert to DT_INST defines
Convert driver to use DT_INST_ defines.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-03-17 11:03:10 -06:00
Øyvind Rønningstad
6492dcec6f soc: nrf53: soc: Add nrf53_has_erratum19()
And add assert on bootup if workarounds are not enabled.

Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
2020-03-17 11:41:19 +01:00
Øyvind Rønningstad
1d5cb928dd soc: arm: Kconfig: Add config for NRF_SPU region sizes
Needs to be aware of the Kconfig NRF5340_CPUAPP_ERRATUM19.

Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
2020-03-17 11:41:19 +01:00
Øyvind Rønningstad
c5094b82f5 soc: arm: nrf53: defconfig: Add config for Erratum 19
Erratum 19: SPU region size is 32 kB instead of 16 kB.
The config should be used for alignment for data that must follow SPU
region boundaries, and to enable runtime checks when configuring SPU
regions.

Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
2020-03-17 11:41:19 +01:00
Andrew Boie
80a0d9d16b kernel: interrupt/idle stacks/threads as array
The set of interrupt stacks is now expressed as an array. We
also define the idle threads and their associated stacks this
way. This allows for iteration in cases where we have multiple
CPUs.

There is now a centralized declaration in kernel_internal.h.

On uniprocessor systems, z_interrupt_stacks has one element
and can be used in the same way as _interrupt_stack.

The IRQ stack for CPU 0 is now set in init.c instead of in
arch code.

The extern definition of the main thread stack is now removed,
this doesn't need to be in a header.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-03-16 23:17:36 +02:00
Gerard Marull-Paretas
ff8fea4ebb drivers: counter: stm32: enable support for H7 series
Enable counter driver support for H7 series. Tested with H743ZI MCU
using samples/drivers/counter/alarm.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-03-16 10:23:13 -05:00
Timo Teräs
6fd168e9a1 driver: uart: ns16550: convert to DT_INST_*
Change to code to use the automatically generated DT_INST_*
defines and remove the now unneeded configs and fixups.

Signed-off-by: Timo Teräs <timo.teras@iki.fi>
2020-03-14 02:22:05 +02:00
Jose Alberto Meza
64f8aa9e0d soc: arm: microchip: Expose PECI feature on MEC1501 SoC
Define PECI_XEC feature.

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2020-03-13 18:53:04 +02:00
Stephanos Ioannidis
685bf54829 soc: arm: qemu_cortex_a53: Use the refactored AArch64 interrupt system
This commit updates the `qemu_cortex_a53` platform to use the
refactored AArch64 interrupt system.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-03-13 09:59:59 +01:00
Stephanos Ioannidis
5ac617c817 soc: arm: xilinx_zynqmp: Use the refactored AArch32 interrupt system
This commit updates the `xilinx_zynqmp` platform to use the refactored
AArch32 interrupt system.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-03-13 09:59:59 +01:00
Vincent Wan
c58d8fcb79 soc: ti_simplelink: system power management for cc13x2_cc26x2
Add support for sleep states. Sleep state 1 corresponds to idle mode,
and Sleep state 2 corresponds to standby mode, as per the Technical
Reference Manual.

Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
2020-03-12 19:22:53 -06:00
Jukka Rissanen
0f1700a08b soc: arm: st_stm32: Add STM32F407XE
Add support for the STM32F407XE SoC.

Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
2020-03-12 20:18:39 +02:00
Pooja Karanjekar
173f636426 soc: silabs_exx32: Make HFRCO frequency configurable
This commit adds an option to configure the frequency
in Hz for the HFRCO clock source. The default value
for this option is 0 which skips the configuration of the HFRCO.
This feature is supported for efm32gg, efm32jg, efm32pg, efm32fg
and efm32mg SOCs currently.

Signed-off-by: Pooja Karanjekar <pooja.karanjekar@lemonbeat.com>
2020-03-12 09:00:21 -05:00
Kumar Gala
9213024696 drivers: gpio: stellaris: convert to DT_INST defines
Convert driver to use DT_INST_ defines.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-12 04:54:04 -06:00
Kumar Gala
dbcd856dc1 drivers: ethernet: stellaris: convert to DT_INST defines
Convert driver to use DT_INST_ defines.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-12 04:54:04 -06:00
Kumar Gala
aa98c7ba17 drivers: serial: pl011: convert to DT_INST defines
Convert driver to use DT_INST_ defines.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-12 04:53:30 -06:00
Andrei Gansari
3692da14ea soc: lpc55xxx define secure/non-secure core
Define secure related features on the lpc55xxx soc cores.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2020-03-12 12:24:12 +02:00
Andrei Gansari
b833aa1136 soc: lpc55xxx mpu areas defined from dts
Number of MPU regions obtained from MPU.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2020-03-12 12:24:12 +02:00
Gerard Marull-Paretas
f2b93fae5a soc: stm32: add support for stm32h743xx
Add support for STM32H743XX SoC series.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-03-11 17:10:58 +01:00
Daniel Leung
4700c93f3c soc: mec1501: wait for PLL to lock coming out of deep sleep
The 48MHz PLL on MEC1501 is shut off during deep sleep (i.e. heavy
sleep in datasheet). When coming out of deep sleep, this PLL needs
about 3ms to lock. Most peripherals are using this PLL as clock
source and timing would be off before PLL is locked. Example of
this is seen on serial console where garbage characters are sent
as the UART block is not pushing characters out at the configured
baud rate. This likely affects all other peripherals such as I2C
and eSPI. Luckily, there is a register to indicate whether the PLL
is ready. So spin on it when coming out of deep sleep.

Fixes #23207

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-03-11 10:13:41 -04:00
Kumar Gala
490494c58f drivers: entropy: sam: convert to DT_INST defines
Convert driver to use DT_INST_ defines.  The preferred defines for
drivers are DT_INST_.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-11 07:59:38 -06:00
Kumar Gala
70d78412f7 drivers: watchdog: sam: convert to DT_INST defines
Convert driver to use DT_INST_ defines.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-11 07:59:38 -06:00
Kumar Gala
76e0cf63b3 drivers: ps2: mchp_xec: convert to DT_INST defines
Convert driver to use DT_INST_ defines.  The preferred defines for
drivers are DT_INST_.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-11 07:59:38 -06:00
Kumar Gala
c68a1d427d drivers: espi: mchp_xec: convert to DT_INST defines
Convert driver to use DT_INST_ defines.  The preferred defines for
drivers are DT_INST_.  The driver mostly used DT_INST_ defines but
a few IRQ priority defines needed conversion.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-11 07:59:38 -06:00
Kumar Gala
9a8831b781 drivers: counter: mchp_xec: convert to DT_INST defines
Convert driver to use DT_INST_ defines.  The preferred defines for
drivers are DT_INST_.

As part of this change we utilize the device tree for GIRQ info and
rename timer3 to 2 since we are doing this by instance number.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-11 07:59:38 -06:00
Kumar Gala
d6b6ebe522 drivers: counter: mchp_xec: Fix dts prop type for max-value
The max-value should just be an int and not an array.  Change the type
to 'int' in the binding and fixup the driver to match.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-11 07:59:38 -06:00
Kumar Gala
3e6614a330 drivers: uart: msp432p4xx: convert to DT_INST defines
Convert driver to fully use DT_INST_ defines.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-11 07:59:38 -06:00
Kumar Gala
e04a367408 drivers: mcux_rtc: convert to DT_INST defines
Convert driver to use DT_INST_ defines.  Replace dts_fixup.h use
for DT_RTC_0_NAME with DT_INST_0_NXP_KINETIS_RTC_LABEL to be
consistent.  Also, remove the aliases that had been used for this
driver in various nxp_k*.dtsi.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-11 07:59:38 -06:00
Kumar Gala
a49de1543b drivers: entropy: mcux_trng: convert to DT_INST defines
Convert driver to use DT_INST_ defines.  The preferred defines for
drivers are DT_INST_.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-11 07:59:38 -06:00
Kumar Gala
a9e68d61df drivers: clock_control: mcux_sim: convert to DT_INST defines
Convert driver to use DT_INST_ defines.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-11 07:59:38 -06:00
Kumar Gala
a32eed06f7 drivers: clock_control: mcux_pcc: convert to DT_INST defines
Convert driver to use DT_INST_ defines.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-11 07:59:38 -06:00
Kumar Gala
6ad07b6a2a drivers: clock_control: mcux_mcg: convert to DT_INST defines
Convert driver to use DT_INST_ defines.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-11 07:59:38 -06:00
Kumar Gala
ee53047aff drivers: clock_control: mcux_ccm: convert to DT_INST defines
Convert driver to use DT_INST_ defines.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-11 07:59:38 -06:00
Kumar Gala
41fcf784e9 drivers: mcux_gpt: convert to DT_INST defines
Convert driver to use DT_INST_ defines and remove Kconfig per instance
enablement in favor of DT_INST_ define existing.  Also, remove the
aliases that had been used for this driver in nxp_rt.dtsi.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-11 07:59:38 -06:00
Andrzej Głąbek
3e93f9f67d modules: hal: nordic: Fix translation of peripheral symbols
Update the hal_nordic module revision, to apply the following changes:

nrfx_config: Fix translation of symbols for _S or _NS only peripherals

For peripherals with only one type of access available (either secure
or non-secure), the common symbol translation scheme cannot be used
as it leads to mapping to non-existing symbols (e.g. NRF_FICR_NS).
Instead, use fixed translations for these symbols (e.g. NRF_FICR to
NRF_FICR_S, only for secure images).

nrfx_config: Add missing _S/_NS symbol translations for nRF5340/nRF9160

Add translations of names with _S and _NS suffixes for peripheral
access symbols that are available for a given chip but were not used
so far in any nrfx HAL or driver, to make the lists of translations
complete and consistent.

This commit corrects also the translation of NRF_I2S symbol for nRF5340
whose name for this SoC contains also the index 0 (so it needs to be
handled similarly like NRF_PDM0 is).

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2020-03-10 17:21:27 +01:00
Gerard Marull-Paretas
5df13cb910 soc: arm: stm32: configure LDO supply on H7 init
Configure the LDO supply when initializing H7 (M7) SoC. I have
observed MCU hanging on LL_PWR_IsActiveFlag_VOS() wait loop when
doing a cold boot if LDO supply is not explicitely enabled.
According to the datasheet LDO should be enabled by default,
however HAL examples also configure LDO, so there may be a
reason to perform such step.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-03-10 10:22:08 -05:00
Paul M. Bendixen
878faa9e5a soc: arm: st_stm32 : Add stm32f303Xe version
Added stm32f303Xe based on the stm32f303Xc Kconfig

Signed-off-by: Paul M. Bendixen <paulbendixen@gmail.com>
2020-03-10 15:08:59 +02:00
Gerard Marull-Paretas
244ebb85bd soc: stm32: add support for stm32h750xx
Add support for STM32H750XX SoC.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-03-10 14:48:06 +02:00
Thomas Stranger
a44e9f496e soc: stm32g0: Add support for STM32 IWDG
The driver for STM32's independent watchdog already exists and is
compatible with the stm32g0 SoC. Enable the independent watchdog
for the stm32g0 series for use with this driver.

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
2020-03-10 14:46:07 +02:00
Gerson Fernando Budke
1203547034 soc: arm: atmel: sam4s: Add missing symbols for usart
This add dts_fixup and soc_pinmap to enable usart serial driver.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2020-03-10 14:43:14 +02:00
Gerson Fernando Budke
2da3b0a7fd soc: arm: atmel: sam4s: Fix code align
Fix dts_fixup.h code align.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2020-03-10 14:43:14 +02:00
Francois Ramu
abd8ca94c2 soc: arm: stm32g474 config device
This patch aligns the Kconfig.defconfig.stm32g474re to the
Kconfig.defconfig.stm32g431rb

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2020-03-09 17:26:40 +02:00
Daniel Leung
2ac3a85273 soc: mec1501: wait for UART FIFO clear before deep sleep
It is observed that after each test, weird characters appear on
console. This problem goes away if deep sleep is disabled.
The theory is that the CPU runs to deep sleep (_sys_suspend())
faster than UART can shift all the bits out. If we spin wait
for UART FIFO to clear, this is no longer an issue. This is
circumstantial evidence to the theory. So for now, put in
a workaround to spin wait for UART FIFO to clear before
going into deep sleep.

Relates to #22885

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-02-28 20:18:13 +02:00
Alexander Wachter
b96477dd69 SoC: SAM3x and SAM4: Add the Flash Controller to the DT
This commit adds Device-Tree instances of the Flash controller
to the SAM3X, SAM4E and SAM4S series. The Flash-Controller
is used to get the unique device identifier.

Signed-off-by: Alexander Wachter <alexander@wachter.cloud>
2020-02-27 21:14:54 +01:00
Alexander Wachter
4cfd4a707d SoC: stm32: Include LL utilities if HWINFO is selected
Include stm32XXxx_ll_utils.h in soc.h for every stm32 SoC,
if CONFIG_HWINFO_STM32 is selected.

Signed-off-by: Alexander Wachter <alexander@wachter.cloud>
2020-02-27 21:14:54 +01:00
Ioannis Glaropoulos
a062edd805 boards: arm: silabs_exx32: correct Kconfig option prompt
Fix a typo in the option prompt for Kconfig symbol
SOC_SERIES_EFM32GG11B.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-02-25 14:07:45 +02:00
Abhishek Shah
f64cd1a5db soc: arm64: qemu-cortex-a53: Add MMU support
Add qemu-cortex-a53 memory regions with proper attributes
to translation tables. Minimal regions to execute "hello_world"
are added as of now, More granular memory regions should be
added later as per the requirement.

Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
2020-02-20 17:24:59 +02:00
Gerson Fernando Budke
6ea8ae7a9a soc: arm: atmel: sam4e: Fix USART1 soc_pinmap
The USART1 soc_pinmap have wrong TXD1 pin definition. This fix port and
function definition.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2020-02-15 16:35:01 -06:00
Gerson Fernando Budke
09eab93889 soc: arm: atmel: sam4e: Add missing usart dts_fixup
Add mising dts_fixups symbols to allow enable usart driver. This fix
align code on dts_fixups too.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2020-02-15 16:35:01 -06:00
Ulf Magnusson
378d6b137a kconfig: Replace non-defconfig single-symbol 'if's with 'depends on'
Same deal as in commit eddd98f811 ("kconfig: Replace some single-symbol
'if's with 'depends on'"), for the remaining cases outside defconfig
files. See that commit for an explanation.

Will do the defconfigs separately in case there are any complaints
there.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2020-02-12 10:32:34 -06:00
Ulf Magnusson
a42a42cd5a kconfig: Replace defconfig singe-symbol 'if's with 'depends on'
Same deal as in commit eddd98f ("kconfig: Replace some single-symbol
'if's with 'depends on'"), for all symbols defined within defconfig
files. See that commit for an explanation.

Maybe 'if's were used originally to mirror the 'if's in the main Kconfig
files, and then it got copied around by people assuming 'if' must work
differently from 'depends on'. It doesn't match in every spot at least.
Better to keep it simple and just consistently use 'depends on' when
it's a single symbol/choice I think. Helps reinforce that 'if' isn't
magic too.

Verified by printing all Kconfig menu nodes (symbols, choices, menus,
etc.) before and after the change and diffing (should show no
difference).

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2020-02-12 10:32:13 -06:00
Erwan Gouriou
9631709ca4 soc: stm32h7: Move PWR init code in soc init function
Move PWR init code out of clock control driver and
put SMPS related function under SMPS condition as it
is not supported by all soc variants of the series.

Fixes #22363

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-02-11 17:41:49 +02:00
Kumar Gala
28da5fdde7 sam0: flash: Fix build issue reported by flash_shell sample
The DT_FLASH_DEV_NAME define used by the sample was set to a define
symbol that was never generated.  Change it to use
DT_INST_0_ATMEL_SAM0_NVMCTRL_LABEL on the sam0 family of SoCs that
had this issue.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-02-08 10:29:28 -06:00
Ulf Magnusson
c5839f834b kconfig: Remove assignments to CONFIG_<arch> syms and hide them
All board defconfig files currently set the architecture in addition to
the board and the SoC, by setting e.g. CONFIG_ARM=y. This spams up
defconfig files.

CONFIG_<arch> symbols currently being set in configuration files also
means that they are configurable (can be changed in menuconfig and in
configuration files), even though changing the architecture won't work,
since other things get set from -DBOARD=<board>. Many boards also allow
changing the architecture symbols independently from the SoC symbols,
which doesn't make sense.

Get rid of all assignments to CONFIG_<arch> symbols and clean up the
relationships between symbols and the configuration interface, like
this:

1. Remove the choice with the CONFIG_<arch> symbols in arch/Kconfig and
   turn the CONFIG_<arch> symbols into invisible
   (promptless/nonconfigurable) symbols instead.

   Getting rid of the choice allows the symbols to be 'select'ed (choice
   symbols don't support 'select').

2. Select the right CONFIG_<arch> symbol from the SOC_SERIES_* symbols.
   This makes sense since you know the architecture if you know the SoC.

   Put the select on the SOC_* symbol instead for boards that don't have
   a SOC_SERIES_*.

3. Remove all assignments to CONFIG_<arch> symbols. The assignments
   would generate errors now, since the symbols are promptless.

The change was done by grepping for assignments to CONFIG_<arch>
symbols, finding the SOC_SERIES_* (or SOC_*) symbol being set in the
same defconfig file, and putting a 'select' on it instead.

See
https://github.com/ulfalizer/zephyr/commits/hide-arch-syms-unsquashed
for a split-up version of this commit, which will make it easier to see
how stuff was done. This needs to go in as one commit though.

This change is safer than it might seem re. outstanding PRs, because any
assignment to CONFIG_<arch> symbols generates an error now, making
outdated stuff easy to catch.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2020-02-08 00:50:08 -06:00
Markus Fuchs
53e3c310b5 dts: arm: stm32f4: Add CRYP support for STM32F4xx SoC series
Add Cryptographic Accelerator support for STM32F415/417 and STM32F43x
devices.

Signed-off-by: Markus Fuchs <markus.fuchs@de.sauter-bc.com>
2020-02-07 10:45:51 -06:00
Gerson Fernando Budke
f3663292bc soc: arm: sam4s: Add spi driver support
Add device tree fixups and pinmap to enable spi driver.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2020-02-05 14:25:23 -06:00
Francois Ramu
612f29ee27 soc: arm: stm32g4 disable sleep mode
This patch allows successive reflashing operation
on nucleo_g431rb boards

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2020-02-05 13:48:15 -06:00
Gerson Fernando Budke
49ccf28242 drivers: spi: sam: Add SPI CS soc_pinmap for sam4e soc
Add SPI CS soc_pinmap definitions to enable SPI driver on sam4e series.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2020-02-05 10:14:51 -05:00
Peter Bigot
d869a6c766 drivers: gpio_imx: add support for pin validation
Add the common config structure as a prefix of the driver-specific
config structure and use the devicetree GPIO pin counts to initialize
it.  Not all aliases appear to be present, but using instances breaks
because the ports used by different boards do not always start with
the first.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2020-02-05 12:00:36 +01:00
Gerson Fernando Budke
4a5de7bb87 soc: arm: atmel: Add sam4e mcu
Add sam4e related soc files.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2020-02-04 17:51:41 -05:00
Gerson Fernando Budke
f21aaeffaa soc: atmel: sam: Add spi pinmap
This add SPI pinmap definitions to spi0/1 for SAMV71 series.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2020-02-04 14:55:45 -05:00
Gerson Fernando Budke
7422cff736 drivers: spi: sam: Enable generic config
The current sam spi driver uses soc dependent name which duplicate
configuration to enable other platforms. This refactor current
definitions to a generic way to reuse symbols by multi soc definitions.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2020-02-04 14:55:45 -05:00
Gerson Fernando Budke
9e52789054 soc: arm: atmel: Add samv71 mcu
Add samv71 related soc files.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2020-02-04 08:56:19 -06:00
Henrik Brix Andersen
a28f8fbef5 soc: arm: nxp: ke1xf: add option for keeping watchdog enabled at boot
Add option for keeping the watchdog timer of the NXP Kinetis KE1xF SoC
series enabled at boot with a configurable, initial timeout.

This removes the risk of failure from when z_arm_watchdog_init()
disables the watchdog timer until the application code configures a
timeout and re-enables the watchdog timer.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-02-03 14:58:01 -08:00
Oane Kingma
fff0a2b5e7 dts / boards / soc: Add support for SiLabs Gecko watchdog
This commit adds the following:
- device tree bindings for Gecko watchdog driver
- EFM32PG SOC support for the watchdog driver
- EFM32PG board support for the watchdog driver
- DTS aliases for testing with default watchdog driver test

Signed-off-by: Oane Kingma <o.kingma@interay.com>
2020-02-03 11:25:40 -08:00
Carlo Caione
0958673ee1 arch: arm64: Enable shared IRQ line for UART
Enable the shared IRQ for the UART line and enable the remaining tasks
that depends on a separated declaration of the TX/RX/Err/... IRQs.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2020-02-01 08:08:43 -05:00
Carlo Caione
a61290e1a3 arch: arm64: Add support for qemu_cortex_a53 board
This patch introduces support for the qemu_cortex_a53 board emulated
using QEMU (virt platform) adding SoC, board and DTS files.

| ./scripts/sanitycheck -p qemu_cortex_a53
|
| Total complete:  190/ 190  100%  skipped:   40, failed:    0
| 150 of 150 tests passed (100.00%), 0 failed,
|     40 skipped with 0 warnings in 580.93 seconds

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2020-02-01 08:08:43 -05:00
Ivo Clarysse
0c8a99582e dts: arm: stm32f4: add CAN_2 controller
Add the CAN controller device tree node for CAN_2 of the STM32F4 SoC
series.

Signed-off-by: Ivo Clarysse <ivo@bcdevices.com>
2020-01-30 14:27:28 -05:00
Christian Taedcke
fbbf68d63c soc: silabs_exx32: Support all gpio ports on efm32jg and efm32pg
This commit adds the remaining gpio ports I, J and K to the device
tree and dts_fixup headers of the EFM32JG12B and EFM32PG12B SoCs.

Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
2020-01-30 09:15:53 -06:00
Benjamin Valentin
6fd08da96a soc: atmel_sam0: remove CONFIG_ENTROPY_NAME from dts_fixup.h
It's not needed anymore and causes build failures.

Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
2020-01-30 08:44:30 -06:00
Benjamin Valentin
9f548b94cd soc: atmel_sam0: remove obsolete include
`cortex_m/exc.h` is not needed anymore and ceased to exist.

Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
2020-01-30 08:44:30 -06:00
Francois Ramu
4ef62a2db7 soc: arm: st_stm32: configure stm32g431 series
This patch cleans the defconfig of the STM32G431
     device from STMicroelectronics.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2020-01-30 08:30:15 -06:00
Francois Ramu
fafd20ca93 soc: arm: st_stm32: add stm32g474 series
This patch introduces the support of the STM32G474
     device from STMicroelectronics.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2020-01-30 08:30:15 -06:00
Christian Taedcke
4ead400d79 arm: exx32: Add Silabs EFM32JG12B soc files
The Silicon Labs EFM32 Jade Gecko MCU includes:

    * Cortex-M3 core at 40MHz
    * up to 1024KB of flash and 256KB of RAM
    * multiple low power peripherals

This is basically the same as the EFM32 Pearl Gecko, but with an ARM
Cortex-M3 core instead of a Cortex-M4F.

Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
2020-01-30 07:06:54 -06:00
Scott Branden
54ce0b2d34 arm: Add Broadcom Valkyrie SoC support
Add initial support for Broadcom Valkyrie SoC as part of Zephyr.

Signed-off-by: Scott Branden <scott.branden@broadcom.com>
2020-01-30 03:54:01 -06:00
Henrik Brix Andersen
be3cb485eb soc: arm: nxp: kinetis: disable watchdog init if bootloader is enabled
Disable the early watchdog initialization for the NXP Kinetis series
if the application is to be chain-loaded by mcuboot.

The early watchdog initialization must only take place once and needs
to happen within a SoC specific number of CPU clock cycles after
reset.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-01-29 15:12:24 -06:00
Henrik Brix Andersen
282d85c3f4 soc: arm: nxp: kinetis: unify CONFIG_WDOG_INIT Kconfig option
Move CONFIG_WDOG_INIT for the NXP Kinetis series to the top-level
Kinetis Kconfig file and enable it where needed.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-01-29 15:12:24 -06:00
Henrik Brix Andersen
9523f792da soc: nxp: kinetis: kw4xz: move watchdog init to z_arm_watchdog_init
Move the NXP Kinetis KW4xZ watchdog initialization code to
z_arm_watchdog_init() and make it optional based on CONFIG_WDOG_INIT.

This brings the KW4xZ in line with the other NXP Kinetis series SoC
implementations.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-01-29 15:12:24 -06:00
Henrik Brix Andersen
f9f7379549 soc: nxp: kinetis: kl2x: move watchdog init to z_arm_watchdog_init
Move the NXP Kinetis KL2x watchdog initialization code to
z_arm_watchdog_init() and make it optional based on
CONFIG_WDOG_INIT.

This brings the KL2x in line with the other NXP Kinetis series SoC
implementations.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-01-29 15:12:24 -06:00
Kwon Tae-young
271bd8bcea soc: stm32l1: Add support for STM32 IWDG
The driver for STM32's independent watchdog already exists and is
compatible with the stm32l1 SoC. Enable the independent watchdog
for the stm32l1 series for use with this driver.

Signed-off-by: Kwon Tae-young <tykwon@m2i.co.kr>
2020-01-29 11:20:57 -06:00
Ulf Magnusson
1b394ad153 soc: ti_simplelink: kconfig: Refactor CCFG flash block handling
Instead of having TI_CCFG_PRESENT as a symbol that's only defined in
soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.defconfig.series and y when
SOC_SERIES_CC13X2_CC26X2 is enabled, turn it into a helper symbol that's
selected by SOC_SERIES_CC13X2_CC26X2.

This avoids having a symbol that's only defined in a Kconfig.defconfig
file, which is confusing. It also makes things a bit more generic, in
case other boards with CCFGs are added.

Also rename it to HAS_TI_CCFG to be consistent with other helper
symbols, and add a help text.

Flagged by scripts/kconfig/lint.py.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2020-01-29 09:41:46 -06:00
Krzysztof Chruscinski
510102dd71 soc: arm: nordic_nrf: nrf52: Add workaround for anomaly 132
Added delay before starting low frequency clock for the first time to
ensure that anomaly conditions are not met. Delay is configurable and
might be disabled.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2020-01-29 15:38:55 +01:00
Andrzej Głąbek
01648cc099 Revert "soc: nrf5340: Fix busy waiting on nRF5340 application core"
This reverts commit 49bd19f3f2,
as the patch it contains is no longer needed after nrfx is updated
to version 2.1.0.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2020-01-29 15:00:45 +01:00
Andrzej Głąbek
7899b1f5b6 modules: hal_nordic: Update nrfx to version 2.1.0
Update the hal_nordic module revision, to switch to nrfx 2.1.0.

Because the list of peripherals for nRF5340 has changed as follows:
- SPIM2 has been renamed to SPIM4
- SPIM2-3, SPIS2-3, TWIM2-3, TWIS2-3, and UARTE2-3 have been added
a couple of related corrections needed to be applied in dts and Kconfig
files, plus the spi_nrfx_spim driver has been extended with the support
for SPIM4.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2020-01-29 15:00:45 +01:00
Henrik Brix Andersen
5a82424767 dts: arm: stm32f3: add can controller
Add the CAN controller device tree node for CAN_1 of the STM32F3 SoC
series.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-01-29 09:47:27 +01:00
Sarvesh Patkar
4f2c107389 drivers: flash: stm32: Update flash driver implementation
Remove soc/arm/st_stm32/stm32YY/flash_registers.h files.
Change register accesses in stm32 flash drivers to use FLASH_TypeDef
from modules/hal/stm32/stm32cube/stm32YYxx/soc/stm32xxxxxx.h.

Fixes #16235

Signed-off-by: Sarvesh Patkar <psarvesh314@gmail.com>
2020-01-28 15:30:12 -06:00
Francois Ramu
25700ace0a soc: arm: stm32: define the heap size when enabling dma feature
when DMA IP is enabled on stm32 series,
the heap size must be configured to large value
because of dma channels configuration.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2020-01-28 12:58:44 -06:00
Jose Alberto Meza
592e0afdf3 soc: arm: microchip: Update fixup for priorities
Avoid exposing unnecessary details for eSPI IRQ priorities.

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2020-01-28 20:13:36 +02:00
Jonas Eriksson
3e64e751b6 soc: stm32f1: Add support for stm32f1xx SoCs
Define stm32f100xx family, tested using stm32vl_disco
(stm32f100rb).

Signed-off-by: Jonas Eriksson <jonas@upto.se>
2020-01-28 08:30:52 -06:00
Ulf Magnusson
cf89ba33ea global: Fix up leading/trailing blank lines in files
To make the updated test in
https://github.com/zephyrproject-rtos/ci-tools/pull/121 clean, though it
only checks modified files.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2020-01-27 17:41:55 -06:00
Peter Bigot
02ae343100 treewide: use full path to uart.h header
The build infrastructure should not be adding the drivers subdirectory
to the include path.  Fix the legacy uses that depended on that
addition.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2020-01-26 17:52:12 +01:00
Peter Bigot
5e470ec3bf treewide: use full path to gpio/gpio_mmio32.h header
The build infrastructure should not be adding the drivers subdirectory
to the include path.  Fix the legacy uses that depended on that
addition.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2020-01-26 17:52:12 +01:00
Henrik Brix Andersen
cd28b0b6d2 soc: arm: nxp: ke1xf: remove unused SPI dts fixups
Remove unused SPI device tree fixups from the NXP KE1xF SoC.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-01-24 21:31:25 -05:00
Ulf Magnusson
d28e1f6bcb kconfig: Turn pointless 'menuconfig's into 'config's
Same deal as in commit 677f1e6 ("config: Turn pointless/confusing
'menuconfig's into 'config's"), for a newly-introduced stuff.

Also clean up headers to be consistent with recent cleanups.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2020-01-24 21:30:17 -05:00
Oane Kingma
e91da4ae45 soc/arm/silabs_exx32: Add support for EFM32GG11B SoC
This commit adds support for the Silicon Labs EFM32GG11B
series of SoCs.

Signed-off-by: Oane Kingma <o.kingma@interay.com>
2020-01-24 10:28:33 -06:00
Benjamin Valentin
2539a1751d soc: atmel_sam0: update dts_fixup.h for TRNG
Update dts_fixup.h to re-use the SAM TRNG driver.

Signed-off-by: Benjamin Valentin <benpicco@googlemail.com>
2020-01-23 12:40:59 +01:00
Øyvind Rønningstad
05f0d85b6a extensions.cmake: Replace TEXT_START with ROM_START
In zephyr_linker_sources().
This is done since the point of the location is to place things at given
offsets. This can only be done consistenly if the linker code is placed
into the _first_ section.

All uses of TEXT_START are replaced with ROM_START.

ROM_START is only supported in some arches, as some arches have several
custom sections before text. These don't currently have ROM_START or
TEXT_START available, but that could be added with a bit of refactoring
in their linker script.

No SORT_KEYs are changed.

This also fixes an error introduced when TEXT_START was added, where
TEXT_SECTION_OFFSET was applied to riscv's common linker.ld instead of
to openisa_rv32m1's specific linker.ld.

Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
2020-01-23 03:22:59 -08:00
Ulf Magnusson
77743741e6 soc: psoc6: kconfig: Do not select CPU_CORTEX_M_HAS_DWT on Cortex-M0
CPU_CORTEX_M_HAS_DWT depends on

    !CPU_CORTEX_M0 && !CPU_CORTEX_M0PLUS

, but SOC_SERIES_PSOC62 unconditionally selects it, even for
SOC_PSOC6_M0. This forces CPU_CORTEX_M_HAS_DWT on on Cortex-M0.

Fix it by moving the selects for CPU capabilities to the more specific
SOC_PSOC6_{M0,M4} symbols. This seems more readable than adding a
condition to the 'select CPU_CORTEX_M_HAS_DWT'.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2020-01-23 09:39:01 +01:00
Robert Lubos
65ec2d9701 boards: nrf52811_pca10056: Enable nRF 802.15.4 driver by default
nrf52811_pca10056 board should enable nRF 802.15.4 radio driver
automatically when 802.15.4 subsystem is enabled, as other Nordic
802.15.4-compliant boards do.

Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
2020-01-22 14:58:40 +01:00
Henrik Brix Andersen
75549fc560 soc: arm: nxp: kinetis: k6x: enable RTC device
Enable the RTC counter present in the NXP K6x SoC if CONFIG_COUNTER is
enabled. Add the needed dts fixup for the RTC device.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-01-22 06:27:30 -06:00
Antony Pavlov
fc1cdf233d soc: arm: stm32l1: Add STM32L152Xe stuff
The STM32L151 and STM32L152 differ in that
the STM32L152 features an LCD controller.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
2020-01-20 18:08:43 -06:00
Ioannis Glaropoulos
7fee3efd99 soc: arm: remove explicit selection of already selected symbols
CPU_CORTEX_M_HAS_SYSTICK and CPU_CORTEX_M_HAS_VTOR do not need
to be explicitely selected in SoC/Boards definitions of
platforms implementing the Cortex-M mainline architecture; they
are already selected by ARMV7_M_ARM8_M_MAINLINE Kconfig symbol.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-01-20 17:23:42 -05:00
Ioannis Glaropoulos
1d60bca3fe soc: arm: arm: Select CPU DWT feature symbol for ARM Cortex-M SoCs
The Data Watchpoint and Trace (DWT) is an optional debug unit
for the Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+)
that provides watchpoints, data tracing and system profiling
capabilities. We select it for the ARM Cortex-M SoCs
- Beetle
- Musca A, Musca B
since it is present in these SoCs.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-01-20 14:05:47 +01:00
Stephanos Ioannidis
155c1f5ffe soc: arm: ti_simplelink: Select CPU DWT feature symbol
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-20 14:05:47 +01:00
Stephanos Ioannidis
4cef583dc7 soc: arm: ti_lm3s6965: Select CPU DWT feature symbol
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-20 14:05:47 +01:00
Stephanos Ioannidis
88d79a49d2 soc: arm: st_stm32: Select CPU DWT feature symbol
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-20 14:05:47 +01:00
Stephanos Ioannidis
f9453832aa soc: arm: silabs_exx32: Select CPU DWT feature symbol
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-20 14:05:47 +01:00
Stephanos Ioannidis
d658883a7c soc: arm: nxp_lpc: Select CPU DWT feature symbol
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-20 14:05:47 +01:00
Stephanos Ioannidis
09843584ec soc: arm: nxp_kinetis: Select CPU DWT feature symbol
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-20 14:05:47 +01:00
Stephanos Ioannidis
16bb973044 soc: arm: nxp_imx: Select CPU DWT feature symbol
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-20 14:05:47 +01:00
Stephanos Ioannidis
8095cafaa1 soc: arm: nordic_nrf: Select CPU DWT feature symbol
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-20 14:05:47 +01:00
Stephanos Ioannidis
3d7deff3fb soc: arm: microchip_mec: Select CPU DWT feature symbol
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-20 14:05:47 +01:00
Stephanos Ioannidis
02090592ab soc: arm: psoc6: Select CPU DWT feature symbol
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-20 14:05:47 +01:00
Stephanos Ioannidis
d32546fb7e soc: arm: atmel_sam: Select CPU DWT feature symbol
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-20 14:05:47 +01:00
Kumar Gala
b1602c8e39 arm: Removed support for CC2650
The SoC, driver, and board support for the CC2650 and CC2650 Sensortag
aren't currently supported and we are removing them as such.  If anyone
is interesting in supporting this platform we can easily recovery it
from git.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-01-18 09:27:55 -06:00
Ulf Magnusson
4e85006ba4 dts: Rename generated_dts_board*.{h,conf} to devicetree*.{h,conf}
generated_dts_board.h is pretty redundant and confusing as a name. Call
it devicetree.h instead.

dts.h would be another option, but DTS stands for "devicetree source"
and is the source code format, so it's a bit confusing too.

The replacement was done by grepping for 'generated_dts_board' and
'GENERATED_DTS_BOARD'.

Two build diagram and input-output SVG files were updated as well, along
with misc. documentation.

hal_ti, mcuboot, and ci-tools updates are included too, in the west.yml
update.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2020-01-17 17:57:59 +01:00
Henrik Brix Andersen
774367b14a soc: nxp: k6x: enable bandgap buffer if temperature sensor is enabled
Enable the bandgap buffer on the NXP Kinetis K6x SoC series Power
Management Controller (PMC) if the internal temperature sensor is in
use.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-01-16 17:30:42 -06:00
Roland Ma
b0bdf91e11 boards: arm: Add board definition for stm32 nucleo_f767zi
Added board definition additions for stm32 nucleo_f767zi
board.

Signed-off-by: Roland Ma <rolandma@yahoo.com>
2020-01-16 22:51:13 +01:00
Roland Ma
01049b73be dts: arm: st: Add dts and soc additions for stm32 F767ZI board
Added dts additions for stm32 nucleo f767zi board, also added
and modified soc addtions for thet board.
Updated dts reference file name.
Updated yaml to take out adc for now.

Signed-off-by: Roland Ma <rolandma@yahoo.com>
2020-01-16 22:51:13 +01:00
Andrei Gansari
c9301ad8a3 soc: enables flash on LPC55xxx SoCs
Enables IAP Flash Controller device on LPC55xxx SoCs.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2020-01-16 08:19:46 -06:00
Maureen Helm
ee65932c96 drivers: watchdog: Refactor mcux wdog driver to use generated dts macros
Refactors the mcux wdog driver to use generated device tree macros
directly. Removes now unused dts fixup macros from kinetis socs.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-01-15 18:02:19 -05:00
Maureen Helm
9329c0db27 drivers: counter: Refactor mcux rtc driver to use generated dts macros
Refactors the mcux rtc driver to use generated device tree macros
directly. Removes now unused dts fixup macros from kinetis socs.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-01-15 18:02:19 -05:00
Maureen Helm
94c5a75998 drivers: spi: Refactor mcux dspi driver to use generated dts macros
Refactors the mcux dspi driver to use generated device tree macros
directly. Removes now unused dts fixup macros from kinetis socs.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-01-15 18:02:19 -05:00
Maureen Helm
93b457f4da drivers: serial: Refactor mcux lpsci driver to use generated dts macros
Refactors the mcux lpsci driver to use generated device tree macros
directly. Removes now unused dts fixup macros from i.mx rt and kinetis
socs.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-01-15 18:02:19 -05:00
Maureen Helm
5df8b5d63e drivers: serial: Refactor mcux uart driver to use generated dts macros
Refactors the mcux uart driver to use generated device tree macros
directly. Removes now unused dts fixup macros from kinetis socs.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-01-15 18:02:19 -05:00
Maureen Helm
806813bb6a drivers: i2c: Refactor mcux i2c driver to use generated dts macros
Refactors the mcux lpi2c driver to use generated device tree macros
directly. Removes now unused dts fixup macros from kinetis socs.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-01-15 18:02:19 -05:00
Maureen Helm
c0e2c6369b soc: nxp_imx: Fix counter_basic_api test for i.mx rt boards
The counter_basic_api test was broken for i.mx rt boards when we
refactored the mcux gpt driver to use generated device tree macros in
commit b8ad9969ef.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-01-15 11:30:44 -05:00
Håkon Øye Amundsen
e3da8cc18c soc: nordic: add HAS_HW_NRF_ACL for nrf53 net core
The network core has the ACL peripheral, reflect this in the
SoC kconfig.

Signed-off-by: Håkon Øye Amundsen <haakon.amundsen@nordicsemi.no>
2020-01-15 14:13:05 +01:00
Maureen Helm
b541962cce soc: nxp_kinetis: Remove extra blank line at end of ke1xf dts fixup
Removes an extra blank line at the end of the ke1xf device tree fixup
file.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-01-14 11:10:27 -05:00
Maureen Helm
b8ad9969ef drivers: counter: Refactor mcux gpt driver to use generated dts macros
Refactors the mcux gpt driver to use generated device tree macros
directly. Removes now unused dts fixup macros from i.mx rt socs.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-01-14 11:10:27 -05:00
Maureen Helm
9e14543c19 drivers: gpio: Refactor mcux igpio driver to use generated dts macros
Refactors the mcux igpio driver to use generated device tree macros
directly. Removes now unused dts fixup macros from i.mx rt socs.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-01-14 11:10:27 -05:00
Maureen Helm
a2082303b8 drivers: serial: Refactor mcux lpuart driver to use generated dts macros
Refactors the mcux lpuart driver to use generated device tree macros
directly. Removes now unused dts fixup macros from i.mx rt and kinetis
socs.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-01-14 11:10:27 -05:00
Maureen Helm
7242660399 drivers: i2c: Refactor mcux lpi2c driver to use generated dts macros
Refactors the mcux lpi2c driver to use generated device tree macros
directly. Removes now unused dts fixup macros from i.mx rt and kinetis
socs.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-01-14 11:10:27 -05:00
Vincent Wan
ce90e24d25 kconfig: deprecate TI cc2650_sensortag and cc2650 SoC
Adding Kconfig settings to warn anyone trying to build for this
platform of its pending deprecation in 2.2.0.

Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
2020-01-13 10:21:12 -05:00
Christian Taedcke
20aa2bcf05 boards: efr32_slwstk6061a: Add support for spi nor flash
This commit adds support for the on-board flash MX25R8035F that is
directly connected to the efr32fg soc.

Signed-off-by: Christian Taedcke <hacking@taedcke.com>
2020-01-10 07:14:35 -06:00
Christian Taedcke
0201d182a8 boards: efr32mg_sltb004a: Add support for spi nor flash
This commit adds support for the on-board flash MX25R8035F that is
directly connected to the efr32mg soc.

Signed-off-by: Christian Taedcke <hacking@taedcke.com>
2020-01-10 07:14:35 -06:00
Marcin Szymczyk
2d6c6959f9 soc: nrf91: add power management
Only System OFF mode is supported.

Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
2020-01-10 13:09:44 +01:00
Marcin Szymczyk
32b3ab2354 soc: nrf53: add power management
Only System OFF mode is supported.

Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
2020-01-10 13:09:44 +01:00
Stephanos Ioannidis
d314253fbb soc: arm: xilinx_zynqmp: Relocate platform-specific initialisation.
This commit relocates the exception vector table address range
configuration routine that was previously implemented as part of
Cortex-R architecture reset function to SoC platform-specific
initialisation routine.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-10 10:34:17 +01:00
Ryan QIAN
7f75e4f83b soc: arm: nxp_imx: rt: add device support i.MX RT1010
- Add device support for i.MXRT1010

Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2020-01-09 16:29:22 -06:00
Stephanos Ioannidis
09ee834b4c soc: arm: xilinx_zynqmp: Refactor for multi-arch support.
The Xilinx ZynqMP SoC embeds both Cortex-R "RPU" and Cortex-A "APU"
cores.

Since the current Zephyr architecture cannot support AMP of Cortex-R
and Cortex-A within the same project, the RPU and APU should be
considered separate platforms and handled accordingly.

This commit re-purposes the SOC_XILINX_ZYNQMP symbol as a helper symbol
indicating that Xilinx ZynqMP SoC is used, and adds a new symbol,
SOC_XILINX_ZYNQMP_RPU, for specifying the actual build target platform.

When Cortex-A support is added in the future, SOC_XILINX_ZYNQMP_APU
symbol should be added and used to conditionally handle APU-specific
code.

For more details, refer to the issue #20217.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-07 17:17:12 +01:00
Henrik Brix Andersen
ebb4126cbe soc: nxp: ke1xf: rename ftm instances to pwm to match other SoCs
Rename the NXP FTM instances in the KE1xF SoC to PWM to match the
other SoCs/boards using the FlexTimer as PWM generator.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-01-06 10:03:20 -06:00
Henrik Brix Andersen
87e768c79d soc: arm: nxp: remove unused DT_FTM_* dts fixups
Remove the now unused DT_FTM_* dts fixups from NXP ARM SoCs.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-01-06 10:03:20 -06:00
Jose Alberto Meza
3783c83b25 soc: arm: microchip: Allow to support only light sleep
Make sure light sleep hook function is compile when needed
This solves linking error for shippable test that only enable
light sleep.

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2020-01-03 12:04:00 -08:00
Andrzej Głąbek
49bd19f3f2 soc: nrf5340: Fix busy waiting on nRF5340 application core
This patch adds a temporary workaround for the incorrect initialization
of the SystemCoreClock global variable that is done for the application
core of nRF5340 (see system_nrf5340_application.c) and that results in
k_busy_wait() producing delays of twice the requested time.
The problem is that the call to SystemCoreClockUpdate() that is done
at the end of SystemInit() correctly sets the value of SystemCoreClock
to reflect the hardware state after reset (HFCLK128M divided by 2),
but then the SystemCoreClock variable is initialized (by z_data_copy()
called from z_arm_prep_c()) to the __SYSTEM_CLOCK value that is defined
as 128000000. This in turn results in nrfx_coredep_delay_us() (used by
k_busy_wait() by default for nRF SoCs) delaying for twice the requested
number of microseconds.
The temporary workaround is to call SystemCoreClockUpdate() at a later
stage of the system initialization, in its nRF53 specific part.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2020-01-03 14:19:38 +01:00
Benjamin Valentin
cd0873015a timer: sam0_rtc_timer: Add support for SAME54
The RTC peripheral found in the SAMD5x/SAME5x MCUs is very
simmilar to the one found in existing sam0 devices with only
a few changes to register names and the clock source selection.

Signed-off-by: Benjamin Valentin <benpicco@googlemail.com>
2019-12-21 11:15:52 -05:00
Jack Rosenthal
53ed9e57a2 soc: stm32f0: Add support for STM32F098xx SOC
This adds a Kconfig options and device tree configs for the STM32F098
series of SoC.

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
2019-12-20 20:27:20 -05:00
Carlo Caione
aec9a8c4be arch: arm: Move ARM code to AArch32 sub-directory
Before introducing the code for ARM64 (AArch64) we need to relocate the
current ARM code to a new AArch32 sub-directory. For now we can assume
that no code is shared between ARM and ARM64.

There are no functional changes. The code is moved to the new location
and the file paths are fixed to reflect this change.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2019-12-20 11:40:59 -05:00
Øyvind Rønningstad
b1026da300 arm: linker.ld: Port the CC32xx flash header to zephyr_linker_sources()
Add the .dbghdr sections via its own linker script snippet.

Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
2019-12-20 08:54:53 -05:00
Øyvind Rønningstad
54c1af861c arm: linker.ld: Port NXP_IMX_RT_BOOT_HEADER to zephyr_linker_sources()
Add the .boot_hdr.* sections via its own linker script snippet.

Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
2019-12-20 08:54:53 -05:00
Øyvind Rønningstad
f5fda5cfa1 arm: linker.ld: Port KINETIS_FLASH_CONFIG to zephyr_linker_sources()
Add the .kinetis_flash_config via its own linker script snippet.

Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
2019-12-20 08:54:53 -05:00
Stephanos Ioannidis
11d0f0a294 drivers: interrupt_controller: Refactor GIC configurations
The current GIC configuration scheme is designed to support only one
specific type and version of GIC (i.e. GIC-400 that implements the
GICv2 interface).

This commit adds a set of GIC version configuration symbols that can
be selected by the SoC configuration to specify which version of GIC
interface is implemented in the SoC.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-12-19 11:05:27 -05:00
Krzysztof Chruscinski
2c429ca24f soc: arm: nordic: Remove enabling of temperature sensor
nrf51 and nrf52 by default was enabling temperature sensor if sensor
API was enabled. It was causing code size increase even when
temperature sensor was not touched by anyone. Removed default enabling
of temperature sensor for both series.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2019-12-19 16:02:55 +01:00
Filip Brozovic
e541e63653 soc: arm: stm32g0: add STM32G031 SoC series
This commit adds support for the STM32G031xx SoCs
by STMicroelectronics.

Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
2019-12-18 22:06:39 +01:00
Filip Brozovic
5756c00017 soc: arm: stm32g0: add hw flow control property for usart1 to dts fixup
This commit adds the missing USART1 HW_FLOW_CONTROL property to the
stm32g0 DTS fixup file.

Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
2019-12-18 22:06:39 +01:00
Filip Brozovic
fc2dfae64f drivers: i2c: add STM32G0X I2C support
Add I2C driver support for STM32G0X SoC series.

Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
2019-12-18 22:06:27 +01:00
Erwan Gouriou
af7e093ae6 soc: stm32f446 : update default gpio configuration
Fix GPIO default configuration for F446.
Default config for GPIO should be `y`.


Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-12-18 07:36:13 -06:00
Sahaj Sarup
d072ab83ac arm: 96b_stm32_sensor_mez: spi: Enable SPI4
This patch enables SPI4 on the 96Boards STM32 Sensors Mezzanine.
SPI4 has been broken out to a Grove Connector on the board.

Changes:

- Updated board dts to enable spi4
- Updated board Kconfig
- Updated board documentation
- Update board pinmux
- Updated stm32f4 pinmux header file
- Updated stm32f401 dtsi
- Updated stm32f4 defconfig to enable PORTE GPIO
- Added board to spi_loopback test

Test: spi_loopback test passed

Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
2019-12-18 07:34:37 -06:00
Kamil Piszczek
3a39f79d9b soc: arm: nordic: nrf53: add nfct hw in kconfig
Added the NFCT Peripheral capability to the Application Core
Kconfig of the nRF5340 SoC.

Signed-off-by: Kamil Piszczek <Kamil.Piszczek@nordicsemi.no>
2019-12-16 15:44:09 +01:00
Erwan Gouriou
3a95dda66c drivers/eeprom: stm32: Enables only for L1 series
Setting EEPROM_STM32 with `default y` under `if SOC_FAMILY_STM32`
overrides `depends on SOC_SERIES_STM32L1X` in EEPROM_STM32
definition.
Then, if ever EEPROM is set in any file (as in
tests/drivers/build_all`), EEPROM_STM32 will be indeed set,
with potential issues on series where driver is not yet correctly
handled.

Fix this by removing EEPROM_STM32 definition in STM32 generic
file and set `default y` along with the `depends on` to keep
it effective.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-12-15 10:19:25 -05:00
Marcin Szymczyk
e6b3a33318 soc: nrf: update dts_fixup.h to SPI DT
Commit 94bed60abea53818c8cd723e233799a77c4b4e4b introduced separate
DT symbols for SPI and SPIM. Update dts_fixup.h for all nRF chips
to align with those changes.

Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
2019-12-13 17:10:24 -06:00
Marcin Szymczyk
03a99e0d7f soc: nrf: update dts_fixup.h to I2C DT
Commit a8a85c21cff7319e80af16688ea6076594fab7c8 introduced separate
DT symbols for TWI and TWIM. Update dts_fixup.h for all nRF chips
to align with those changes.

Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
2019-12-13 17:10:24 -06:00
Maureen Helm
95743561a6 drivers: serial: Use generated dts macros in mcux flexcomm driver
Uses the generated device tree macros, DT_NXP_LPC_USART_USART_*, in the
mcux flexcomm driver and removes the now unused dts fixups from the
lpc54xxx and lpc55xxx socs.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-12-13 18:45:54 +01:00
Maureen Helm
72e0080e56 drivers: serial: Rename lpc usart shim driver
Renames the lpc usart shim driver to more accurately reflect the
flexcomm hardware IP and to prepare for instantiating it on an SoC
outside the LPC family.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-12-13 18:45:54 +01:00
Vladimir Atanasov
8e0e23fefc soc/kl2x: added I2C_1 labels
added I2C_1 labels for kl2x soc in dts_fixup.h

Signed-off-by: Vladimir Atanasov <vlado.atanasov@gmail.com>
2019-12-12 15:13:59 -06:00
Jose Alberto Meza
673ee9e84e soc: arm: mchp: Add missing definition for SoC pins
Add missing definition for SoC pin

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2019-12-12 11:47:50 -08:00
Kwon Tae-young
69924b19c8 drivers: eeprom: add driver support for EEPROM of STM32L1
Could not find a supported LL with EEPROM.
So I used HAL.

Tested with: 96b_wistrio

Signed-off-by: Kwon Tae-young <tykwon@m2i.co.kr>
2019-12-12 07:57:33 -06:00
Anas Nashif
3765e46a40 soc: mec1501: fix build failure
When CONFIG_SYS_POWER_DEEP_SLEEP_STATES is not set, we have an unused
function that causes a build failure.
Enclose that function in the #ifdef.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-12-11 13:09:52 -06:00
Feng Cheng
ee57c8e749 drivers: flash: Add the flash driver of the stm32f1x family
Most of the code is copied from the stm32f0x family
Tested on stm32f103ze soc

Signed-off-by: Feng Cheng <i@fengch.me>
2019-12-11 12:40:33 -06:00
Ulf Magnusson
984bfae831 global: Remove leading/trailing blank lines in files
Remove leading/trailing blank lines in .c, .h, .py, .rst, .yml, and
.yaml files.

Will avoid failures with the new CI test in
https://github.com/zephyrproject-rtos/ci-tools/pull/112, though it only
checks changed files.

Move the 'target-notes' target in boards/xtensa/odroid_go/doc/index.rst
to get rid of the trailing blank line there. It was probably misplaced.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-12-11 19:17:27 +01:00
Andrei Gansari
487dc7cb94 soc: enable secure mode for LPC55xxx
Devices that are SECURE enabled may require sometimes to enable secure
bits on CMSE register.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2019-12-10 08:48:56 -06:00
Maureen Helm
5472961ca0 boards: lpcxpresso54114: Enable spi instance 5
Enables spi instance 5 on the lpcxpresso54114 board. Configures pinmuxes
and clocks, and updates board documentation accordingly.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-12-10 08:48:56 -06:00
Maureen Helm
ea5c3b6e04 boards: lpcxpresso55s69: Enable spi instance 8
Enables the high-speed spi instance 8 on the lpcxpresso55s69 board.
Configures pinmuxes and clocks, and updates board documentation
accordingly.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-12-10 08:48:56 -06:00
Maureen Helm
3efd339e7e soc: nxp_lpc: Enable the mcux flexcomm spi driver
Enables the mcux flexcomm spi driver on lpc54xxx and lpc55xxx socs.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-12-10 08:48:56 -06:00
Kumar Gala
82e05450ca include: Fix use of <power.h> -> <power/power.h>
Fix #include <power.h> as it has been deprecated and
should be #include <power/power.h>.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-12-10 08:39:37 -05:00
Kumar Gala
cd0f8d5c4f include: Fix use of <sys_io.h> -> <sys/sys_io.h>
Fix #include <sys_io.h> as it has been deprecated and
should be #include <sys/sys_io.h>.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-12-10 08:39:37 -05:00
Kumar Gala
24ae1b1aa7 include: Fix use of <misc/FOO.h> -> <sys/FOO.h>
Fix #include <misc/FOO.h> as misc/FOO.h has been deprecated and
should be #include <sys/FOO.h>.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-12-10 08:39:37 -05:00
Vinayak Kariappa Chettimada
e18d1b6a46 arm: soc: nRF51: Remove ISR_STACK_SIZE assignment
As ISR stack size depends on application code, its best set
in the application's prj.conf file. Hence, remove it from
soc Kconfig files.

Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
2019-12-10 15:34:26 +02:00
Henrik Brix Andersen
b9b9303f1f soc: arm: nxp: add dts fixups for lpi2c bus timeouts
Add device tree fixups for the NXP LPI2C bus timeout property to the
NXP i.MX RT and Kineties KE1xF SoC series.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2019-12-09 16:01:38 -06:00
Scott Worley
60915c884f soc : mec1501 : Deep and light sleep example
Created MEC1501 deep and light sleep example for MCHP MEC1501.
Modifications were made to SoC, board, timer, and hello world
sample program. Power management split into SoC power
implementing the interface and device power for device specific
logic.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2019-12-09 11:57:03 -05:00
Ioannis Glaropoulos
16d8a492c6 soc: arm: stm32: remove custom fixed MPU region definition
We remove the custom fixed MPU region definition from ST
STM32 SoC definitions, as the common fixed MPU
region definition is now used.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-12-09 11:51:14 -05:00
Ioannis Glaropoulos
bee70b4ca8 soc: arm: arm: remove custom fixed MPU region definition
We remove the custom fixed MPU region definition from ARM
- Beetle
- Musca_a
- Musca_b1
- MPS2 (an385 and an521)
SoC definitions, as the common fixed MPU region definition
is now used.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-12-09 11:51:14 -05:00
Ioannis Glaropoulos
c9da964752 soc: arm: silabs: remove custom fixed MPU region definition
We remove the custom fixed MPU region definition from Silicon
Labs exx32 SoC definitions, as the common fixed MPU region
definition is now used.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-12-09 11:51:14 -05:00
Ioannis Glaropoulos
12eb1e4038 soc: arm: nxp kinetis: force custom fixed MPU region configuration
For the NXP Kinetis SoCs with the NXP MPU regions, we keep
the confiruation of the fixed SoC MPU regions at each SoC
definition.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-12-09 11:51:14 -05:00
Ioannis Glaropoulos
9ce4d8f20d soc: arm: nxp: remove custom fixed MPU region definition
We remove the custom fixed MPU region definition from NXP IMX
RT, Kinetis, and LPC SoC definitions, as the common fixed MPU
region definition is now used.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-12-09 11:51:14 -05:00
Ioannis Glaropoulos
ac35acd5aa soc: arm: atmel: remove custom fixed MPU region definition
We remove the custom fixed MPU region definition from Atmel
SAM SoC definition, as the common fixed MPU region definition
is now used.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-12-09 11:51:14 -05:00
Ioannis Glaropoulos
95e8cd0041 soc: arm: nordic_nrf: remove custom fixed MPU region definition
We remove the custom fixed MPU region definition from Nordic
nRF SoC definition, as the common fixed MPU region definition
is now used.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-12-09 11:51:14 -05:00
Ioannis Glaropoulos
cede12b159 soc: arm: framework for common fixed MPU region configuration
We move the configuration of the fixed MPU regions for ARM
Cortex-M SoCs in a common place under soc/arm/common/cortex-m,
instead of having this configuration present in each ARM SoC or
SoC Series definition. The rationale behind this is that for all
SoCs the fixed MPU regions configured at SoC definition are only
used for enforcing default Flash and SRAM access policies, and
currently, this is common to all ARM SoCs with MPU support.

We also simplify the Flash and SRAM MPU region definition,
aiming at using a single MPU region index to program each
of them.

We still support the possibility for ARM SoCs to opt-out and,
instead, define their own custom fixed MPU regions at SoC
definition. We do it using a Kconfig option, introduced
explicitly for this purpose.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-12-09 11:51:14 -05:00
Ulf Magnusson
87e917a925 kconfig: Remove redundant 'default n' and 'prompt' properties
Bool symbols implicitly default to 'n'.

A 'default n' can make sense e.g. in a Kconfig.defconfig file, if you
want to override a 'default y' on the base definition of the symbol. It
isn't used like that on any of these symbols though.

Also replace some

    config
    	prompt "foo"
    	bool/int

with the more common shorthand

    config
    	bool/int "foo"

See the 'Style recommendations and shorthands' section in
https://docs.zephyrproject.org/latest/guides/kconfig/index.html.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-12-09 16:14:50 +01:00
Stephanos Ioannidis
b9b474cc82 soc: same70: Fix incorrect default config value
The type of SOC_ATMEL_SAME70_DISABLE_ERASE_PIN is bool, yet its default
is specified as an int value of 0.

This commit removes the implied `default 0`, which is equivalent to
`default n`.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-12-09 15:50:13 +01:00
Francisco Munoz
11c7e5a157 soc: microchip_mec: Add header for extracting eSPI data
This header contains encoding offsets for all the eSPI channels which
communicate data from/to the host.

Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
2019-11-20 15:02:08 -05:00
Francisco Munoz
6b3ece2f1d soc: arm: mec1501: Update espi kconfig variable
Leave kconfig ESPI_XEC variable in terms of ESPI

Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
2019-11-20 15:02:08 -05:00
Ulf Magnusson
d0a6f682d1 kconfig: Fix up newly-introduced copy-pasted headers
Same deal as in https://github.com/zephyrproject-rtos/zephyr/pull/20280,
for newly-introduced stuff.

Will avoid failures with the new CI test in
https://github.com/zephyrproject-rtos/ci-tools/pull/112, though it only
checks changed files.

Also fix some un-indented properties on choices. Choice properties work
the same as symbol properties syntactically.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-11-19 15:25:08 -05:00
Piotr Mienkowski
8f0aa32ad5 soc: gecko: Enable SWO output during SoC initialization
Enable SWO debug output during system initialization and not as part of
GPIO driver initialization. After the modification the logger output
becomes available earlier during the boot process. Also, it's not
necessary anymore to build full GPIO driver only to enable SWO. This may
be critical when building small images.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2019-11-19 13:56:06 -05:00
Ioannis Glaropoulos
3c4fb60399 boards: arm: nrf5340_dk: fix nRF Cache and NVMC macro usage
We need to fix the formato of the macros for nRF CACHE and NVMC
peripherals in soc.c, so the _S and _NS suffixes are skipped.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-11-14 12:18:44 +01:00
Vinayak Kariappa Chettimada
29a1bbd24a boards: arm: nrf5340_dk: Enable DC/DC by default
Since the nRF5340 DK contains the required DC/DC circuitry,
enable it by default while keeping it configurable. This
reduces power consumption in application core , network
core and high voltage use.

Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
2019-11-14 12:18:44 +01:00
Christian Taedcke
6486c429f1 dts: silabs: Define all available gpio ports for efr32mg12p
Add device tree elements for all gpio ports of the efr32mg12p including
the dts fixup entries.
Also remove gpio port e since this is not available in efr32mg12p socs.

Signed-off-by: Christian Taedcke <hacking@taedcke.com>
2019-11-13 12:05:48 -06:00
Andrei Gansari
38e8bd8444 soc: define gpio pull-down for LPC54114
Add define that maps to IOCON register PULL-DOWN bit.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2019-11-13 12:05:48 -06:00
Andrei Gansari
20700f912e soc: LPC55xxx clock comment fix
SoC initialization had an incorrect comment regarding system clock.
Corrected from 48Mhz -> 96Mhz.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2019-11-13 12:05:48 -06:00
Andrei Gansari
de514bc98a soc: enable PINT device at LPC SoC boot
PINT device is enabled when SoC is booting up. Applies to LPC54xxx and
LPC55xxx families.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2019-11-13 12:05:48 -06:00
Emil Obalski
3747fd0a68 soc: nordic: Add support for nRF52833
This commit adds basic support for nRF52833 SoC.
Changes affect introducing:
 - architecuture files (dtsi)
 - configuration of nrfx drivers
 - adaptation of inclusions based on chosen SoC
 - configuration of NFCT_PINS_AS_GPIOS depends on HAS_HW_NRF_NFCT.

Signed-off-by: Emil Obalski <emil.obalski@nordicsemi.no>
2019-11-13 10:33:38 -06:00
Francois Ramu
91884302bf soc: arm: st_stm32: add driver lptimer management to stm32wb series
This patch introduces the support of the Low Power Timer
     for the STM32WBxx from STMicroelectronics.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2019-11-13 10:31:06 -06:00
Alexander Wachter
c180e059bf soc: stm32f103Xb: Enable CAN support for this SoC
This commit enables CAN on the STM32F103Xb SoC series.

Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
2019-11-13 10:30:19 -06:00
Gaute Gamnes
efa28c9de9 soc: arm: nrf53: add nRF5340 CPUNET SoC definition
Nordic nRF5340 Network (CPU NET) SoC definition.

Signed-off-by: Gaute Gamnes <gaute.gamnes@nordicsemi.no>
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-11-08 19:26:35 +01:00
Ioannis Glaropoulos
397d1938de soc: arm: nrf53: add nRF5340 CPUAPP SoC definition
Nordic nRF5340 CPUAPP (Application MCU) SoC definition
(Secure and Non-Secure domains).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-11-08 19:26:35 +01:00
Christian Taedcke
b25569ef74 soc: silabs_exx32: Enable mpu on efr32mg soc
Enables the arm v7m mpu on the efr32mg soc and the board
efr32mg_sltb004a.

Tested on hardware with samples/mpu/mpu_test and
tests/kernel/mem_protect

Signed-off-by: Christian Taedcke <hacking@taedcke.com>
2019-11-08 10:38:18 -06:00
Francois Ramu
d0c9234d70 soc: arm: st_stm32: add driver lptimer management to stm32l4 series
This patch introduces the support of the Low Power Timer
     for the STM32L4xx from STMicroelectronics.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2019-11-08 10:04:21 -06:00
Francois Ramu
0ae7023405 driver: timer: st_stm32: add lptimer management to stm32xx series
This patch introduces the support of the LowPower Timer
 for the STM32xx from STMicroelectronics.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2019-11-08 10:04:21 -06:00
Andrzej Głąbek
2115099932 nordic: Update nrfx HAL function calls after switching to nrfx 2.0.0
Calls to nrfx HAL functions in various nRF platform related source
files are complemented with pointers to relevant peripherals.

Additionally, TIMER HAL functions that got renamed in nrfx 2.0.0 are
updated in the qemu_cortex_m0 board supporting code.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2019-11-08 14:54:12 +01:00
Andrzej Głąbek
b814f8ab4b soc: nordic_nrf: Update validation of base adresses with new entries
Add checks for:
- NRF_RNG
- NRF_IPC
- NRF_WDT0
- NRF_WDT1

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2019-11-08 14:54:12 +01:00
Andrzej Głąbek
cf92c31e02 modules: hal_nordic: Update nrfx to version 2.0.0
Update the hal_nordic module revision to switch to nrfx 2.0.0.
Add Kconfig options that enable to use the newly introduced nrfx
drivers in Zephyr.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2019-11-08 14:54:12 +01:00
Andrew Boie
4f77c2ad53 kernel: rename z_arch_ to arch_
Promote the private z_arch_* namespace, which specifies
the interface between the core kernel and the
architecture code, to a new top-level namespace named
arch_*.

This allows our documentation generation to create
online documentation for this set of interfaces,
and this set of interfaces is worth treating in a
more formal way anyway.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-11-07 15:21:46 -08:00
Maureen Helm
261a1bfa70 soc: nxp_imx: Remove CLOCK_CONTROL_IMX_CCM config
There is no imx ccm shim driver in drivers/clock_control. This config
was only used to conditionally compile nxp hal drivers, even though the
imx6/7 soc init always needs them.

Updates the nxp hal to unconditionally compile the ccm drivers and
removes the unnecessary config symbol.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-11-07 15:55:49 -06:00
Vincent Wan
1b263ba0a6 dts: specify cpu frequency for TI CC13X2/CC26X2
Add cpu clock frequency information to DTS so that it can be retrieved
in the code.

Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
2019-11-07 15:55:21 -06:00
Benjamin Valentin
7e722564df soc: atmel_sam0: Add SAME53
This adds supoprt for the Atmel SAME53 SoC.

The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals
with the sam0 Cortex-M0+ and saml1x Cortex-M23 parts.

Signed-off-by: Benjamin Valentin <benpicco@googlemail.com>
2019-11-06 21:18:00 -06:00
Benjamin Valentin
de6bc41430 soc: atmel_sam0: Add SAME51
This adds supoprt for the Atmel SAME51 SoC.

The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals
with the sam0 Cortex-M0+ and saml1x Cortex-M23 parts.

Signed-off-by: Benjamin Valentin <benpicco@googlemail.com>
2019-11-06 21:18:00 -06:00