michaelh/zephyr
1
0
Fork 0
Code Releases Activity

arch: arm64: Add support for qemu_cortex_a53 board

Browse source 
This patch introduces support for the qemu_cortex_a53 board emulated
using QEMU (virt platform) adding SoC, board and DTS files.

| ./scripts/sanitycheck -p qemu_cortex_a53
|
| Total complete:  190/ 190  100%  skipped:   40, failed:    0
| 150 of 150 tests passed (100.00%), 0 failed,
|     40 skipped with 0 warnings in 580.93 seconds

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit is contained in:
Carlo Caione 2019-11-10 17:43:26 +00:00 • committed by Anas Nashif
commit a61290e1a3
18 changed files with 393 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

4
CODEOWNERS
View file

@ -31,6 +31,7 @@
/soc/arm/bcm*/ @sbranden
/soc/arm/nxp*/ @MaureenHelm
/soc/arm/nordic_nrf/ @ioannisg
/soc/arm/qemu_cortex_a53/ @carlocaione
/soc/arm/st_stm32/ @erwango
/soc/arm/st_stm32/stm32f4/ @rsalveti @idlethread
/soc/arm/st_stm32/stm32mp1/ @arnopo
@ -77,6 +78,7 @@
/boards/arm/nrf*/ @carlescufi @lemrey @ioannisg
/boards/arm/nucleo*/ @erwango
/boards/arm/nucleo_f401re/ @rsalveti @idlethread
/boards/arm/qemu_cortex_a53/ @carlocaione
/boards/arm/qemu_cortex_m*/ @ioannisg
/boards/arm/sam4s_xplained/ @fallrisk
/boards/arm/v2m_beetle/ @fvincenzo
@ -210,6 +212,7 @@
/dts/arm/atmel/samr21.dtsi @benpicco
/dts/arm/atmel/sam*5*.dtsi @benpicco
/dts/arm/broadcom/ @sbranden
/dts/arm/qemu-virt/ @carlocaione
/dts/arm/st/ @erwango
/dts/arm/ti/cc13?2* @bwitherspoon
/dts/arm/ti/cc26?2* @bwitherspoon
@ -226,6 +229,7 @@
/dts/riscv/riscv32-fe310.dtsi @nategraff-sifive
/dts/riscv/riscv32-litex-vexriscv.dtsi @mateusz-holenko @kgugala @pgielda
/dts/arm/armv7-r.dtsi @bbolen
/dts/arm/armv8-a.dtsi @carlocaione
/dts/arm/xilinx/ @bbolen
/dts/xtensa/xtensa.dtsi @ydamigos
/dts/bindings/ @galak

8
boards/arm/qemu_cortex_a53/Kconfig.board Normal file
View file

@ -0,0 +1,8 @@
# Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
# SPDX-License-Identifier: Apache-2.0
config BOARD_QEMU_CORTEX_A53
bool "Cortex-A53 Emulation (QEMU)"
depends on SOC_QEMU_CORTEX_A53
select ARM64
select QEMU_TARGET

12
boards/arm/qemu_cortex_a53/Kconfig.defconfig Normal file
View file

@ -0,0 +1,12 @@
# Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
# SPDX-License-Identifier: Apache-2.0
if BOARD_QEMU_CORTEX_A53
config BUILD_OUTPUT_BIN
default n
config BOARD
default "qemu_cortex_a53"
endif # BOARD_QEMU_CORTEX_A53

14
boards/arm/qemu_cortex_a53/board.cmake Normal file
View file

@ -0,0 +1,14 @@
# Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
# SPDX-License-Identifier: Apache-2.0
set(EMU_PLATFORM qemu)
set(QEMU_ARCH aarch64)
set(QEMU_CPU_TYPE_${ARCH} cortex-a53)
set(QEMU_FLAGS_${ARCH}
-cpu ${QEMU_CPU_TYPE_${ARCH}}
-nographic
-machine virt
)
board_set_debugger_ifnset(qemu)

110
boards/arm/qemu_cortex_a53/doc/index.rst Normal file
View file

@ -0,0 +1,110 @@
.. _qemu_cortex_a53:
ARM Cortex-A53 Emulation (QEMU)
###############################
Overview
********
This board configuration will use QEMU to emulate a generic Cortex-A53 hardware
platform.
.. figure:: qemu_cortex_a53.png
:width: 600px
:align: center
:alt: Qemu
Qemu (Credit: qemu.org)
This configuration provides support for an ARM Cortex-A53 CPU and these
devices:
* GIC-400 interrupt controller
* ARM architected timer
* PL011 UART controller
Hardware
********
Supported Features
==================
The following hardware features are supported:
+--------------+------------+----------------------+
| Interface | Controller | Driver/Component |
+==============+============+======================+
| GIC | on-chip | interrupt controller |
+--------------+------------+----------------------+
| PL011 UART | on-chip | serial port |
+--------------+------------+----------------------+
| ARM TIMER | on-chip | system clock |
+--------------+------------+----------------------+
The kernel currently does not support other hardware features on this platform.
Devices
========
System Clock
------------
This board configuration uses a system clock frequency of 62.5 MHz.
Serial Port
-----------
This board configuration uses a single serial communication channel with the
CPU's UART0.
Known Problems or Limitations
==============================
The following platform features are unsupported:
* Writing to the hardware's flash memory
Programming and Debugging
*************************
Use this configuration to run basic Zephyr applications and kernel tests in the QEMU
emulated environment, for example, with the :ref:`synchronization_sample`:
.. zephyr-app-commands::
:zephyr-app: samples/synchronization
:host-os: unix
:board: qemu_cortex_a53
:goals: run
This will build an image with the synchronization sample app, boot it using
QEMU, and display the following console output:
.. code-block:: console
***** Booting Zephyr OS build zephyr-v2.0.0-1657-g99d310da48e5 *****
threadA: Hello World from qemu_cortex_a53!
threadB: Hello World from qemu_cortex_a53!
threadA: Hello World from qemu_cortex_a53!
threadB: Hello World from qemu_cortex_a53!
threadA: Hello World from qemu_cortex_a53!
threadB: Hello World from qemu_cortex_a53!
threadA: Hello World from qemu_cortex_a53!
threadB: Hello World from qemu_cortex_a53!
Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`.
Debugging
=========
Refer to the detailed overview about :ref:`application_debugging`.
Networking
==========
References
**********
1. (ID050815) ARM® Cortex®-A Series - Programmer’s Guide for ARMv8-A
2. (ID070919) Arm® Architecture Reference Manual - Armv8, for Armv8-A architecture profile
3. (ARM DAI 0527A) Application Note Bare-metal Boot Code for ARMv8-A Processors
4. AArch64 Exception and Interrupt Handling
5. Fundamentals of ARMv8-A

BIN
boards/arm/qemu_cortex_a53/doc/qemu_cortex_a53.png Normal file
View file

Binary file not shown.
Side by side

After

Width:  |  Height:  |  Size: 10 KiB

26
boards/arm/qemu_cortex_a53/qemu_cortex_a53.dts Normal file
View file

@ -0,0 +1,26 @@
/*
* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*
*/
/dts-v1/;
#include <arm/qemu-virt/qemu-virt-a53.dtsi>
/ {
model = "QEMU Cortex-A53";
compatible = "qemu,arm-cortex-a53";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,flash = &flash0;
};
};
&uart0 {
status = "okay";
current-speed = <115200>;
clock-frequency = <24000000>;
};

19
boards/arm/qemu_cortex_a53/qemu_cortex_a53.yaml Normal file
View file

@ -0,0 +1,19 @@
identifier: qemu_cortex_a53
name: QEMU Emulation for Cortex-A53
type: qemu
simulation: qemu
arch: arm
toolchain:
- cross-compile
ram: 128
testing:
ignore_tags:
- cmsis_rtos
- console
- drivers
- interrupt
- logging
- net
- nfc
- shell
- tracing

20
boards/arm/qemu_cortex_a53/qemu_cortex_a53_defconfig Normal file
View file

@ -0,0 +1,20 @@
CONFIG_ARM=y
CONFIG_SOC_QEMU_CORTEX_A53=y
CONFIG_BOARD_QEMU_CORTEX_A53=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_XIP=n
# QEMU settings
CONFIG_SRAM_BASE_ADDRESS=0x40000000
CONFIG_SRAM_SIZE=131072
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable serial port
CONFIG_UART_PL011=y
CONFIG_UART_PL011_PORT0=y

16
dts/arm/armv8-a.dtsi Normal file
View file

@ -0,0 +1,16 @@
/*
* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "skeleton.dtsi"
/ {
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
};
};

72
dts/arm/qemu-virt/qemu-virt-a53.dtsi Normal file
View file

@ -0,0 +1,72 @@
/*
* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Derived from DTS extracted with:
*
* qemu-system-aarch64 -machine virt -cpu cortex-a53 -nographic
* -machine dumpdtb=virt.dtb
*
* dtc -I dtb -O dts virt.dtb
*/
#include <mem.h>
#include <arm/armv8-a.dtsi>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0>;
};
};
soc {
interrupt-parent = <&gic>;
gic: interrupt-controller@8000000 {
compatible = "arm,gic";
reg = <0x8000000 0x10000>,
<0x8010000 0x10000>;
interrupt-controller;
#interrupt-cells = <4>;
label = "GIC";
status = "okay";
};
uart0: uart@9000000 {
compatible = "arm,pl011";
reg = <0x9000000 0x1000>;
status = "disabled";
interrupts = <GIC_SPI 1 0 IRQ_TYPE_LEVEL>;
interrupt-names = "irq_0";
label = "UART_0";
};
flash0: flash@0 {
compatible = "soc-nv-flash";
reg = <0x0 DT_SIZE_K(64)>;
};
arch_timer: timer {
compatible = "arm,arm-timer";
interrupts = <GIC_PPI 13 IRQ_DEFAULT_PRIORITY
IRQ_TYPE_EDGE>,
<GIC_PPI 14 IRQ_DEFAULT_PRIORITY
IRQ_TYPE_EDGE>,
<GIC_PPI 11 IRQ_DEFAULT_PRIORITY
IRQ_TYPE_EDGE>,
<GIC_PPI 10 IRQ_DEFAULT_PRIORITY
IRQ_TYPE_EDGE>;
label = "arch_timer";
};
};
};

9
dts/bindings/cpu/arm,cortex-a53.yaml Normal file
View file

@ -0,0 +1,9 @@
# Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
# SPDX-License-Identifier: Apache-2.0
description: >
This is a representation of ARM Cortex-A53 CPU.
compatible: "arm,cortex-a53"
include: cpu.yaml

2
soc/arm/qemu_cortex_a53/CMakeLists.txt Normal file
View file

@ -0,0 +1,2 @@
# Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
# SPDX-License-Identifier: Apache-2.0

35
soc/arm/qemu_cortex_a53/Kconfig.defconfig Normal file
View file

@ -0,0 +1,35 @@
# Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
# SPDX-License-Identifier: Apache-2.0
if SOC_QEMU_CORTEX_A53
config SOC
default "qemu_cortex_a53"
config NUM_IRQS
# must be >= the highest interrupt number used
# - include the UART interrupts
default 220
config 2ND_LVL_ISR_TBL_OFFSET
default 1
config MAX_IRQ_PER_AGGREGATOR
default 219
config NUM_2ND_LEVEL_AGGREGATORS
default 1
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 62500000
# Workaround for not being able to have commas in macro arguments
DT_CHOSEN_Z_FLASH := zephyr,flash
config FLASH_SIZE
default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
config FLASH_BASE_ADDRESS
default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
endif # SOC_QEMU_CORTEX_A53

9
soc/arm/qemu_cortex_a53/Kconfig.soc Normal file
View file

@ -0,0 +1,9 @@
# Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_QEMU_CORTEX_A53
bool "QEMU virt platform (cortex-a53)"
select CPU_CORTEX_A53
select GIC_V2
select MULTI_LEVEL_INTERRUPTS
select 2ND_LEVEL_INTERRUPTS

10
soc/arm/qemu_cortex_a53/dts_fixup.h Normal file
View file

@ -0,0 +1,10 @@
/*
* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_PL011_PORT0_BASE_ADDRESS DT_ARM_PL011_9000000_BASE_ADDRESS
#define DT_PL011_PORT0_NAME DT_ARM_PL011_9000000_LABEL
#define DT_PL011_PORT0_CLOCK_FREQUENCY DT_ARM_PL011_9000000_CLOCK_FREQUENCY
#define DT_PL011_PORT0_BAUD_RATE DT_ARM_PL011_9000000_CURRENT_SPEED

8
soc/arm/qemu_cortex_a53/linker.ld Normal file
View file

@ -0,0 +1,8 @@
/*
* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*
*/
#include <arch/arm/aarch64/scripts/linker.ld>

19
soc/arm/qemu_cortex_a53/soc.h Normal file
View file

@ -0,0 +1,19 @@
/*
* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*
*/
#ifndef _SOC_H_
#define _SOC_H_
#include <sys/util.h>
#ifndef _ASMLANGUAGE
#include <device.h>
#endif /* !_ASMLANGUAGE */
#endif /* _SOC_H_ */