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drivers: flash: stm32: Update flash driver implementation

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Remove soc/arm/st_stm32/stm32YY/flash_registers.h files.
Change register accesses in stm32 flash drivers to use FLASH_TypeDef
from modules/hal/stm32/stm32cube/stm32YYxx/soc/stm32xxxxxx.h.

Fixes #16235

Signed-off-by: Sarvesh Patkar <psarvesh314@gmail.com>
This commit is contained in:
Sarvesh Patkar 2019-11-16 14:34:13 -08:00 • committed by Maureen Helm
commit 4f2c107389
20 changed files with 156 additions and 714 deletions
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95
drivers/flash/flash_stm32.c
View file

@ -112,7 +112,7 @@ static int flash_stm32_check_status(struct device *dev)
#endif
FLASH_FLAG_WRPERR;
if (FLASH_STM32_REGS(dev)->sr & error) {
if (FLASH_STM32_REGS(dev)->SR & error) {
return -EIO;
}
@ -129,8 +129,11 @@ int flash_stm32_wait_flash_idle(struct device *dev)
if (rc < 0) {
return -EIO;
}
while ((FLASH_STM32_REGS(dev)->sr & FLASH_SR_BSY)) {
#if defined(CONFIG_SOC_SERIES_STM32G0X)
while ((FLASH_STM32_REGS(dev)->SR & FLASH_SR_BSY1)) {
#else
while ((FLASH_STM32_REGS(dev)->SR & FLASH_SR_BSY)) {
#endif
if (k_uptime_get() > timeout_time) {
return -EIO;
}
@ -153,20 +156,14 @@ static void flash_stm32_flush_caches(struct device *dev,
defined(CONFIG_SOC_SERIES_STM32G4X)
ARG_UNUSED(offset);
ARG_UNUSED(len);
#if defined(CONFIG_SOC_SERIES_STM32F4X)
struct stm32f4x_flash *regs = FLASH_STM32_REGS(dev);
#elif defined(CONFIG_SOC_SERIES_STM32L4X)
struct stm32l4x_flash *regs = FLASH_STM32_REGS(dev);
#elif defined(CONFIG_SOC_SERIES_STM32WBX)
struct stm32wbx_flash *regs = FLASH_STM32_REGS(dev);
#elif defined(CONFIG_SOC_SERIES_STM32G4X)
struct stm32g4x_flash *regs = FLASH_STM32_REGS(dev);
#endif
if (regs->acr.val & FLASH_ACR_DCEN) {
regs->acr.val &= ~FLASH_ACR_DCEN;
regs->acr.val |= FLASH_ACR_DCRST;
regs->acr.val &= ~FLASH_ACR_DCRST;
regs->acr.val |= FLASH_ACR_DCEN;
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
if (regs->ACR & FLASH_ACR_DCEN) {
regs->ACR &= ~FLASH_ACR_DCEN;
regs->ACR |= FLASH_ACR_DCRST;
regs->ACR &= ~FLASH_ACR_DCRST;
regs->ACR |= FLASH_ACR_DCEN;
}
#elif defined(CONFIG_SOC_SERIES_STM32F7X)
SCB_InvalidateDCache_by_Addr((uint32_t *)(CONFIG_FLASH_BASE_ADDRESS
@ -237,25 +234,8 @@ static int flash_stm32_write(struct device *dev, off_t offset,
static int flash_stm32_write_protection(struct device *dev, bool enable)
{
#if defined(CONFIG_SOC_SERIES_STM32F4X)
struct stm32f4x_flash *regs = FLASH_STM32_REGS(dev);
#elif defined(CONFIG_SOC_SERIES_STM32F1X)
struct stm32f1x_flash *regs = FLASH_STM32_REGS(dev);
#elif defined(CONFIG_SOC_SERIES_STM32F7X)
struct stm32f7x_flash *regs = FLASH_STM32_REGS(dev);
#elif defined(CONFIG_SOC_SERIES_STM32F0X)
struct stm32f0x_flash *regs = FLASH_STM32_REGS(dev);
#elif defined(CONFIG_SOC_SERIES_STM32F3X)
struct stm32f3x_flash *regs = FLASH_STM32_REGS(dev);
#elif defined(CONFIG_SOC_SERIES_STM32L4X)
struct stm32l4x_flash *regs = FLASH_STM32_REGS(dev);
#elif defined(CONFIG_SOC_SERIES_STM32WBX)
struct stm32wbx_flash *regs = FLASH_STM32_REGS(dev);
#elif defined(CONFIG_SOC_SERIES_STM32G0X)
struct stm32g0x_flash *regs = FLASH_STM32_REGS(dev);
#elif defined(CONFIG_SOC_SERIES_STM32G4X)
struct stm32g4x_flash *regs = FLASH_STM32_REGS(dev);
#endif
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
int rc = 0;
flash_stm32_sem_take(dev);
@ -266,11 +246,11 @@ static int flash_stm32_write_protection(struct device *dev, bool enable)
flash_stm32_sem_give(dev);
return rc;
}
regs->cr |= FLASH_CR_LOCK;
regs->CR |= FLASH_CR_LOCK;
} else {
if (regs->cr & FLASH_CR_LOCK) {
regs->keyr = FLASH_KEY1;
regs->keyr = FLASH_KEY2;
if (regs->CR & FLASH_CR_LOCK) {
regs->KEYR = FLASH_KEY1;
regs->KEYR = FLASH_KEY2;
}
}
@ -280,34 +260,13 @@ static int flash_stm32_write_protection(struct device *dev, bool enable)
}
static struct flash_stm32_priv flash_data = {
#if defined(CONFIG_SOC_SERIES_STM32F0X)
.regs = (struct stm32f0x_flash *) DT_FLASH_DEV_BASE_ADDRESS,
.pclken = { .bus = STM32_CLOCK_BUS_AHB1,
.enr = LL_AHB1_GRP1_PERIPH_FLASH },
#elif defined(CONFIG_SOC_SERIES_STM32F1X)
.regs = (struct stm32f1x_flash *) DT_FLASH_DEV_BASE_ADDRESS,
.pclken = { .bus = STM32_CLOCK_BUS_AHB1,
.enr = LL_AHB1_GRP1_PERIPH_FLASH },
#elif defined(CONFIG_SOC_SERIES_STM32F3X)
.regs = (struct stm32f3x_flash *) DT_FLASH_DEV_BASE_ADDRESS,
.pclken = { .bus = STM32_CLOCK_BUS_AHB1,
.enr = LL_AHB1_GRP1_PERIPH_FLASH },
#elif defined(CONFIG_SOC_SERIES_STM32F4X)
.regs = (struct stm32f4x_flash *) DT_FLASH_DEV_BASE_ADDRESS,
#elif defined(CONFIG_SOC_SERIES_STM32F7X)
.regs = (struct stm32f7x_flash *) DT_FLASH_DEV_BASE_ADDRESS,
#elif defined(CONFIG_SOC_SERIES_STM32L4X)
.regs = (struct stm32l4x_flash *) DT_FLASH_DEV_BASE_ADDRESS,
.pclken = { .bus = STM32_CLOCK_BUS_AHB1,
.enr = LL_AHB1_GRP1_PERIPH_FLASH },
#elif defined(CONFIG_SOC_SERIES_STM32WBX)
.regs = (struct stm32wbx_flash *) DT_FLASH_DEV_BASE_ADDRESS,
#elif defined(CONFIG_SOC_SERIES_STM32G0X)
.regs = (struct stm32g0x_flash *) DT_FLASH_DEV_BASE_ADDRESS,
.pclken = { .bus = STM32_CLOCK_BUS_AHB1,
.enr = LL_AHB1_GRP1_PERIPH_FLASH },
#elif defined(CONFIG_SOC_SERIES_STM32G4X)
.regs = (struct stm32g4x_flash *) DT_FLASH_DEV_BASE_ADDRESS,
.regs = (FLASH_TypeDef *) DT_FLASH_DEV_BASE_ADDRESS,
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32F0X) || \
defined(CONFIG_SOC_SERIES_STM32F1X) || \
defined(CONFIG_SOC_SERIES_STM32F3X) || \
defined(CONFIG_SOC_SERIES_STM32G0X) || \
defined(CONFIG_SOC_SERIES_STM32G4X)
.pclken = { .bus = STM32_CLOCK_BUS_AHB1,
.enr = LL_AHB1_GRP1_PERIPH_FLASH },
#endif

36
drivers/flash/flash_stm32.h
View file

@ -8,8 +8,6 @@
#ifndef ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_
#define ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_
#include <flash_registers.h>
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32F0X) || \
defined(CONFIG_SOC_SERIES_STM32F1X) || \
@ -21,33 +19,13 @@
#endif
struct flash_stm32_priv {
#if defined(CONFIG_SOC_SERIES_STM32F0X)
struct stm32f0x_flash *regs;
/* clock subsystem driving this peripheral */
struct stm32_pclken pclken;
#elif defined(CONFIG_SOC_SERIES_STM32F1X)
struct stm32f1x_flash *regs;
struct stm32_pclken pclken;
#elif defined(CONFIG_SOC_SERIES_STM32F3X)
struct stm32f3x_flash *regs;
/* clock subsystem driving this peripheral */
struct stm32_pclken pclken;
#elif defined(CONFIG_SOC_SERIES_STM32F4X)
struct stm32f4x_flash *regs;
#elif defined(CONFIG_SOC_SERIES_STM32F7X)
struct stm32f7x_flash *regs;
#elif defined(CONFIG_SOC_SERIES_STM32L4X)
struct stm32l4x_flash *regs;
/* clock subsystem driving this peripheral */
struct stm32_pclken pclken;
#elif defined(CONFIG_SOC_SERIES_STM32WBX)
struct stm32wbx_flash *regs;
#elif defined(CONFIG_SOC_SERIES_STM32G0X)
struct stm32g0x_flash *regs;
/* clock subsystem driving this peripheral */
struct stm32_pclken pclken;
#elif defined(CONFIG_SOC_SERIES_STM32G4X)
struct stm32g4x_flash *regs;
FLASH_TypeDef *regs;
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32F0X) || \
defined(CONFIG_SOC_SERIES_STM32F1X) || \
defined(CONFIG_SOC_SERIES_STM32F3X) || \
defined(CONFIG_SOC_SERIES_STM32G0X) || \
defined(CONFIG_SOC_SERIES_STM32G4X)
/* clock subsystem driving this peripheral */
struct stm32_pclken pclken;
#endif

24
drivers/flash/flash_stm32f0x.c
View file

@ -36,12 +36,12 @@ static unsigned int get_page(off_t offset)
static int write_hword(struct device *dev, off_t offset, u16_t val)
{
volatile u16_t *flash = (u16_t *)(offset + CONFIG_FLASH_BASE_ADDRESS);
struct stm32f0x_flash *regs = FLASH_STM32_REGS(dev);
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
u32_t tmp;
int rc;
/* if the control register is locked, do not fail silently */
if (regs->cr & FLASH_CR_LOCK) {
if (regs->CR & FLASH_CR_LOCK) {
return -EIO;
}
@ -57,10 +57,10 @@ static int write_hword(struct device *dev, off_t offset, u16_t val)
}
/* Set the PG bit */
regs->cr |= FLASH_CR_PG;
regs->CR |= FLASH_CR_PG;
/* Flush the register write */
tmp = regs->cr;
tmp = regs->CR;
/* Perform the data write operation at the desired memory address */
*flash = val;
@ -69,20 +69,20 @@ static int write_hword(struct device *dev, off_t offset, u16_t val)
rc = flash_stm32_wait_flash_idle(dev);
/* Clear the PG bit */
regs->cr &= (~FLASH_CR_PG);
regs->CR &= (~FLASH_CR_PG);
return rc;
}
static int erase_page(struct device *dev, unsigned int page)
{
struct stm32f0x_flash *regs = FLASH_STM32_REGS(dev);
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
u32_t page_address = CONFIG_FLASH_BASE_ADDRESS;
u32_t tmp;
int rc;
/* if the control register is locked, do not fail silently */
if (regs->cr & FLASH_CR_LOCK) {
if (regs->CR & FLASH_CR_LOCK) {
return -EIO;
}
@ -96,19 +96,19 @@ static int erase_page(struct device *dev, unsigned int page)
page_address += page * FLASH_PAGE_SIZE;
/* Set the PER bit and select the page you wish to erase */
regs->cr |= FLASH_CR_PER;
regs->ar = page_address;
regs->CR |= FLASH_CR_PER;
regs->AR = page_address;
/* Set the STRT bit */
regs->cr |= FLASH_CR_STRT;
regs->CR |= FLASH_CR_STRT;
/* flush the register write */
tmp = regs->cr;
tmp = regs->CR;
/* Wait for the BSY bit */
rc = flash_stm32_wait_flash_idle(dev);
regs->cr &= ~FLASH_CR_PER;
regs->CR &= ~FLASH_CR_PER;
return rc;
}

24
drivers/flash/flash_stm32f1x.c
View file

@ -37,12 +37,12 @@ static unsigned int get_page(off_t offset)
static int write_hword(struct device *dev, off_t offset, u16_t val)
{
volatile u16_t *flash = (u16_t *)(offset + CONFIG_FLASH_BASE_ADDRESS);
struct stm32f1x_flash *regs = FLASH_STM32_REGS(dev);
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
u32_t tmp;
int rc;
/* if the control register is locked, do not fail silently */
if (regs->cr & FLASH_CR_LOCK) {
if (regs->CR & FLASH_CR_LOCK) {
return -EIO;
}
@ -58,10 +58,10 @@ static int write_hword(struct device *dev, off_t offset, u16_t val)
}
/* Set the PG bit */
regs->cr |= FLASH_CR_PG;
regs->CR |= FLASH_CR_PG;
/* Flush the register write */
tmp = regs->cr;
tmp = regs->CR;
/* Perform the data write operation at the desired memory address */
*flash = val;
@ -70,20 +70,20 @@ static int write_hword(struct device *dev, off_t offset, u16_t val)
rc = flash_stm32_wait_flash_idle(dev);
/* Clear the PG bit */
regs->cr &= (~FLASH_CR_PG);
regs->CR &= (~FLASH_CR_PG);
return rc;
}
static int erase_page(struct device *dev, unsigned int page)
{
struct stm32f1x_flash *regs = FLASH_STM32_REGS(dev);
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
u32_t page_address = CONFIG_FLASH_BASE_ADDRESS;
u32_t tmp;
int rc;
/* if the control register is locked, do not fail silently */
if (regs->cr & FLASH_CR_LOCK) {
if (regs->CR & FLASH_CR_LOCK) {
return -EIO;
}
@ -97,19 +97,19 @@ static int erase_page(struct device *dev, unsigned int page)
page_address += page * FLASH_PAGE_SIZE;
/* Set the PER bit and select the page you wish to erase */
regs->cr |= FLASH_CR_PER;
regs->ar = page_address;
regs->CR |= FLASH_CR_PER;
regs->AR = page_address;
/* Set the STRT bit */
regs->cr |= FLASH_CR_STRT;
regs->CR |= FLASH_CR_STRT;
/* flush the register write */
tmp = regs->cr;
tmp = regs->CR;
/* Wait for the BSY bit */
rc = flash_stm32_wait_flash_idle(dev);
regs->cr &= ~FLASH_CR_PER;
regs->CR &= ~FLASH_CR_PER;
return rc;
}

22
drivers/flash/flash_stm32f3x.c
View file

@ -35,12 +35,12 @@ static unsigned int get_page(off_t offset)
static int erase_page(struct device *dev, unsigned int page)
{
struct stm32f3x_flash *regs = FLASH_STM32_REGS(dev);
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
u32_t page_address = CONFIG_FLASH_BASE_ADDRESS;
int rc;
/* if the control register is locked, do not fail silently */
if (regs->cr & FLASH_CR_LOCK) {
if (regs->CR & FLASH_CR_LOCK) {
return -EIO;
}
@ -53,16 +53,16 @@ static int erase_page(struct device *dev, unsigned int page)
page_address += page * FLASH_PAGE_SIZE;
/* Set the PER bit and select the page you wish to erase */
regs->cr |= FLASH_CR_PER;
regs->CR |= FLASH_CR_PER;
/* Set page address */
regs->ar = page_address;
regs->AR = page_address;
/* Set the STRT bit */
regs->cr |= FLASH_CR_STRT;
regs->CR |= FLASH_CR_STRT;
/* Wait for the BSY bit */
rc = flash_stm32_wait_flash_idle(dev);
regs->cr &= ~FLASH_CR_PER;
regs->CR &= ~FLASH_CR_PER;
return rc;
}
@ -87,12 +87,12 @@ int flash_stm32_block_erase_loop(struct device *dev, unsigned int offset,
static int write_hword(struct device *dev, off_t offset, u16_t val)
{
volatile u16_t *flash = (u16_t *)(offset + CONFIG_FLASH_BASE_ADDRESS);
struct stm32f3x_flash *regs = FLASH_STM32_REGS(dev);
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
u32_t tmp;
int rc;
/* if the control register is locked, do not fail silently */
if (regs->cr & FLASH_CR_LOCK) {
if (regs->CR & FLASH_CR_LOCK) {
return -EIO;
}
@ -108,10 +108,10 @@ static int write_hword(struct device *dev, off_t offset, u16_t val)
}
/* Set the PG bit */
regs->cr |= FLASH_CR_PG;
regs->CR |= FLASH_CR_PG;
/* Flush the register write */
tmp = regs->cr;
tmp = regs->CR;
/* Perform the data write operation at the desired memory address */
*flash = val;
@ -120,7 +120,7 @@ static int write_hword(struct device *dev, off_t offset, u16_t val)
rc = flash_stm32_wait_flash_idle(dev);
/* Clear the PG bit */
regs->cr &= (~FLASH_CR_PG);
regs->CR &= (~FLASH_CR_PG);
return rc;
}

32
drivers/flash/flash_stm32f4x.c
View file

@ -21,11 +21,11 @@ bool flash_stm32_valid_range(struct device *dev, off_t offset, u32_t len,
ARG_UNUSED(write);
#if (FLASH_SECTOR_TOTAL == 12) && defined(FLASH_OPTCR_DB1M)
struct stm32f4x_flash *regs = FLASH_STM32_REGS(dev);
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
/*
* RM0090, table 7.1: STM32F42xxx, STM32F43xxx
*/
if (regs->optcr & FLASH_OPTCR_DB1M) {
if (regs->OPTCR & FLASH_OPTCR_DB1M) {
/* Device configured in Dual Bank, but not supported for now */
return false;
}
@ -36,12 +36,12 @@ bool flash_stm32_valid_range(struct device *dev, off_t offset, u32_t len,
static int write_byte(struct device *dev, off_t offset, u8_t val)
{
struct stm32f4x_flash *regs = FLASH_STM32_REGS(dev);
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
u32_t tmp;
int rc;
/* if the control register is locked, do not fail silently */
if (regs->cr & FLASH_CR_LOCK) {
if (regs->CR & FLASH_CR_LOCK) {
return -EIO;
}
@ -50,29 +50,29 @@ static int write_byte(struct device *dev, off_t offset, u8_t val)
return rc;
}
regs->cr &= ~CR_PSIZE_MASK;
regs->cr |= FLASH_PSIZE_BYTE;
regs->cr |= FLASH_CR_PG;
regs->CR &= ~CR_PSIZE_MASK;
regs->CR |= FLASH_PSIZE_BYTE;
regs->CR |= FLASH_CR_PG;
/* flush the register write */
tmp = regs->cr;
tmp = regs->CR;
*((u8_t *) offset + CONFIG_FLASH_BASE_ADDRESS) = val;
rc = flash_stm32_wait_flash_idle(dev);
regs->cr &= (~FLASH_CR_PG);
regs->CR &= (~FLASH_CR_PG);
return rc;
}
static int erase_sector(struct device *dev, u32_t sector)
{
struct stm32f4x_flash *regs = FLASH_STM32_REGS(dev);
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
u32_t tmp;
int rc;
/* if the control register is locked, do not fail silently */
if (regs->cr & FLASH_CR_LOCK) {
if (regs->CR & FLASH_CR_LOCK) {
return -EIO;
}
@ -92,15 +92,15 @@ static int erase_sector(struct device *dev, u32_t sector)
}
#endif
regs->cr &= STM32F4X_SECTOR_MASK;
regs->cr |= FLASH_CR_SER | (sector << 3);
regs->cr |= FLASH_CR_STRT;
regs->CR &= STM32F4X_SECTOR_MASK;
regs->CR |= FLASH_CR_SER | (sector << 3);
regs->CR |= FLASH_CR_STRT;
/* flush the register write */
tmp = regs->cr;
tmp = regs->CR;
rc = flash_stm32_wait_flash_idle(dev);
regs->cr &= ~(FLASH_CR_SER | FLASH_CR_SNB);
regs->CR &= ~(FLASH_CR_SER | FLASH_CR_SNB);
return rc;
}

18
drivers/flash/flash_stm32f7x.c
View file

@ -26,11 +26,11 @@ bool flash_stm32_valid_range(struct device *dev, off_t offset, u32_t len,
static int write_byte(struct device *dev, off_t offset, u8_t val)
{
struct stm32f7x_flash *regs = FLASH_STM32_REGS(dev);
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
int rc;
/* if the control register is locked, do not fail silently */
if (regs->cr & FLASH_CR_LOCK) {
if (regs->CR & FLASH_CR_LOCK) {
return -EIO;
}
@ -40,7 +40,7 @@ static int write_byte(struct device *dev, off_t offset, u8_t val)
}
/* prepare to write a single byte */
regs->cr = (regs->cr & CR_PSIZE_MASK) |
regs->CR = (regs->CR & CR_PSIZE_MASK) |
FLASH_PSIZE_BYTE | FLASH_CR_PG;
/* flush the register write */
__DSB();
@ -51,18 +51,18 @@ static int write_byte(struct device *dev, off_t offset, u8_t val)
__DSB();
rc = flash_stm32_wait_flash_idle(dev);
regs->cr &= (~FLASH_CR_PG);
regs->CR &= (~FLASH_CR_PG);
return rc;
}
static int erase_sector(struct device *dev, u32_t sector)
{
struct stm32f7x_flash *regs = FLASH_STM32_REGS(dev);
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
int rc;
/* if the control register is locked, do not fail silently */
if (regs->cr & FLASH_CR_LOCK) {
if (regs->CR & FLASH_CR_LOCK) {
return -EIO;
}
@ -86,7 +86,7 @@ static int erase_sector(struct device *dev, u32_t sector)
#endif /* CONFIG_FLASH_SIZE */
#endif /* defined(FLASH_OPTCR_nDBANK) && FLASH_SECTOR_TOTAL == 24 */
regs->cr = (regs->cr & (CR_PSIZE_MASK | STM32F7X_SECTOR_MASK)) |
regs->CR = (regs->CR & (CR_PSIZE_MASK | STM32F7X_SECTOR_MASK)) |
FLASH_PSIZE_BYTE |
FLASH_CR_SER |
(sector << FLASH_CR_SNB_Pos) |
@ -95,7 +95,7 @@ static int erase_sector(struct device *dev, u32_t sector)
__DSB();
rc = flash_stm32_wait_flash_idle(dev);
regs->cr &= ~(FLASH_CR_SER | FLASH_CR_SNB);
regs->CR &= ~(FLASH_CR_SER | FLASH_CR_SNB);
return rc;
}
@ -210,7 +210,7 @@ void flash_stm32_page_layout(struct device *dev,
size_t *layout_size)
{
#if FLASH_OPTCR_nDBANK
if (FLASH_STM32_REGS(dev)->optcr & FLASH_OPTCR_nDBANK) {
if (FLASH_STM32_REGS(dev)->OPTCR & FLASH_OPTCR_nDBANK) {
*layout = stm32f7_flash_layout_single_bank;
*layout_size = ARRAY_SIZE(stm32f7_flash_layout_single_bank);
} else {

26
drivers/flash/flash_stm32g0x.c
View file

@ -46,12 +46,12 @@ static unsigned int get_page(off_t offset)
static int write_dword(struct device *dev, off_t offset, u64_t val)
{
volatile u32_t *flash = (u32_t *)(offset + CONFIG_FLASH_BASE_ADDRESS);
struct stm32g0x_flash *regs = FLASH_STM32_REGS(dev);
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
u32_t tmp;
int rc;
/* if the control register is locked, do not fail silently */
if (regs->cr & FLASH_CR_LOCK) {
if (regs->CR & FLASH_CR_LOCK) {
return -EIO;
}
@ -68,10 +68,10 @@ static int write_dword(struct device *dev, off_t offset, u64_t val)
}
/* Set the PG bit */
regs->cr |= FLASH_CR_PG;
regs->CR |= FLASH_CR_PG;
/* Flush the register write */
tmp = regs->cr;
tmp = regs->CR;
/* Perform the data write operation at the desired memory address */
flash[0] = (u32_t)val;
@ -81,19 +81,19 @@ static int write_dword(struct device *dev, off_t offset, u64_t val)
rc = flash_stm32_wait_flash_idle(dev);
/* Clear the PG bit */
regs->cr &= (~FLASH_CR_PG);
regs->CR &= (~FLASH_CR_PG);
return rc;
}
static int erase_page(struct device *dev, unsigned int page)
{
struct stm32g0x_flash *regs = FLASH_STM32_REGS(dev);
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
u32_t tmp;
int rc;
/* if the control register is locked, do not fail silently */
if (regs->cr & FLASH_CR_LOCK) {
if (regs->CR & FLASH_CR_LOCK) {
return -EIO;
}
@ -104,20 +104,20 @@ static int erase_page(struct device *dev, unsigned int page)
}
/* Set the PER bit and select the page you wish to erase */
regs->cr |= FLASH_CR_PER;
regs->cr &= ~FLASH_CR_PNB_Msk;
regs->cr |= ((page % 256) << 3);
regs->CR |= FLASH_CR_PER;
regs->CR &= ~FLASH_CR_PNB_Msk;
regs->CR |= ((page % 256) << 3);
/* Set the STRT bit */
regs->cr |= FLASH_CR_STRT;
regs->CR |= FLASH_CR_STRT;
/* flush the register write */
tmp = regs->cr;
tmp = regs->CR;
/* Wait for the BSY bit */
rc = flash_stm32_wait_flash_idle(dev);
regs->cr &= ~FLASH_CR_PER;
regs->CR &= ~FLASH_CR_PER;
return rc;
}

26
drivers/flash/flash_stm32g4x.c
View file

@ -42,12 +42,12 @@ static unsigned int get_page(off_t offset)
static int write_dword(struct device *dev, off_t offset, u64_t val)
{
volatile u32_t *flash = (u32_t *)(offset + CONFIG_FLASH_BASE_ADDRESS);
struct stm32g4x_flash *regs = FLASH_STM32_REGS(dev);
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
u32_t tmp;
int rc;
/* if the control register is locked, do not fail silently */
if (regs->cr & FLASH_CR_LOCK) {
if (regs->CR & FLASH_CR_LOCK) {
return -EIO;
}
@ -64,10 +64,10 @@ static int write_dword(struct device *dev, off_t offset, u64_t val)
}
/* Set the PG bit */
regs->cr |= FLASH_CR_PG;
regs->CR |= FLASH_CR_PG;
/* Flush the register write */
tmp = regs->cr;
tmp = regs->CR;
/* Perform the data write operation at the desired memory address */
flash[0] = (u32_t)val;
@ -77,19 +77,19 @@ static int write_dword(struct device *dev, off_t offset, u64_t val)
rc = flash_stm32_wait_flash_idle(dev);
/* Clear the PG bit */
regs->cr &= (~FLASH_CR_PG);
regs->CR &= (~FLASH_CR_PG);
return rc;
}
static int erase_page(struct device *dev, unsigned int page)
{
struct stm32g4x_flash *regs = FLASH_STM32_REGS(dev);
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
u32_t tmp;
int rc;
/* if the control register is locked, do not fail silently */
if (regs->cr & FLASH_CR_LOCK) {
if (regs->CR & FLASH_CR_LOCK) {
return -EIO;
}
@ -100,20 +100,20 @@ static int erase_page(struct device *dev, unsigned int page)
}
/* Set the PER bit and select the page you wish to erase */
regs->cr |= FLASH_CR_PER;
regs->cr &= ~FLASH_CR_PNB_Msk;
regs->cr |= ((page % 256) << 3);
regs->CR |= FLASH_CR_PER;
regs->CR &= ~FLASH_CR_PNB_Msk;
regs->CR |= ((page % 256) << 3);
/* Set the STRT bit */
regs->cr |= FLASH_CR_STRT;
regs->CR |= FLASH_CR_STRT;
/* flush the register write */
tmp = regs->cr;
tmp = regs->CR;
/* Wait for the BSY bit */
rc = flash_stm32_wait_flash_idle(dev);
regs->cr &= ~FLASH_CR_PER;
regs->CR &= ~FLASH_CR_PER;
return rc;
}

44
drivers/flash/flash_stm32l4x.c
View file

@ -48,7 +48,7 @@ static unsigned int get_page(off_t offset)
static int write_dword(struct device *dev, off_t offset, u64_t val)
{
volatile u32_t *flash = (u32_t *)(offset + CONFIG_FLASH_BASE_ADDRESS);
struct stm32l4x_flash *regs = FLASH_STM32_REGS(dev);
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
#if defined(FLASH_OPTR_DUALBANK) || defined(FLASH_OPTR_DBANK)
bool dcache_enabled = false;
#endif /* FLASH_OPTR_DUALBANK || FLASH_OPTR_DBANK */
@ -56,7 +56,7 @@ static int write_dword(struct device *dev, off_t offset, u64_t val)
int rc;
/* if the control register is locked, do not fail silently */
if (regs->cr & FLASH_CR_LOCK) {
if (regs->CR & FLASH_CR_LOCK) {
return -EIO;
}
@ -77,17 +77,17 @@ static int write_dword(struct device *dev, off_t offset, u64_t val)
* Disable the data cache to avoid the silicon errata 2.2.3:
* "Data cache might be corrupted during Flash memory read-while-write operation"
*/
if (regs->acr.val & FLASH_ACR_DCEN) {
if (regs->ACR & FLASH_ACR_DCEN) {
dcache_enabled = true;
regs->acr.val &= (~FLASH_ACR_DCEN);
regs->ACR &= (~FLASH_ACR_DCEN);
}
#endif /* FLASH_OPTR_DUALBANK || FLASH_OPTR_DBANK */
/* Set the PG bit */
regs->cr |= FLASH_CR_PG;
regs->CR |= FLASH_CR_PG;
/* Flush the register write */
tmp = regs->cr;
tmp = regs->CR;
/* Perform the data write operation at the desired memory address */
flash[0] = (u32_t)val;
@ -97,14 +97,14 @@ static int write_dword(struct device *dev, off_t offset, u64_t val)
rc = flash_stm32_wait_flash_idle(dev);
/* Clear the PG bit */
regs->cr &= (~FLASH_CR_PG);
regs->CR &= (~FLASH_CR_PG);
#if defined(FLASH_OPTR_DUALBANK) || defined(FLASH_OPTR_DBANK)
/* Reset/enable the data cache if previously enabled */
if (dcache_enabled) {
regs->acr.val |= FLASH_ACR_DCRST;
regs->acr.val &= (~FLASH_ACR_DCRST);
regs->acr.val |= FLASH_ACR_DCEN;
regs->ACR |= FLASH_ACR_DCRST;
regs->ACR &= (~FLASH_ACR_DCRST);
regs->ACR |= FLASH_ACR_DCEN;
}
#endif /* FLASH_OPTR_DUALBANK || FLASH_OPTR_DBANK */
@ -113,7 +113,7 @@ static int write_dword(struct device *dev, off_t offset, u64_t val)
static int erase_page(struct device *dev, unsigned int page)
{
struct stm32l4x_flash *regs = FLASH_STM32_REGS(dev);
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
u32_t tmp;
u16_t pages_per_bank;
int rc;
@ -124,7 +124,7 @@ static int erase_page(struct device *dev, unsigned int page)
#elif defined(FLASH_OPTR_DUALBANK)
/* L4 series (2K page size) with configurable Dual Bank (default y) */
/* Dual Bank is only option for 1M devices */
if ((regs->optr & FLASH_OPTR_DUALBANK) || (DT_FLASH_SIZE == 1024)) {
if ((regs->OPTR & FLASH_OPTR_DUALBANK) || (DT_FLASH_SIZE == 1024)) {
/* Dual Bank configuration (nbr pages = flash size / 2 / 2K) */
pages_per_bank = DT_FLASH_SIZE >> 2;
} else {
@ -134,7 +134,7 @@ static int erase_page(struct device *dev, unsigned int page)
}
#elif defined(FLASH_OPTR_DBANK)
/* L4+ series (4K page size) with configurable Dual Bank (default y)*/
if (regs->optr & FLASH_OPTR_DBANK) {
if (regs->OPTR & FLASH_OPTR_DBANK) {
/* Dual Bank configuration (nbre pags = flash size / 2 / 4K) */
pages_per_bank = DT_FLASH_SIZE >> 3;
} else {
@ -145,7 +145,7 @@ static int erase_page(struct device *dev, unsigned int page)
#endif
/* if the control register is locked, do not fail silently */
if (regs->cr & FLASH_CR_LOCK) {
if (regs->CR & FLASH_CR_LOCK) {
return -EIO;
}
@ -156,26 +156,26 @@ static int erase_page(struct device *dev, unsigned int page)
}
/* Set the PER bit and select the page you wish to erase */
regs->cr |= FLASH_CR_PER;
regs->CR |= FLASH_CR_PER;
#ifdef FLASH_CR_BKER
regs->cr &= ~FLASH_CR_BKER_Msk;
regs->CR &= ~FLASH_CR_BKER_Msk;
/* Select bank, only for DUALBANK devices */
if (page >= pages_per_bank)
regs->cr |= FLASH_CR_BKER;
regs->CR |= FLASH_CR_BKER;
#endif
regs->cr &= ~FLASH_CR_PNB_Msk;
regs->cr |= ((page % pages_per_bank) << 3);
regs->CR &= ~FLASH_CR_PNB_Msk;
regs->CR |= ((page % pages_per_bank) << 3);
/* Set the STRT bit */
regs->cr |= FLASH_CR_STRT;
regs->CR |= FLASH_CR_STRT;
/* flush the register write */
tmp = regs->cr;
tmp = regs->CR;
/* Wait for the BSY bit */
rc = flash_stm32_wait_flash_idle(dev);
regs->cr &= ~FLASH_CR_PER;
regs->CR &= ~FLASH_CR_PER;
return rc;
}

28
drivers/flash/flash_stm32wbx.c
View file

@ -42,12 +42,12 @@ static u32_t get_page(off_t offset)
static int write_dword(struct device *dev, off_t offset, u64_t val)
{
volatile u32_t *flash = (u32_t *)(offset + CONFIG_FLASH_BASE_ADDRESS);
struct stm32wbx_flash *regs = FLASH_STM32_REGS(dev);
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
u32_t tmp;
int ret, rc;
/* if the control register is locked, do not fail silently */
if (regs->cr & FLASH_CR_LOCK) {
if (regs->CR & FLASH_CR_LOCK) {
rc = -EIO;
}
@ -63,10 +63,10 @@ static int write_dword(struct device *dev, off_t offset, u64_t val)
}
/* Set the PG bit */
regs->cr |= FLASH_CR_PG;
regs->CR |= FLASH_CR_PG;
/* Flush the register write */
tmp = regs->cr;
tmp = regs->CR;
/* Perform the data write operation at the desired memory address */
flash[0] = (u32_t)val;
@ -76,18 +76,18 @@ static int write_dword(struct device *dev, off_t offset, u64_t val)
rc = flash_stm32_wait_flash_idle(dev);
/* Clear the PG bit */
regs->cr &= (~FLASH_CR_PG);
regs->CR &= (~FLASH_CR_PG);
return 0;
}
static int erase_page(struct device *dev, u32_t page)
{
struct stm32wbx_flash *regs = FLASH_STM32_REGS(dev);
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
int rc;
/* if the control register is locked, do not fail silently */
if (regs->cr & FLASH_CR_LOCK) {
if (regs->CR & FLASH_CR_LOCK) {
return -EIO;
}
@ -98,21 +98,21 @@ static int erase_page(struct device *dev, u32_t page)
}
/* Check erase operation allowed */
if (regs->cr & FLASH_SR_PESD) {
if (regs->CR & FLASH_SR_PESD) {
return -EBUSY;
}
/* Proceed to erase the page */
regs->cr |= FLASH_CR_PER;
regs->cr &= ~FLASH_CR_PNB_Msk;
regs->cr |= page << FLASH_CR_PNB_Pos;
regs->CR |= FLASH_CR_PER;
regs->CR &= ~FLASH_CR_PNB_Msk;
regs->CR |= page << FLASH_CR_PNB_Pos;
regs->cr |= FLASH_CR_STRT;
regs->CR |= FLASH_CR_STRT;
/* Wait for the BSY bit */
rc = flash_stm32_wait_flash_idle(dev);
regs->cr &= (~FLASH_TYPEERASE_PAGES);
regs->CR &= (~FLASH_TYPEERASE_PAGES);
return rc;
}
@ -171,7 +171,7 @@ void flash_stm32_page_layout(struct device *dev,
int flash_stm32_check_status(struct device *dev)
{
struct stm32wbx_flash *regs = FLASH_STM32_REGS(dev);
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
u32_t error = 0;
/* Save Flash errors */

52
soc/arm/st_stm32/stm32f0/flash_registers.h
View file

@ -1,52 +0,0 @@
/*
* Copyright (c) 2017 RnDity Sp. z o.o.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32F0X_FLASH_REGISTERS_H_
#define _STM32F0X_FLASH_REGISTERS_H_
#include <zephyr/types.h>
/**
* @brief
*
* Based on reference manual:
* STM32F030x4/x6/x8/xC,
* STM32F070x6/xB advanced ARM ® -based MCUs
*
* Chapter 3.3.5: Embedded Flash Memory
*/
enum {
STM32_FLASH_LATENCY_0 = 0x0,
STM32_FLASH_LATENCY_1 = 0x1
};
/* 3.3.5.1 FLASH_ACR */
union ef_acr {
u32_t val;
struct {
u32_t latency :3 __packed;
u32_t rsvd__3 :1 __packed;
u32_t prftbe :1 __packed;
u32_t prftbs :1 __packed;
u32_t rsvd__6_31 :26 __packed;
} bit;
};
/* 3.3.5 Embedded flash registers */
struct stm32f0x_flash {
volatile union ef_acr acr;
volatile u32_t keyr;
volatile u32_t optkeyr;
volatile u32_t sr;
volatile u32_t cr;
volatile u32_t ar;
volatile u32_t rsvd;
volatile u32_t obr;
volatile u32_t wrpr;
};
#endif /* _STM32F0X_FLASH_REGISTERS_H_ */

51
soc/arm/st_stm32/stm32f1/flash_registers.h
View file

@ -1,51 +0,0 @@
/*
* Copyright (c) 2016 Open-RnD Sp. z o.o.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32F10X_FLASH_REGISTERS_H_
#define _STM32F10X_FLASH_REGISTERS_H_
/**
* @brief
*
* Based on reference manual:
* STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
* advanced ARM(r)-based 32-bit MCUs
*
* Chapter 3.3.3: Embedded Flash Memory
*/
enum {
STM32F10X_FLASH_LATENCY_0 = 0x0,
STM32F10X_FLASH_LATENCY_1 = 0x1,
STM32F10X_FLASH_LATENCY_2 = 0x2,
};
/* 3.3.3 FLASH_ACR */
union __ef_acr {
u32_t val;
struct {
u32_t latency :3 __packed;
u32_t hlfcya :1 __packed;
u32_t prftbe :1 __packed;
u32_t prftbs :1 __packed;
u32_t rsvd__6_31 :26 __packed;
} bit;
};
/* 3.3.3 Embedded flash registers */
struct stm32f1x_flash {
volatile union __ef_acr acr;
volatile u32_t keyr;
volatile u32_t optkeyr;
volatile u32_t sr;
volatile u32_t cr;
volatile u32_t ar;
volatile u32_t rsvd;
volatile u32_t obr;
volatile u32_t wrpr;
};
#endif /* _STM32F10X_FLASHREGISTERS_H_ */

60
soc/arm/st_stm32/stm32f3/flash_registers.h
View file

@ -1,60 +0,0 @@
/*
* Copyright (c) 2016 RnDity Sp. z o.o.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32F3X_FLASH_REGISTERS_H_
#define _STM32F3X_FLASH_REGISTERS_H_
#include <zephyr/types.h>
/**
* @brief
*
* Based on reference manual:
* STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
* advanced ARM(r)-based 32-bit MCUs
* &
* STM32F334xx advanced ARM(r)-based 32-bit MCUs
*
* Chapter 3.3.3: Embedded Flash Memory
*/
enum {
STM32_FLASH_LATENCY_0 = 0x0,
STM32_FLASH_LATENCY_1 = 0x1,
STM32_FLASH_LATENCY_2 = 0x2,
};
/* 3.3.3 FLASH_ACR */
union ef_acr {
u32_t val;
struct {
u32_t latency :3 __packed;
u32_t hlfcya :1 __packed;
u32_t prftbe :1 __packed;
u32_t prftbs :1 __packed;
u32_t rsvd__6_31 :26 __packed;
} bit;
};
/* 3.3.3 Embedded flash registers */
struct stm32f3x_flash {
volatile union ef_acr acr;
volatile u32_t keyr;
volatile u32_t optkeyr;
volatile u32_t sr;
volatile u32_t cr;
volatile u32_t ar;
volatile u32_t rsvd;
volatile u32_t obr;
volatile u32_t wrpr;
};
/* list of device commands */
enum stm32_embedded_flash_cmd {
STM32_FLASH_CMD_LATENCY_FOR_CLOCK_SET,
};
#endif /* _STM32F3X_FLASH_REGISTERS_H_ */

42
soc/arm/st_stm32/stm32f4/flash_registers.h
View file

@ -1,42 +0,0 @@
/*
* Copyright (c) 2016 Linaro Limited.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32F4X_FLASH_REGISTERS_H_
#define _STM32F4X_FLASH_REGISTERS_H_
/**
* @brief
*
* Based on reference manual:
*
* Chapter 3.4: Embedded Flash Memory
*/
union __flash_acr {
u32_t val;
struct {
u32_t latency :4 __packed;
u32_t rsvd__4_7 :4 __packed;
u32_t prften :1 __packed;
u32_t icen :1 __packed;
u32_t dcen :1 __packed;
u32_t icrst :1 __packed;
u32_t dcrst :1 __packed;
u32_t rsvd__13_31 :19 __packed;
} bit;
};
/* 3.8.7 Embedded flash registers */
struct stm32f4x_flash {
volatile union __flash_acr acr;
volatile u32_t keyr;
volatile u32_t optkeyr;
volatile u32_t sr;
volatile u32_t cr;
volatile u32_t optcr;
};
#endif /* _STM32F4X_FLASHREGISTERS_H_ */

44
soc/arm/st_stm32/stm32f7/flash_registers.h
View file

@ -1,44 +0,0 @@
/*
* Copyright (c) 2018 Yurii Hamann
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32F7X_FLASH_REGISTERS_H_
#define _STM32F7X_FLASH_REGISTERS_H_
/**
* @brief
*
* Based on reference manual:
* RM0385 Reference manual STM32F75xxx and STM32F74xxx
* advanced ARM(r)-based 32-bit MCUs
*
* Chapter 3: Embedded Flash Memory
*/
union __flash_acr {
u32_t val;
struct {
u32_t latency :4 __packed;
u32_t rsvd__4_7 :4 __packed;
u32_t prften :1 __packed;
u32_t arten :1 __packed;
u32_t rsvd__10 :1 __packed;
u32_t artrst :1 __packed;
u32_t rsvd__12_31 :20 __packed;
} bit;
};
/* 3.7 FLASH registers */
struct stm32f7x_flash {
volatile union __flash_acr acr;
volatile u32_t keyr;
volatile u32_t optkeyr;
volatile u32_t sr;
volatile u32_t cr;
volatile u32_t optcr;
volatile u32_t optcr1;
};
#endif /* _STM32F7X_FLASHREGISTERS_H_ */

53
soc/arm/st_stm32/stm32g0/flash_registers.h
View file

@ -1,53 +0,0 @@
/*
* Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32G0X_FLASH_REGISTERS_H_
#define _STM32G0X_FLASH_REGISTERS_H_
#define FLASH_SR_BSY FLASH_SR_BSY1
enum {
STM32_FLASH_LATENCY_0 = 0x0,
STM32_FLASH_LATENCY_1 = 0x1,
STM32_FLASH_LATENCY_2 = 0x2,
};
/* 3.7.1 FLASH_ACR */
union __ef_acr {
u32_t val;
struct {
u32_t latency :3 __packed;
u32_t rsvd__3_7 :5 __packed;
u32_t prften :1 __packed;
u32_t icen :1 __packed;
u32_t rsvd__10 :1 __packed;
u32_t icrst :1 __packed;
u32_t rsvd__12_15 :4 __packed;
u32_t empty :1 __packed;
u32_t rsvd__17 :1 __packed;
u32_t dbg_swend :1 __packed;
u32_t rsvd__19_31 :13 __packed;
} bit;
};
/* FLASH register map */
struct stm32g0x_flash {
volatile union __ef_acr acr;
volatile u32_t rsvd__4;
volatile u32_t keyr;
volatile u32_t optkeyr;
volatile u32_t sr;
volatile u32_t cr;
volatile u32_t eccr;
volatile u32_t rsvd_0;
volatile u32_t optr;
volatile u32_t pcrop1sr;
volatile u32_t pcrop1er;
volatile u32_t wrp1ar;
volatile u32_t wrp1br;
};
#endif /* _STM32G0X_FLASH_REGISTERS_H_ */

67
soc/arm/st_stm32/stm32g4/flash_registers.h
View file

@ -1,67 +0,0 @@
/*
* Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32G4X_FLASH_REGISTERS_H_
#define _STM32G4X_FLASH_REGISTERS_H_
enum {
STM32G4X_FLASH_LATENCY_0 = 0x0,
STM32G4X_FLASH_LATENCY_1 = 0x1,
STM32G4X_FLASH_LATENCY_2 = 0x2,
STM32G4X_FLASH_LATENCY_3 = 0x3,
STM32G4X_FLASH_LATENCY_4 = 0x4,
STM32G4X_FLASH_LATENCY_5 = 0x5,
STM32G4X_FLASH_LATENCY_6 = 0x6,
STM32G4X_FLASH_LATENCY_7 = 0x7,
STM32G4X_FLASH_LATENCY_8 = 0x8,
STM32G4X_FLASH_LATENCY_9 = 0x9,
STM32G4X_FLASH_LATENCY_10 = 0x10,
STM32G4X_FLASH_LATENCY_11 = 0x11,
STM32G4X_FLASH_LATENCY_12 = 0x12,
STM32G4X_FLASH_LATENCY_13 = 0x13,
STM32G4X_FLASH_LATENCY_14 = 0x14,
};
/* 3.7.1 FLASH_ACR */
union __ef_acr {
u32_t val;
struct {
u32_t latency :4 __packed;
u32_t rsvd__4_7 :4 __packed;
u32_t prften :1 __packed;
u32_t icen :1 __packed;
u32_t dcen :1 __packed;
u32_t icrst :1 __packed;
u32_t dcrst :1 __packed;
u32_t run_pd :1 __packed;
u32_t sleep_pd :1 __packed;
u32_t rsvd__15_17 :3 __packed;
u32_t dbg_swend :1 __packed;
u32_t rsvd__19_31 :13 __packed;
} bit;
};
/* 3.7.13 Embedded flash registers */
struct stm32g4x_flash {
volatile union __ef_acr acr;
volatile u32_t pdkeyr;
volatile u32_t keyr;
volatile u32_t optkeyr;
volatile u32_t sr;
volatile u32_t cr;
volatile u32_t eccr;
volatile u32_t optr;
volatile u32_t pcrop1sr;
volatile u32_t pcrop1er;
volatile u32_t wrp1ar;
volatile u32_t wrp1br;
volatile u32_t pcrop2sr;
volatile u32_t pcrop2er;
volatile u32_t wrp2ar;
volatile u32_t wrp2br;
};
#endif /* _STM32G4X_FLASH_REGISTERS_H_ */

63
soc/arm/st_stm32/stm32l4/flash_registers.h
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@ -1,63 +0,0 @@
/*
* Copyright (c) 2016 Open-RnD Sp. z o.o.
* Copyright (c) 2016 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32L4X_FLASH_REGISTERS_H_
#define _STM32L4X_FLASH_REGISTERS_H_
enum {
STM32L4X_FLASH_LATENCY_0 = 0x0,
STM32L4X_FLASH_LATENCY_1 = 0x1,
STM32L4X_FLASH_LATENCY_2 = 0x2,
STM32L4X_FLASH_LATENCY_3 = 0x3,
STM32L4X_FLASH_LATENCY_4 = 0x4,
};
/* 3.7.1 FLASH_ACR */
union __ef_acr {
u32_t val;
struct {
u32_t latency :3 __packed;
u32_t rsvd__3_7 :5 __packed;
u32_t prften :1 __packed;
u32_t icen :1 __packed;
u32_t dcen :1 __packed;
u32_t icrst :1 __packed;
u32_t dcrst :1 __packed;
u32_t run_pd :1 __packed;
u32_t sleep_pd :1 __packed;
u32_t rsvd__16_31 :17 __packed;
} bit;
};
/* FLASH register map */
struct stm32l4x_flash {
volatile union __ef_acr acr;
volatile u32_t pdkeyr;
volatile u32_t keyr;
volatile u32_t optkeyr;
volatile u32_t sr;
volatile u32_t cr;
volatile u32_t eccr;
volatile u32_t rsvd_0;
volatile u32_t optr;
volatile u32_t pcrop1sr;
volatile u32_t pcrop1er;
volatile u32_t wrp1ar;
volatile u32_t wrp1br;
volatile u32_t rsvd_2[4];
/*
* The registers below are only present on STM32L4x2, STM32L4x5,
* STM32L4x6.
*/
volatile u32_t pcrop2sr;
volatile u32_t pcrop2er;
volatile u32_t wrp2ar;
volatile u32_t wrp2br;
};
#endif /* _STM32L4X_FLASH_REGISTERS_H_ */

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soc/arm/st_stm32/stm32wb/flash_registers.h
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/*
* Copyright (c) 2019 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32WBX_FLASH_REGISTERS_H_
#define _STM32WBX_FLASH_REGISTERS_H_
enum {
STM32WBX_FLASH_LATENCY_0 = 0x0,
STM32WBX_FLASH_LATENCY_1 = 0x1,
STM32WBX_FLASH_LATENCY_2 = 0x2,
STM32WBX_FLASH_LATENCY_3 = 0x3,
STM32WBX_FLASH_LATENCY_4 = 0x4,
};
/* 3.7.1 FLASH_ACR */
union __ef_acr {
u32_t val;
struct {
u32_t latency :3 __packed;
u32_t rsvd__3_7 :5 __packed;
u32_t prften :1 __packed;
u32_t icen :1 __packed;
u32_t dcen :1 __packed;
u32_t icrst :1 __packed;
u32_t dcrst :1 __packed;
u32_t rsvd__13_14 :2 __packed;
u32_t pes :1 __packed;
u32_t empty :1 __packed;
u32_t rsvd__17_31 :15 __packed;
} bit;
};
/* FLASH register map */
struct stm32wbx_flash {
volatile union __ef_acr acr;
volatile u32_t rsvd_0;
volatile u32_t keyr;
volatile u32_t optkeyr;
volatile u32_t sr;
volatile u32_t cr;
volatile u32_t eccr;
volatile u32_t rsvd_1;
volatile u32_t optr;
volatile u32_t pcrop1asr;
volatile u32_t pcrop1aer;
volatile u32_t wrp1ar;
volatile u32_t wrp1br;
volatile u32_t pcrop1bsr;
volatile u32_t pcrop1ber;
volatile u32_t ipccbr;
volatile u32_t rsvd_2[8];
volatile u32_t c2acr;
volatile u32_t c2sr;
volatile u32_t c2cr;
volatile u32_t rsvd_3[7];
volatile u32_t sfr;
volatile u32_t srrvr;
};
#endif /* _STM32WBX_FLASH_REGISTERS_H_ */