soc: silabs_exx32: Add support for SiLabs EFR32BG13P SoC
This commit adds support for Silicon Labs EFR32BG13P (Blue Gecko) SoC. Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
This commit is contained in:
parent
729a9b0050
commit
bdcfa4f375
14 changed files with 451 additions and 1 deletions
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@ -242,6 +242,7 @@
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/dts/arm/microchip/ @franciscomunoz @albertofloyd @scottwcpg
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/dts/arm/silabs/efm32gg11b* @oanerer
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/dts/arm/silabs/efm32_jg_pg* @chrta
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/dts/arm/silabs/efr32bg13p* @mnkp
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/dts/arm/silabs/efm32jg12b* @chrta
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/dts/arm/silabs/efm32pg12b* @chrta
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/dts/riscv/microsemi-miv.dtsi @galak
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188
dts/arm/silabs/efr32bg13p.dtsi
Normal file
188
dts/arm/silabs/efr32bg13p.dtsi
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/*
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* Copyright (c) 2020 Piotr Mienkowski
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/i2c/i2c.h>
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#include "gpio_gecko.h"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-m4f";
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reg = <0>;
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};
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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soc {
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flash-controller@400e0000 {
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compatible = "silabs,gecko-flash-controller";
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label = "FLASH_CTRL";
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reg = <0x400e0000 0x104>;
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interrupts = <25 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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label = "FLASH_0";
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write-block-size = <4>;
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erase-block-size = <2048>;
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};
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};
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usart0: usart@40010000 { /* USART0 */
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compatible = "silabs,gecko-usart";
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reg = <0x40010000 0x400>;
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interrupts = <12 0>, <13 0>;
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interrupt-names = "rx", "tx";
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peripheral-id = <0>;
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status = "disabled";
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label = "USART_0";
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};
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usart1: usart@40010400 { /* USART1 */
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compatible = "silabs,gecko-usart";
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reg = <0x40010400 0x400>;
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interrupts = <20 0>, <21 0>;
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interrupt-names = "rx", "tx";
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peripheral-id = <1>;
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status = "disabled";
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label = "USART_1";
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};
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usart2: usart@40010800 { /* USART2 */
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compatible = "silabs,gecko-usart";
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reg = <0x40010800 0x400>;
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interrupts = <38 0>, <39 0>;
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interrupt-names = "rx", "tx";
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peripheral-id = <2>;
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status = "disabled";
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label = "USART_2";
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};
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leuart0: leuart@4004a000 { /* LEUART0 */
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compatible = "silabs,gecko-leuart";
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reg = <0x4004a000 0x400>;
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interrupts = <22 0>;
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peripheral-id = <0>;
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status = "disabled";
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label = "LEUART_0";
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};
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i2c0: i2c@4000c000 {
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compatible = "silabs,gecko-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x4000c000 0x400>;
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interrupts = <17 0>;
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label = "I2C_0";
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status = "disabled";
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};
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i2c1: i2c@4000c400 {
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compatible = "silabs,gecko-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x4000c400 0x400>;
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interrupts = <40 0>;
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label = "I2C_1";
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status = "disabled";
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};
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rtcc0: rtcc@40042000 {
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compatible = "silabs,gecko-rtcc";
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reg = <0x40042000 0x184>;
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interrupts = <31 0>;
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clock-frequency = <32768>;
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prescaler = <1>;
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status = "disabled";
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label = "RTCC_0";
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};
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gpio: gpio@4000a400 {
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compatible = "silabs,gecko-gpio";
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reg = <0x4000a400 0xc00>;
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interrupts = <10 2 18 2>;
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interrupt-names = "GPIO_EVEN", "GPIO_ODD";
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label = "GPIO";
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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gpioa: gpio@4000a000 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x4000a000 0x30>;
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label = "GPIO_A";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpiob: gpio@4000a030 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x4000a030 0x30>;
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label = "GPIO_B";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioc: gpio@4000a060 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x4000a060 0x30>;
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label = "GPIO_C";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpiod: gpio@4000a090 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x4000a090 0x30>;
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label = "GPIO_D";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpiof: gpio@4000a0f0 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x4000a0f0 0x30>;
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label = "GPIO_F";
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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wdog0: wdog@40052000 {
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compatible = "silabs,gecko-wdog";
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reg = <0x40052000 0x2C>;
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label = "WDOG0";
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interrupts = <2 0>;
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status = "disabled";
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};
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wdog1: wdog@40052400 {
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compatible = "silabs,gecko-wdog";
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reg = <0x40052400 0x2C>;
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label = "WDOG1";
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interrupts = <3 0>;
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status = "disabled";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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24
dts/arm/silabs/efr32bg13p632f512gm48.dtsi
Normal file
24
dts/arm/silabs/efr32bg13p632f512gm48.dtsi
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/*
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* Copyright (c) 2020 Piotr Mienkowski
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <silabs/efr32bg13p.dtsi>
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/ {
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(64)>;
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};
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soc {
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compatible = "silabs,efr32bg13p632f512gm48", "silabs,efr32bg13p", "silabs,efr32", "simple-bus";
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flash-controller@400e0000 {
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flash0: flash@0 {
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reg = <0 DT_SIZE_K(512)>;
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};
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};
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};
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};
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19
dts/bindings/gpio/silabs,gecko-gpio-port.yaml
Normal file
19
dts/bindings/gpio/silabs,gecko-gpio-port.yaml
Normal file
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description: SiLabs Gecko GPIO port node
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compatible: "silabs,gecko-gpio-port"
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include: [gpio-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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label:
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required: true
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"#gpio-cells":
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const: 2
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gpio-cells:
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- pin
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- flags
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20
dts/bindings/gpio/silabs,gecko-gpio.yaml
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20
dts/bindings/gpio/silabs,gecko-gpio.yaml
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description: SiLabs Gecko GPIO node
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compatible: "silabs,gecko-gpio"
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include: base.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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label:
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required: true
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location-swo:
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type: int
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required: false
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description: Serial Wire Output (SWO) PIN location
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32
soc/arm/silabs_exx32/efr32bg13p/Kconfig.defconfig.efr32bg13p
Normal file
32
soc/arm/silabs_exx32/efr32bg13p/Kconfig.defconfig.efr32bg13p
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# Silicon Labs EFR32BG13P (Blue Gecko) MCU configuration options
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# Copyright (c) 2020 Piotr Mienkowski
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# SPDX-License-Identifier: Apache-2.0
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if GPIO
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config GPIO_GECKO
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default y
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endif # GPIO
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if I2C
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config I2C_GECKO
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default y
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endif # I2C
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if FLASH
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config SOC_FLASH_GECKO
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default y
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endif # FLASH
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if SPI
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config SPI_GECKO
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default y
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endif # SPI
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20
soc/arm/silabs_exx32/efr32bg13p/Kconfig.defconfig.series
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20
soc/arm/silabs_exx32/efr32bg13p/Kconfig.defconfig.series
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# Silicon Labs EFR32BG13P (Blue Gecko) MCU configuration options
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# Copyright (c) 2020 Piotr Mienkowski
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_EFR32BG13P
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config SOC_SERIES
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default "efr32bg13p"
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config SOC_PART_NUMBER
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default "EFR32BG13P632F512GM48" if SOC_PART_NUMBER_EFR32BG13P632F512GM48
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config NUM_IRQS
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# must be >= the highest interrupt number used
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default 47
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source "soc/arm/silabs_exx32/efr32bg13p/Kconfig.defconfig.efr32bg13p"
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endif # SOC_SERIES_EFR32BG13P
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24
soc/arm/silabs_exx32/efr32bg13p/Kconfig.series
Normal file
24
soc/arm/silabs_exx32/efr32bg13p/Kconfig.series
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# Silicon Labs EFR32BG13P (Blue Gecko) MCU
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# Copyright (c) 2020 Piotr Mienkowski
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_EFR32BG13P
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bool "EFR32BG13P Series MCU"
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select ARM
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select CPU_CORTEX_M4
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_FPU
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select CPU_HAS_ARM_MPU
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select SOC_FAMILY_EXX32
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select HAS_SILABS_GECKO
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select HAS_SWO
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select HAS_SYS_POWER_STATE_SLEEP_1
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select HAS_SYS_POWER_STATE_SLEEP_2
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select HAS_SYS_POWER_STATE_SLEEP_3
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select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
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select SOC_GECKO_CMU
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select SOC_GECKO_EMU
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select SOC_GECKO_GPIO
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help
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Enable support for EFR32BG13P Blue Gecko MCU series
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11
soc/arm/silabs_exx32/efr32bg13p/Kconfig.soc
Normal file
11
soc/arm/silabs_exx32/efr32bg13p/Kconfig.soc
Normal file
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# Silicon Labs EFR32BG13P (Blue Gecko) MCU series
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# Copyright (c) 2020 Piotr Mienkowski
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_EFR32BG13P
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config SOC_PART_NUMBER_EFR32BG13P632F512GM48
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bool
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endif # SOC_SERIES_EFR32BG13P
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37
soc/arm/silabs_exx32/efr32bg13p/dts_fixup.h
Normal file
37
soc/arm/silabs_exx32/efr32bg13p/dts_fixup.h
Normal file
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/*
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* Copyright (c) 2020 Piotr Mienkowski
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* This file is a temporary workaround for mapping of the generated information
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* to the current driver definitions. This will be removed when the drivers
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* are modified to handle the generated information, or the mapping of
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* generated data matches the driver definitions.
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*/
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY
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#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS
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#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL
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#define DT_GPIO_GECKO_COMMON_NAME DT_SILABS_GECKO_GPIO_4000A400_LABEL
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#define DT_GPIO_GECKO_COMMON_EVEN_IRQ DT_SILABS_GECKO_GPIO_4000A400_IRQ_GPIO_EVEN
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#define DT_GPIO_GECKO_COMMON_EVEN_PRI DT_SILABS_GECKO_GPIO_4000A400_IRQ_GPIO_EVEN_PRIORITY
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#define DT_GPIO_GECKO_COMMON_ODD_IRQ DT_SILABS_GECKO_GPIO_4000A400_IRQ_GPIO_ODD
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#define DT_GPIO_GECKO_COMMON_ODD_PRI DT_SILABS_GECKO_GPIO_4000A400_IRQ_GPIO_ODD_PRIORITY
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#define DT_GPIO_GECKO_SWO_LOCATION DT_SILABS_GECKO_GPIO_4000A400_LOCATION_SWO
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#define DT_GPIO_GECKO_PORTA_NAME DT_SILABS_GECKO_GPIO_PORT_4000A000_LABEL
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#define DT_GPIO_GECKO_PORTB_NAME DT_SILABS_GECKO_GPIO_PORT_4000A030_LABEL
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#define DT_GPIO_GECKO_PORTC_NAME DT_SILABS_GECKO_GPIO_PORT_4000A060_LABEL
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#define DT_GPIO_GECKO_PORTD_NAME DT_SILABS_GECKO_GPIO_PORT_4000A090_LABEL
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#define DT_GPIO_GECKO_PORTF_NAME DT_SILABS_GECKO_GPIO_PORT_4000A0F0_LABEL
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#define DT_GPIO_GECKO_PORTI_NAME DT_SILABS_GECKO_GPIO_PORT_4000A180_LABEL
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#define DT_GPIO_GECKO_PORTJ_NAME DT_SILABS_GECKO_GPIO_PORT_4000A1B0_LABEL
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#define DT_GPIO_GECKO_PORTK_NAME DT_SILABS_GECKO_GPIO_PORT_4000A1E0_LABEL
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/* End of SoC Level DTS fixup file */
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16
soc/arm/silabs_exx32/efr32bg13p/linker.ld
Normal file
16
soc/arm/silabs_exx32/efr32bg13p/linker.ld
Normal file
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/*
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* Copyright (c) 2018 Diego Sueiro
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Linker command/script file
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*
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* This is the linker script for both standard images.
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*/
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#include <autoconf.h>
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#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>
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30
soc/arm/silabs_exx32/efr32bg13p/soc.h
Normal file
30
soc/arm/silabs_exx32/efr32bg13p/soc.h
Normal file
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/*
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* Copyright (c) 2020 Piotr Mienkowski
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Register access macros for the EFR32BG13P SoC
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*
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*/
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#ifndef EFR32BG13P_SOC_H_
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#define EFR32BG13P_SOC_H_
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#include <sys/util.h>
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#ifndef _ASMLANGUAGE
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#include <em_common.h>
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#include "soc_pinmap.h"
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#include "../common/soc_gpio.h"
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/* Add include for DTS generated information */
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#include <devicetree.h>
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#endif /* !_ASMLANGUAGE */
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#endif /* EFR32BG13P_SOC_H_ */
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28
soc/arm/silabs_exx32/efr32bg13p/soc_pinmap.h
Normal file
28
soc/arm/silabs_exx32/efr32bg13p/soc_pinmap.h
Normal file
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|
|||
/*
|
||||
* Copyright (c) 2020 Piotr Mienkowski
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/** @file
|
||||
* @brief Silabs EFR32BG13P MCU pin definitions.
|
||||
*/
|
||||
|
||||
#ifndef SOC_PINMAP_H_
|
||||
#define SOC_PINMAP_H_
|
||||
|
||||
#include <em_gpio.h>
|
||||
|
||||
/* Serial Wire Output (SWO) */
|
||||
#if (DT_GPIO_GECKO_SWO_LOCATION == 0)
|
||||
#define PIN_SWO {gpioPortF, 2, gpioModePushPull, 1}
|
||||
#elif (DT_GPIO_GECKO_SWO_LOCATION == 1)
|
||||
#define PIN_SWO {gpioPortB, 13, gpioModePushPull, 1}
|
||||
#elif (DT_GPIO_GECKO_SWO_LOCATION == 2)
|
||||
#define PIN_SWO {gpioPortD, 15, gpioModePushPull, 1}
|
||||
#elif (DT_GPIO_GECKO_SWO_LOCATION == 3)
|
||||
#define PIN_SWO {gpioPortC, 11, gpioModePushPull, 1}
|
||||
#elif (DT_GPIO_GECKO_SWO_LOCATION >= 4)
|
||||
#error ("Invalid SWO pin location")
|
||||
#endif
|
||||
|
||||
#endif /* SOC_PINMAP_H_ */
|
2
west.yml
2
west.yml
|
@ -62,7 +62,7 @@ manifest:
|
|||
revision: 03c8819ac3105cc2aee295a8d330de0e665b705f
|
||||
path: modules/hal/microchip
|
||||
- name: hal_silabs
|
||||
revision: 9a3fe1af3a14bf88c86b9cda3bf2a0921d5a97a1
|
||||
revision: 0fb710f258d7ed84a75cfea40319eaf531b61d1e
|
||||
path: modules/hal/silabs
|
||||
- name: hal_st
|
||||
revision: fa481784b3c49780f18d50bafe00390ccb62b2ec
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue