michaelh/zephyr
1
0
Fork 0
Code Releases Activity

soc: silabs_exx32: Add support for SiLabs EFR32BG13P SoC

Browse source 
This commit adds support for Silicon Labs EFR32BG13P (Blue Gecko) SoC.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
This commit is contained in:
Piotr Mienkowski 2020-01-26 22:37:50 +01:00 • committed by Kumar Gala
commit bdcfa4f375
14 changed files with 451 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

1
CODEOWNERS
View file

@ -242,6 +242,7 @@
/dts/arm/microchip/ @franciscomunoz @albertofloyd @scottwcpg
/dts/arm/silabs/efm32gg11b* @oanerer
/dts/arm/silabs/efm32_jg_pg* @chrta
/dts/arm/silabs/efr32bg13p* @mnkp
/dts/arm/silabs/efm32jg12b* @chrta
/dts/arm/silabs/efm32pg12b* @chrta
/dts/riscv/microsemi-miv.dtsi @galak

188
dts/arm/silabs/efr32bg13p.dtsi Normal file
View file

@ -0,0 +1,188 @@
/*
* Copyright (c) 2020 Piotr Mienkowski
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/i2c/i2c.h>
#include "gpio_gecko.h"
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-m4f";
reg = <0>;
};
};
sram0: memory@20000000 {
compatible = "mmio-sram";
};
soc {
flash-controller@400e0000 {
compatible = "silabs,gecko-flash-controller";
label = "FLASH_CTRL";
reg = <0x400e0000 0x104>;
interrupts = <25 0>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@0 {
compatible = "soc-nv-flash";
label = "FLASH_0";
write-block-size = <4>;
erase-block-size = <2048>;
};
};
usart0: usart@40010000 { /* USART0 */
compatible = "silabs,gecko-usart";
reg = <0x40010000 0x400>;
interrupts = <12 0>, <13 0>;
interrupt-names = "rx", "tx";
peripheral-id = <0>;
status = "disabled";
label = "USART_0";
};
usart1: usart@40010400 { /* USART1 */
compatible = "silabs,gecko-usart";
reg = <0x40010400 0x400>;
interrupts = <20 0>, <21 0>;
interrupt-names = "rx", "tx";
peripheral-id = <1>;
status = "disabled";
label = "USART_1";
};
usart2: usart@40010800 { /* USART2 */
compatible = "silabs,gecko-usart";
reg = <0x40010800 0x400>;
interrupts = <38 0>, <39 0>;
interrupt-names = "rx", "tx";
peripheral-id = <2>;
status = "disabled";
label = "USART_2";
};
leuart0: leuart@4004a000 { /* LEUART0 */
compatible = "silabs,gecko-leuart";
reg = <0x4004a000 0x400>;
interrupts = <22 0>;
peripheral-id = <0>;
status = "disabled";
label = "LEUART_0";
};
i2c0: i2c@4000c000 {
compatible = "silabs,gecko-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4000c000 0x400>;
interrupts = <17 0>;
label = "I2C_0";
status = "disabled";
};
i2c1: i2c@4000c400 {
compatible = "silabs,gecko-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4000c400 0x400>;
interrupts = <40 0>;
label = "I2C_1";
status = "disabled";
};
rtcc0: rtcc@40042000 {
compatible = "silabs,gecko-rtcc";
reg = <0x40042000 0x184>;
interrupts = <31 0>;
clock-frequency = <32768>;
prescaler = <1>;
status = "disabled";
label = "RTCC_0";
};
gpio: gpio@4000a400 {
compatible = "silabs,gecko-gpio";
reg = <0x4000a400 0xc00>;
interrupts = <10 2 18 2>;
interrupt-names = "GPIO_EVEN", "GPIO_ODD";
label = "GPIO";
ranges;
#address-cells = <1>;
#size-cells = <1>;
gpioa: gpio@4000a000 {
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a000 0x30>;
label = "GPIO_A";
gpio-controller;
#gpio-cells = <2>;
};
gpiob: gpio@4000a030 {
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a030 0x30>;
label = "GPIO_B";
gpio-controller;
#gpio-cells = <2>;
};
gpioc: gpio@4000a060 {
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a060 0x30>;
label = "GPIO_C";
gpio-controller;
#gpio-cells = <2>;
};
gpiod: gpio@4000a090 {
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a090 0x30>;
label = "GPIO_D";
gpio-controller;
#gpio-cells = <2>;
};
gpiof: gpio@4000a0f0 {
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a0f0 0x30>;
label = "GPIO_F";
gpio-controller;
#gpio-cells = <2>;
};
};
wdog0: wdog@40052000 {
compatible = "silabs,gecko-wdog";
reg = <0x40052000 0x2C>;
label = "WDOG0";
interrupts = <2 0>;
status = "disabled";
};
wdog1: wdog@40052400 {
compatible = "silabs,gecko-wdog";
reg = <0x40052400 0x2C>;
label = "WDOG1";
interrupts = <3 0>;
status = "disabled";
};
};
};
&nvic {
arm,num-irq-priority-bits = <3>;
};

24
dts/arm/silabs/efr32bg13p632f512gm48.dtsi Normal file
View file

@ -0,0 +1,24 @@
/*
* Copyright (c) 2020 Piotr Mienkowski
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <silabs/efr32bg13p.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(64)>;
};
soc {
compatible = "silabs,efr32bg13p632f512gm48", "silabs,efr32bg13p", "silabs,efr32", "simple-bus";
flash-controller@400e0000 {
flash0: flash@0 {
reg = <0 DT_SIZE_K(512)>;
};
};
};
};

19
dts/bindings/gpio/silabs,gecko-gpio-port.yaml Normal file
View file

@ -0,0 +1,19 @@
description: SiLabs Gecko GPIO port node
compatible: "silabs,gecko-gpio-port"
include: [gpio-controller.yaml, base.yaml]
properties:
reg:
required: true
label:
required: true
"#gpio-cells":
const: 2
gpio-cells:
- pin
- flags

20
dts/bindings/gpio/silabs,gecko-gpio.yaml Normal file
View file

@ -0,0 +1,20 @@
description: SiLabs Gecko GPIO node
compatible: "silabs,gecko-gpio"
include: base.yaml
properties:
reg:
required: true
interrupts:
required: true
label:
required: true
location-swo:
type: int
required: false
description: Serial Wire Output (SWO) PIN location

32
soc/arm/silabs_exx32/efr32bg13p/Kconfig.defconfig.efr32bg13p Normal file
View file

@ -0,0 +1,32 @@
# Silicon Labs EFR32BG13P (Blue Gecko) MCU configuration options
# Copyright (c) 2020 Piotr Mienkowski
# SPDX-License-Identifier: Apache-2.0
if GPIO
config GPIO_GECKO
default y
endif # GPIO
if I2C
config I2C_GECKO
default y
endif # I2C
if FLASH
config SOC_FLASH_GECKO
default y
endif # FLASH
if SPI
config SPI_GECKO
default y
endif # SPI

20
soc/arm/silabs_exx32/efr32bg13p/Kconfig.defconfig.series Normal file
View file

@ -0,0 +1,20 @@
# Silicon Labs EFR32BG13P (Blue Gecko) MCU configuration options
# Copyright (c) 2020 Piotr Mienkowski
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_EFR32BG13P
config SOC_SERIES
default "efr32bg13p"
config SOC_PART_NUMBER
default "EFR32BG13P632F512GM48" if SOC_PART_NUMBER_EFR32BG13P632F512GM48
config NUM_IRQS
# must be >= the highest interrupt number used
default 47
source "soc/arm/silabs_exx32/efr32bg13p/Kconfig.defconfig.efr32bg13p"
endif # SOC_SERIES_EFR32BG13P

24
soc/arm/silabs_exx32/efr32bg13p/Kconfig.series Normal file
View file

@ -0,0 +1,24 @@
# Silicon Labs EFR32BG13P (Blue Gecko) MCU
# Copyright (c) 2020 Piotr Mienkowski
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_EFR32BG13P
bool "EFR32BG13P Series MCU"
select ARM
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select CPU_HAS_ARM_MPU
select SOC_FAMILY_EXX32
select HAS_SILABS_GECKO
select HAS_SWO
select HAS_SYS_POWER_STATE_SLEEP_1
select HAS_SYS_POWER_STATE_SLEEP_2
select HAS_SYS_POWER_STATE_SLEEP_3
select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
select SOC_GECKO_CMU
select SOC_GECKO_EMU
select SOC_GECKO_GPIO
help
Enable support for EFR32BG13P Blue Gecko MCU series

11
soc/arm/silabs_exx32/efr32bg13p/Kconfig.soc Normal file
View file

@ -0,0 +1,11 @@
# Silicon Labs EFR32BG13P (Blue Gecko) MCU series
# Copyright (c) 2020 Piotr Mienkowski
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_EFR32BG13P
config SOC_PART_NUMBER_EFR32BG13P632F512GM48
bool
endif # SOC_SERIES_EFR32BG13P

37
soc/arm/silabs_exx32/efr32bg13p/dts_fixup.h Normal file
View file

@ -0,0 +1,37 @@
/*
* Copyright (c) 2020 Piotr Mienkowski
*
* SPDX-License-Identifier: Apache-2.0
*/
/* This file is a temporary workaround for mapping of the generated information
* to the current driver definitions. This will be removed when the drivers
* are modified to handle the generated information, or the mapping of
* generated data matches the driver definitions.
*/
/* SoC level DTS fixup file */
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY
#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL
#define DT_GPIO_GECKO_COMMON_NAME DT_SILABS_GECKO_GPIO_4000A400_LABEL
#define DT_GPIO_GECKO_COMMON_EVEN_IRQ DT_SILABS_GECKO_GPIO_4000A400_IRQ_GPIO_EVEN
#define DT_GPIO_GECKO_COMMON_EVEN_PRI DT_SILABS_GECKO_GPIO_4000A400_IRQ_GPIO_EVEN_PRIORITY
#define DT_GPIO_GECKO_COMMON_ODD_IRQ DT_SILABS_GECKO_GPIO_4000A400_IRQ_GPIO_ODD
#define DT_GPIO_GECKO_COMMON_ODD_PRI DT_SILABS_GECKO_GPIO_4000A400_IRQ_GPIO_ODD_PRIORITY
#define DT_GPIO_GECKO_SWO_LOCATION DT_SILABS_GECKO_GPIO_4000A400_LOCATION_SWO
#define DT_GPIO_GECKO_PORTA_NAME DT_SILABS_GECKO_GPIO_PORT_4000A000_LABEL
#define DT_GPIO_GECKO_PORTB_NAME DT_SILABS_GECKO_GPIO_PORT_4000A030_LABEL
#define DT_GPIO_GECKO_PORTC_NAME DT_SILABS_GECKO_GPIO_PORT_4000A060_LABEL
#define DT_GPIO_GECKO_PORTD_NAME DT_SILABS_GECKO_GPIO_PORT_4000A090_LABEL
#define DT_GPIO_GECKO_PORTF_NAME DT_SILABS_GECKO_GPIO_PORT_4000A0F0_LABEL
#define DT_GPIO_GECKO_PORTI_NAME DT_SILABS_GECKO_GPIO_PORT_4000A180_LABEL
#define DT_GPIO_GECKO_PORTJ_NAME DT_SILABS_GECKO_GPIO_PORT_4000A1B0_LABEL
#define DT_GPIO_GECKO_PORTK_NAME DT_SILABS_GECKO_GPIO_PORT_4000A1E0_LABEL
/* End of SoC Level DTS fixup file */

16
soc/arm/silabs_exx32/efr32bg13p/linker.ld Normal file
View file

@ -0,0 +1,16 @@
/*
* Copyright (c) 2018 Diego Sueiro
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Linker command/script file
*
* This is the linker script for both standard images.
*/
#include <autoconf.h>
#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>

30
soc/arm/silabs_exx32/efr32bg13p/soc.h Normal file
View file

@ -0,0 +1,30 @@
/*
* Copyright (c) 2020 Piotr Mienkowski
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Register access macros for the EFR32BG13P SoC
*
*/
#ifndef EFR32BG13P_SOC_H_
#define EFR32BG13P_SOC_H_
#include <sys/util.h>
#ifndef _ASMLANGUAGE
#include <em_common.h>
#include "soc_pinmap.h"
#include "../common/soc_gpio.h"
/* Add include for DTS generated information */
#include <devicetree.h>
#endif /* !_ASMLANGUAGE */
#endif /* EFR32BG13P_SOC_H_ */

28
soc/arm/silabs_exx32/efr32bg13p/soc_pinmap.h Normal file
View file

@ -0,0 +1,28 @@
/*
* Copyright (c) 2020 Piotr Mienkowski
* SPDX-License-Identifier: Apache-2.0
*/
/** @file
* @brief Silabs EFR32BG13P MCU pin definitions.
*/
#ifndef SOC_PINMAP_H_
#define SOC_PINMAP_H_
#include <em_gpio.h>
/* Serial Wire Output (SWO) */
#if (DT_GPIO_GECKO_SWO_LOCATION == 0)
#define PIN_SWO {gpioPortF, 2, gpioModePushPull, 1}
#elif (DT_GPIO_GECKO_SWO_LOCATION == 1)
#define PIN_SWO {gpioPortB, 13, gpioModePushPull, 1}
#elif (DT_GPIO_GECKO_SWO_LOCATION == 2)
#define PIN_SWO {gpioPortD, 15, gpioModePushPull, 1}
#elif (DT_GPIO_GECKO_SWO_LOCATION == 3)
#define PIN_SWO {gpioPortC, 11, gpioModePushPull, 1}
#elif (DT_GPIO_GECKO_SWO_LOCATION >= 4)
#error ("Invalid SWO pin location")
#endif
#endif /* SOC_PINMAP_H_ */

2
west.yml
View file

@ -62,7 +62,7 @@ manifest:
revision: 03c8819ac3105cc2aee295a8d330de0e665b705f
path: modules/hal/microchip
- name: hal_silabs
revision: 9a3fe1af3a14bf88c86b9cda3bf2a0921d5a97a1
revision: 0fb710f258d7ed84a75cfea40319eaf531b61d1e
path: modules/hal/silabs
- name: hal_st
revision: fa481784b3c49780f18d50bafe00390ccb62b2ec