soc: arm: xilinx_zynqmp: Use CMSIS-Core(R)
This commit updates the `xilinx_zynqmp` SoC initialisation code to use the CMSIS-Core(R) features. In addition, it also defines the Core IP revision value for the SoC as specified in the Zynq UltraScale+ Device Technical Reference Manual. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit is contained in:
parent
efd6e4c3a5
commit
4d778b789a
2 changed files with 7 additions and 13 deletions
|
@ -8,6 +8,7 @@
|
|||
#include <kernel.h>
|
||||
#include <device.h>
|
||||
#include <init.h>
|
||||
#include <arch/arm/aarch32/cortex_r/cmsis.h>
|
||||
|
||||
/**
|
||||
*
|
||||
|
@ -34,9 +35,8 @@ void z_platform_init(void)
|
|||
/*
|
||||
* Use normal exception vectors address range (0x0-0x1C).
|
||||
*/
|
||||
__asm__ volatile(
|
||||
"mrc p15, 0, r0, c1, c0, 0;" /* SCTLR */
|
||||
"bic r0, r0, #" TOSTR(HIVECS) ";" /* Clear HIVECS */
|
||||
"mcr p15, 0, r0, c1, c0, 0;"
|
||||
: : : "memory");
|
||||
unsigned int sctlr = __get_SCTLR();
|
||||
|
||||
sctlr &= ~SCTLR_V_Msk;
|
||||
__set_SCTLR(sctlr);
|
||||
}
|
||||
|
|
|
@ -8,13 +8,7 @@
|
|||
#ifndef _BOARD__H_
|
||||
#define _BOARD__H_
|
||||
|
||||
#include <sys/util.h>
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#include <device.h>
|
||||
#include <sys/util.h>
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
/* Define CMSIS configurations */
|
||||
#define __CR_REV 1U
|
||||
|
||||
#endif /* _BOARD__H_ */
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue