Adds flexspi and semc memory controllers to the i.MX RT SoC. Adds
hyperflash, qspi, and sdram external memories to the mimxrt1050_evk
board.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Previously, when !CONFI_XIP, BOOTLOADER_SRAM_SIZE was defaulted
to 16 (K), reducing the size of SRAM available for the program.
Also, though it has no effect, the value for SRAM start in the
dtsi file was incorrect.
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
To prepare to upcoming dtc v1.4.6, fix warnings in dts files.
This commit addresses the following warning:
Warning (unit_address_vs_reg): Node /soc/pin-controller has a reg
or ranges property, but no unit name
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
To prepare to upcoming dtc v1.4.6, fix warnings in dts files.
This commit addresses the following warning:
Warning (clocks_property): Missing property '#clock-cells' in node
/soc/rcc@40021000 or bad phandle (referred from
/soc/pin-controller/gpio@40011800:clocks[0])
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Adds gpio labels to all kinetis socs in preparation for refactoring the
mcux gpio driver to dts. The kl25z was missing gpio nodes altogether, so
they are added.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Create a dt-bindings/gpio.h file.
Bindings definitions are extracted from existing gpio.h.
gpio dt-bindings file is required because existing gpio.h file could
not be parsed by dts parser.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The i.MX7 SoC is a Hybrid multi-core processor composed by Single/Dual
Cortex A7 core and Single Cortex M4 core.
Zephyr was ported to run on the M4 core. In a later release, it will
also communicate with the A7 core (running Linux) via RPmsg.
The low level drivers come from NXP FreeRTOS BSP and are located at
ext/hal/nxp/imx. More details can be found at ext/hal/nxp/imx/README
The A7 core is responsible to load the M4 binary application into the
RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer,
and get the M4 out of reset.
The A7 can perform these steps at bootloader level after the Linux
system has booted.
The M4 can use up to 5 different RAMs. These are the memory mapping for
A7 and M4:
+---------------+-----------------+---------------------------+
| Memory Name | Start Address | Size |
+===============+=================+===========================+
| TCML | 0x007F8000 | 32KB |
+---------------+-----------------+---------------------------+
| TCMU | 0x20000000 | 32KB |
+---------------+-----------------+---------------------------+
| OCRAM_S | 0x20180000 | 32KB |
+---------------+-----------------+---------------------------+
| OCRAM | 0x00900000 | 128KB |
+---------------+-----------------+---------------------------+
| DDR | 0x10000000 | 256MB |
+---------------+-----------------+---------------------------+
Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
With upcoming ICs that are not in the nRF5x family, rename the flash
driver and all its dependencies from nrf5 to nrf.
Should also fix the issue introduced by f49150cab6 which broke the
assignment of the flash device due to a partial rename.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Add initial support for STM32L073xZ SOC which is not very different
from already supported STM32L072xZ.
Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
Since not all boards enable all devices, we typically have the SoC dtsi
file have a device marked with status = "disabled" and have the
board.dts explicitly enable with status = "ok". Update it so USB on
Atmel SAMD21 work this way.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Switch the SoC device tree to define a single entry per SERCOM instead
of one per mode.
Define a Device Tree binding for the SAM0 SPI and use it instead of
Kconfig for enabling / disabaling instances
Switch the Arduino Zero, Adafruit Feather M0 Basic Proto, and
Trinket M0 to use the new defintion.
Add the APA102 LED that's on the Trinket as a test.
Signed-off-by: Michael Hope <mlhx@google.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Implements interrupt driven UART for the serial driver.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Justin Watson <jwatson5@gmail.com>
The spi nodes should have #address-cells and #size-cells properties much
like i2c does. Add these missing properties.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Most STM32F429 SoCs have 6 SPIs, but STM32F429Vx SoCs only have
4 SPIs. This is one of the rare conditions where device-tree
directive /delete-node/ should be used.
Add spi5 and spi6 node to stm32f429.dtsi. Create file
stm32f429vX.dtsi to delete those nodes and document usage of
/delete-node/ directive.
Signed-off-by: Daniel Wagenknecht <wagenknecht.daniel@gmail.com>
Some stm32f4 SoCs don't support spi2, so remove spi2
device-tree node from stm32f4.dtsi file.
Signed-off-by: Daniel Wagenknecht <wagenknecht.daniel@gmail.com>
stm32f405 is not an expansion of stm32f411, since stm32f411 has more
SPIs than stm32f405.
Fix this by including stm32f401.dtsi in stm32f405.dtsi
(instead of stm32f411.dtsi).
Signed-off-by: Daniel Wagenknecht <wagenknecht.daniel@gmail.com>
Configure ccm size and address via dts. According to the DT
specification, the unit-address of a node must match the
first address specified in the reg property of the node.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
stm32f334 is not an expansion of stm32f303, since
stm32f303 has more I2C, SPI ports than stm32f303.
Fix this by including stm32f3.dtsi in stm32f334.dtsi.
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
This PR includes the required changes in order to support
conditional compilation for Armv8-M architecture. Two
variants of the Armv8-M architecture are defined:
- the Armv8-M Baseline (backwards compatible with ARMv6-M),
- the Armv8-M Mainline (backwards compatible with ARMv7-M).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
