The Atmel DFP headers define two "component typedef styles": RFO and
NTO; where the latter makes use of bit field structs to access hardware
registers.
The default component typedef style assumed by the DFP headers (i.e.
when `COMPONENT_TYPEDEF_STYLE` is not explicitly defined) is "RFO" and
this is indeed the component typedef style used throughout the Zephyr
Atmel SAM drivers, except in the particular instance which this commit
addresses.
The use of `GMAC_TA_Type` bit field struct, which is an "NTO" style
construct, is no longer possible with the latest DFPs because
conditional compilation checks for the bit field struct definitions
were added to restrict the use of such constructs to only when the
global component typedef style is set to "NTO".
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The new Atmel DFP USBHS component headers provide mode-specific
interrupt register field definitions that replace the generic
definitions (e.g. `USBHS_DEVEPTISR_RXSTPI` for a control endpoint is
now `USBHS_DEVEPTISR_CTRL_RXSTPI`).
This commit updates the Zephyr SAM USBHS driver to use the new
mode-specific interrupt register field definitions.
In addition, it maps the generic definitions to the mode-specific
definitions, as the revision A variant headers (e.g. same70a) in the
latest DFPs, at the time of writing, still provide only the generic
definitions.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Convert older DT_INST_ macro use in esp32 drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Rename DT_INST_{0,1,2}_ESPRESSIF_ESP32_UART_IRQ_0 defines to something
non-DT prefixed. This way we know which defines are one's we generate
and which ones are driver created. It should be easy enough to replace
these INST_{0,1,2}_ESPRESSIF_ESP32_UART_IRQ_0 define with DTS generated
one macros once esp32 has interrupt controller support in DTS.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert older DT_INST_ macro use in silab drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert older DT_INST_ macro use in cc13xx_cc26xx drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert older DT_INST_ macro use in stellaris drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This adds the per CPU address offset for intel_apl_adsp, so
the correct base address can be calculated under SMP.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds a rather primitive driver for use with the Intra-DSP
Communication (IDC) on the DSP on certain Intel SoCs. The IDC
generates interrupts from one core to another by writing to
certain registers. This is also being utilized as
the scheduler IPI since it can interrupt other cores.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The DSP wall clock timer on some Intel SoC is a timer driven
directly by external oscillator and is external to the CPU
core(s). It is not as fast as the internal core clock, but
provides a common and synchronized counter for all CPU cores
(which is useful for SMP).
This uses the RISCV timer as base as it is using 64-bit
counter.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The CAVS interrupt controller has different base addresses for
each CPU. When running under SMP, the driver needs to look at
the correct address for the CPU the ISR is running so interrupts
can be dispatched correctly. This adds a function to calculate
the correct base address. Note that each supported SoC may have
different offsets so per SoC config will need to added. Support
for intel_s1000 is added as an example.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The dw_ictl interrupt controller is an interrupt aggregator
supporting multi-level interrupts. Therefore, it needs to be
initialized earlier than any downstream interrupt controllers
and devices.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The cavs_ictl interrupt controller is an interrupt aggregator
supporting multi-level interrupts. Therefore, it needs to be
initialized earlier than any downstream interrupt controllers
and devices.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
It was observed that leaving the pin type configured for i2c for SDA
and SCL results in higher power consumption during standby. So we are
resetting the pin type when bringing the i2c into low power mode, and
setting it back to the correct type when exiting low power mode.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Add a dependency on the I2C resource in the TI Power module,
reconfigure the peripheral upon CPU exiting standby, and add
support for device PM.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Add a dependency on the UART resource in the TI Power module,
reconfigure the UART upon CPU exiting standby, and add support
for device PM.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Adding a dependency on the GPIO resource in the TI Power module, and
configuring the edge detection on pads as a wakeup source.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
z_vrfy_counter_get_value should check the size of memory pointed to
ticks and not the size of the pointer.
Fixes: #22431
Coverity CID :207984
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The shared irq support isn't needed in this driver. We just need to
deal with the fact that some SoCs have only a single interrupt line and
some have three interrupts. We can just ifdef that based on
DT_NUM_IRQS.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Calling device_set_power_state() with DEVICE_PM_SUSPEND_STATE then
DEVICE_PM_OFF_STATE creates an assert in nrf driver
Signed-off-by: Ismael Fillonneau <ismael.fillonneau@stimio.fr>
In the default configuration of the stm32g4 is the dual bank mode.
In dual bank mode, the flash is split into two banks with 256k each.
The erase pages have a range form 0 to 127, where each page has 2k.
If one wants to erase an area above 256k, the driver has to switch
to bank 2 befor erasing. Otherwise it will erase the page moulo 127.
Signed-off-by: Alexander Wachter <alexander.wacher@leica-geosystems.com>
This commit introduces some logs in the stm32 flash implementation.
Thith the logs it is easier to locate problems when they arrise.
Signed-off-by: Alexander Wachter <alexander.wacher@leica-geosystems.com>
A txcnt of zero prevents transmission, as transmit requires the number
of entries in the transmit fifo to be strictly less than the txcnt
value. Set the default to 1.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Convert the driver to use DT_INST_ defines, update all dependent dts,
soc and board files.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
This allows us to start using DT_NODELABEL() to access SPIMs that way,
instead of via an alias.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
uart_configure verification handler was missing what would cause a crash
if called from a user thread.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Add the get_entropy_isr API function for the gecko entropy
driver. When the function is invoked without the ENTROPY_BUSYWAIT
flag, it returns whatever data is available in a non-blocking manner.
Signed-off-by: Pooja Karanjekar <pooja.karanjekar@lemonbeat.com>
Starting a SMI write operation without waiting for completion of the
preceding SMI read operation cause the write operation to fail if
the time between the 2 operations it too short. This leads to the
PHY being in an unusable state on the MIMRT1060-EVK eval board.
In addition the value of the register was not used, as consequence
some bits were not preserved.
The solution is to do a read/modify/write to set only the
ref clock bit, which sets the PHY into 50MHz clock mode,
and keep the value of the other bits.
Signed-off-by: Armand Ciejak <armand@riedonetworks.com>
Force PHY normal operation in eth_mcux_phy_setup in case strap-in
pins configure the PHY in factory test mode.
Signed-off-by: Armand Ciejak <armand@riedonetworks.com>