drivers: eth: mcux: Write correct data into PHY_CONTROL2_REG register
Starting a SMI write operation without waiting for completion of the preceding SMI read operation cause the write operation to fail if the time between the 2 operations it too short. This leads to the PHY being in an unusable state on the MIMRT1060-EVK eval board. In addition the value of the register was not used, as consequence some bits were not preserved. The solution is to do a read/modify/write to set only the ref clock bit, which sets the PHY into 50MHz clock mode, and keep the value of the other bits. Signed-off-by: Armand Ciejak <armand@riedonetworks.com>
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parent
c168f45e60
commit
6c1afb0779
1 changed files with 18 additions and 6 deletions
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@ -48,7 +48,6 @@ enum eth_mcux_phy_state {
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eth_mcux_phy_state_read_duplex,
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eth_mcux_phy_state_wait,
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eth_mcux_phy_state_closing
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};
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static const char *
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@ -291,6 +290,10 @@ static void eth_mcux_phy_event(struct eth_context *context)
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{
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u32_t status;
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bool link_up;
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#ifdef CONFIG_SOC_SERIES_IMX_RT
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status_t res;
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u32_t ctrl2;
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#endif
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phy_duplex_t phy_duplex = kPHY_FullDuplex;
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phy_speed_t phy_speed = kPHY_Speed100M;
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@ -301,11 +304,20 @@ static void eth_mcux_phy_event(struct eth_context *context)
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switch (context->phy_state) {
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case eth_mcux_phy_state_initial:
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#ifdef CONFIG_SOC_SERIES_IMX_RT
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ENET_StartSMIRead(context->base, context->phy_addr,
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PHY_CONTROL2_REG, kENET_MiiReadValidFrame);
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ENET_StartSMIWrite(context->base, context->phy_addr,
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PHY_CONTROL2_REG, kENET_MiiWriteValidFrame,
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PHY_CTL2_REFCLK_SELECT_MASK);
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ENET_DisableInterrupts(context->base, ENET_EIR_MII_MASK);
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res = PHY_Read(context->base, context->phy_addr,
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PHY_CONTROL2_REG, &ctrl2);
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ENET_EnableInterrupts(context->base, ENET_EIR_MII_MASK);
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if (res != kStatus_Success) {
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LOG_WRN("Reading PHY reg failed (status 0x%x)", res);
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k_work_submit(&context->phy_work);
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} else {
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ctrl2 |= PHY_CTL2_REFCLK_SELECT_MASK;
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ENET_StartSMIWrite(context->base, context->phy_addr,
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PHY_CONTROL2_REG,
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kENET_MiiWriteValidFrame,
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ctrl2);
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}
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context->phy_state = eth_mcux_phy_state_reset;
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#endif
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break;
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