ipm: add driver for the CAVS DSP Intra-DSP Communication (IDC)
This adds a rather primitive driver for use with the Intra-DSP Communication (IDC) on the DSP on certain Intel SoCs. The IDC generates interrupts from one core to another by writing to certain registers. This is also being utilized as the scheduler IPI since it can interrupt other cores. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung
Anas Nashif
parent
eb7b0884ea
commit
492e890cd6
6 changed files with 329 additions and 0 deletions
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@ -175,6 +175,7 @@
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/drivers/ipm/ipm_mhu* @karl-zh
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/drivers/ipm/Kconfig.nrfx @masz-nordic @ioannisg
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/drivers/ipm/Kconfig.nrfx_ipc_channel @masz-nordic @ioannisg
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/drivers/ipm/ipm_cavs_idc* @dcpleung
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/drivers/ipm/ipm_nrfx_ipc.c @masz-nordic @ioannisg
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/drivers/ipm/ipm_nrfx_ipc.h @masz-nordic @ioannisg
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/drivers/ipm/ipm_stm32_ipcc.c @arnopo
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@ -8,4 +8,6 @@ zephyr_library_sources_ifdef(CONFIG_IPM_MHU ipm_mhu.c)
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zephyr_library_sources_ifdef(CONFIG_IPM_STM32_IPCC ipm_stm32_ipcc.c)
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zephyr_library_sources_ifdef(CONFIG_IPM_NRFX ipm_nrfx_ipc.c)
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zephyr_library_sources_if_kconfig(ipm_cavs_idc.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE ipm_handlers.c)
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@ -99,6 +99,13 @@ config IPM_STM32_IPCC_PROCID
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help
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use to define the Processor ID for IPCC access
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config IPM_CAVS_IDC
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bool "CAVS DSP Intra-DSP Communication (IDC) driver"
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depends on SMP && CAVS_ICTL
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help
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Driver for the Intra-DSP Communication (IDC) channel for
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cross SoC communications.
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module = IPM
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module-str = ipm
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source "subsys/logging/Kconfig.template.log_config"
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237
drivers/ipm/ipm_cavs_idc.c
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237
drivers/ipm/ipm_cavs_idc.c
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@ -0,0 +1,237 @@
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/*
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* Copyright (c) 2020 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <device.h>
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#include <init.h>
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#include <drivers/ipm.h>
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#include <arch/common/sys_io.h>
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#include <soc.h>
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#include "ipm_cavs_idc.h"
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#include "ipm_cavs_idc_priv.h"
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#ifdef CONFIG_SCHED_IPI_SUPPORTED
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extern void z_sched_ipi(void);
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#endif
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struct cavs_idc_data {
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ipm_callback_t cb;
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void *ctx;
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};
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static struct device DEVICE_NAME_GET(cavs_idc);
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static struct cavs_idc_data cavs_idc_device_data;
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static void cavs_idc_isr(struct device *dev)
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{
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struct cavs_idc_data *drv_data = dev->driver_data;
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u32_t i, id;
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void *ext;
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u32_t idctfc;
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u32_t curr_cpu_id = arch_curr_cpu()->id;
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#ifdef CONFIG_SCHED_IPI_SUPPORTED
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bool do_sched_ipi = false;
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#endif
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for (i = 0; i < CONFIG_MP_NUM_CPUS; i++) {
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if (i == curr_cpu_id) {
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/* skip current core */
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continue;
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}
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idctfc = idc_read(REG_IDCTFC(i), curr_cpu_id);
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if ((idctfc & REG_IDCTFC_BUSY) == 0) {
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/* No message from this core */
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continue;
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}
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/* Extract the message */
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id = idctfc & REG_IDCTFC_MSG_MASK;
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switch (id) {
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#ifdef CONFIG_SCHED_IPI_SUPPORTED
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case IPM_CAVS_IDC_MSG_SCHED_IPI_ID:
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do_sched_ipi = true;
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break;
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#endif
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default:
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if (drv_data->cb != NULL) {
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ext = UINT_TO_POINTER(
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idc_read(REG_IDCTEFC(i), curr_cpu_id) &
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REG_IDCTEFC_MSG_MASK);
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drv_data->cb(drv_data->ctx, id, ext);
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}
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break;
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}
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/* Reset busy bit by writing to it */
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idctfc |= REG_IDCTFC_BUSY;
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idc_write(REG_IDCTFC(i), curr_cpu_id, idctfc);
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}
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#ifdef CONFIG_SCHED_IPI_SUPPORTED
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if (do_sched_ipi) {
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z_sched_ipi();
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}
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#endif
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}
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static int cavs_idc_send(struct device *dev, int wait, u32_t id,
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const void *data, int size)
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{
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u32_t curr_cpu_id = arch_curr_cpu()->id;
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u32_t ext = POINTER_TO_UINT(data);
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u32_t reg;
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bool busy;
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int i;
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if ((wait != 0) || (size != 0)) {
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return -ENOTSUP;
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}
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/* Check if any core is still busy */
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busy = false;
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for (i = 0; i < CONFIG_MP_NUM_CPUS; i++) {
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if (i == curr_cpu_id) {
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/* skip current core */
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continue;
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}
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reg = idc_read(REG_IDCITC(i), curr_cpu_id);
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if ((reg & REG_IDCITC_BUSY) != 0) {
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busy = true;
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break;
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}
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}
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/* Can't send if busy */
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if (busy) {
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return -EBUSY;
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}
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id &= REG_IDCITC_MSG_MASK;
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ext &= REG_IDCIETC_MSG_MASK;
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ext |= REG_IDCIETC_DONE; /* always clear DONE bit */
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for (i = 0; i < CONFIG_MP_NUM_CPUS; i++) {
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if (i == curr_cpu_id) {
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/* skip current core */
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continue;
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}
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idc_write(REG_IDCIETC(i), curr_cpu_id, ext);
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idc_write(REG_IDCITC(i), curr_cpu_id, id | REG_IDCITC_BUSY);
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}
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return 0;
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}
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static int cavs_idc_max_data_size_get(struct device *dev)
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{
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ARG_UNUSED(dev);
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/* IDC can send an ID (of 31 bits, the header) and
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* another data of 30 bits (the extension). It cannot
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* send a whole message over. Best we can do is send
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* a 4-byte aligned pointer.
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*
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* So return 0 here for max data size.
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*/
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return 0;
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}
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static u32_t cavs_idc_max_id_val_get(struct device *dev)
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{
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ARG_UNUSED(dev);
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return IPM_CAVS_IDC_ID_MASK;
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}
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static void cavs_idc_register_callback(struct device *dev, ipm_callback_t cb,
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void *context)
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{
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struct cavs_idc_data *drv_data = dev->driver_data;
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drv_data->cb = cb;
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drv_data->ctx = context;
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}
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static int cavs_idc_set_enabled(struct device *dev, int enable)
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{
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int i, j;
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u32_t mask;
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#ifdef CONFIG_SCHED_IPI_SUPPORTED
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/* With scheduler IPI, IDC must always be enabled. */
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if (enable == 0) {
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return -ENOTSUP;
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}
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#endif
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for (i = 0; i < CONFIG_MP_NUM_CPUS; i++) {
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mask = 0;
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if (enable) {
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for (j = 0; j < CONFIG_MP_NUM_CPUS; j++) {
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if (i == j) {
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continue;
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}
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mask |= REG_IDCCTL_IDCTBIE(j);
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}
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}
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idc_write(REG_IDCCTL, i, mask);
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/* FIXME: when we have API to enable IRQ on specific core. */
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sys_set_bit(DT_CAVS_ICTL_BASE_ADDR + 0x04 +
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CAVS_ICTL_INT_CPU_OFFSET(i),
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CAVS_IRQ_NUMBER(DT_INST_0_INTEL_CAVS_IDC_IRQ_0));
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}
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return 0;
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}
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static int cavs_idc_init(struct device *dev)
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{
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IRQ_CONNECT(DT_INST_0_INTEL_CAVS_IDC_IRQ_0,
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DT_INST_0_INTEL_CAVS_IDC_IRQ_0_PRIORITY,
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cavs_idc_isr, DEVICE_GET(cavs_idc), 0);
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irq_enable(DT_INST_0_INTEL_CAVS_IDC_IRQ_0);
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return 0;
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}
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static const struct ipm_driver_api cavs_idc_driver_api = {
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.send = cavs_idc_send,
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.register_callback = cavs_idc_register_callback,
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.max_data_size_get = cavs_idc_max_data_size_get,
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.max_id_val_get = cavs_idc_max_id_val_get,
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.set_enabled = cavs_idc_set_enabled,
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};
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DEVICE_AND_API_INIT(IPM_CAVS_IDC_DEV_NAME,
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DT_INST_0_INTEL_CAVS_IDC_LABEL,
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&cavs_idc_init, &cavs_idc_device_data, NULL,
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PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&cavs_idc_driver_api);
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#ifdef CONFIG_SCHED_IPI_SUPPORTED
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static int cavs_idc_smp_init(struct device *dev)
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{
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/* Enable IDC for scheduler IPI */
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cavs_idc_set_enabled(dev, 1);
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return 0;
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}
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SYS_INIT(cavs_idc_smp_init, SMP, 0);
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#endif
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36
drivers/ipm/ipm_cavs_idc.h
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36
drivers/ipm/ipm_cavs_idc.h
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@ -0,0 +1,36 @@
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/*
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* Copyright (c) 2020 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_H_
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#define ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_H_
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/* For use with the IPM driver */
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#define IPM_CAVS_IDC_DEV_NAME cavs_idc
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#define IPM_CAVS_IDC_ID_MASK \
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(CAVS_IDC_TYPE(CAVS_IDC_TYPE_MASK) | \
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CAVS_IDC_HEADER(CAVS_IDC_HEADER_MASK))
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/* IDC message type. */
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#define CAVS_IDC_TYPE_SHIFT 24U
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#define CAVS_IDC_TYPE_MASK 0x7FU
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#define CAVS_IDC_TYPE(x) \
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(((x) & CAVS_IDC_TYPE_MASK) << CAVS_IDC_TYPE_SHIFT)
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/* IDC message header. */
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#define CAVS_IDC_HEADER_MASK 0xFFFFFFU
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#define CAVS_IDC_HEADER(x) ((x) & CAVS_IDC_HEADER_MASK)
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/* IDC message extension. */
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#define CAVS_IDC_EXTENSION_MASK 0x3FFFFFFFU
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#define CAVS_IDC_EXTENSION(x) ((x) & CAVS_IDC_EXTENSION_MASK)
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/* Scheduler IPI message (type 0x7F, header 'IPI' in ascii) */
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#define IPM_CAVS_IDC_MSG_SCHED_IPI_DATA 0
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#define IPM_CAVS_IDC_MSG_SCHED_IPI_ID \
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(CAVS_IDC_TYPE(0x7FU) | CAVS_IDC_HEADER(0x495049U))
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#endif /* ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_H_ */
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46
drivers/ipm/ipm_cavs_idc_priv.h
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46
drivers/ipm/ipm_cavs_idc_priv.h
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@ -0,0 +1,46 @@
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/*
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* Copyright (c) 2020 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_PRIV_H_
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#define ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_PRIV_H_
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#define IDC_REG_SIZE DT_INST_0_INTEL_CAVS_IDC_SIZE
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#define IDC_REG_BASE(x) \
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(DT_INST_0_INTEL_CAVS_IDC_BASE_ADDRESS + x * IDC_REG_SIZE)
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#define IDC_CPU_OFFSET 0x10
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#define REG_IDCTFC(x) (0x0 + x * IDC_CPU_OFFSET)
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#define REG_IDCTEFC(x) (0x4 + x * IDC_CPU_OFFSET)
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#define REG_IDCITC(x) (0x8 + x * IDC_CPU_OFFSET)
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#define REG_IDCIETC(x) (0xc + x * IDC_CPU_OFFSET)
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#define REG_IDCCTL 0x50
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#define REG_IDCTFC_BUSY (1 << 31)
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#define REG_IDCTFC_MSG_MASK 0x7FFFFFFF
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#define REG_IDCTEFC_MSG_MASK 0x3FFFFFFF
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#define REG_IDCITC_BUSY (1 << 31)
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#define REG_IDCITC_MSG_MASK 0x7FFFFFFF
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#define REG_IDCIETC_DONE (1 << 30)
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#define REG_IDCIETC_MSG_MASK 0x3FFFFFFF
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#define REG_IDCCTL_IDCIDIE(x) (0x100 << (x))
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#define REG_IDCCTL_IDCTBIE(x) (0x1 << (x))
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static inline u32_t idc_read(u32_t reg, u32_t core_id)
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{
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return sys_read32(IDC_REG_BASE(core_id) + reg);
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}
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static inline void idc_write(u32_t reg, u32_t core_id, u32_t val)
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{
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sys_write32(val, IDC_REG_BASE(core_id) + reg);
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}
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#endif /* ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_PRIV_H_ */
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