timer: add CAVS DSP wall clock timer for Intel SoC
The DSP wall clock timer on some Intel SoC is a timer driven directly by external oscillator and is external to the CPU core(s). It is not as fast as the internal core clock, but provides a common and synchronized counter for all CPU cores (which is useful for SMP). This uses the RISCV timer as base as it is using 64-bit counter. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
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4 changed files with 194 additions and 0 deletions
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@ -217,6 +217,7 @@
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/drivers/timer/litex_timer.c @mateusz-holenko @kgugala @pgielda
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/drivers/timer/xlnx_psttc_timer* @wjliang @stephanosio
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/drivers/timer/cc13x2_cc26x2_rtc_timer.c @vanti
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/drivers/timer/cavs_timer.c @dcpleung
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/drivers/usb/ @jfischer-phytec-iot @finikorg
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/drivers/usb/device/usb_dc_stm32.c @ydamigos @loicpoulain
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/drivers/video/ @loicpoulain
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@ -19,3 +19,4 @@ zephyr_sources_if_kconfig( litex_timer.c)
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zephyr_sources_if_kconfig( mchp_xec_rtos_timer.c)
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zephyr_sources_if_kconfig( xlnx_psttc_timer.c)
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zephyr_sources_if_kconfig( cc13x2_cc26x2_rtc_timer.c)
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zephyr_sources_if_kconfig( cavs_timer.c)
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@ -253,6 +253,17 @@ config XLNX_PSTTC_TIMER_INDEX
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help
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This is the index of TTC timer picked to provide system clock.
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config CAVS_TIMER
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bool "CAVS DSP Wall Clock Timer on Intel SoC"
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depends on CAVS_ICTL
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select TICKLESS_CAPABLE
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help
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The DSP wall clock timer is a timer driven directly by
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external oscillator and is external to the CPU core(s).
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It is not as fast as the internal core clock, but provides
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a common and synchronized counter for all CPU cores (which
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is useful for SMP).
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config SYSTEM_CLOCK_DISABLE
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bool "API to disable system clock"
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help
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181
drivers/timer/cavs_timer.c
Normal file
181
drivers/timer/cavs_timer.c
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@ -0,0 +1,181 @@
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/*
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* Copyright (c) 2020 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <drivers/timer/system_timer.h>
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#include <sys_clock.h>
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#include <spinlock.h>
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#include <arch/xtensa/xtensa_rtos.h>
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/**
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* @file
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* @brief CAVS DSP Wall Clock Timer driver
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*
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* The CAVS DSP on Intel SoC has a timer with one counter and two compare
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* registers that is external to the CPUs. This timer is accessible from
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* all available CPU cores and provides a synchronized timer under SMP.
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*/
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#define TIMER 0
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#define TIMER_IRQ DSP_WCT_IRQ(TIMER)
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#define CYC_PER_TICK (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC \
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/ CONFIG_SYS_CLOCK_TICKS_PER_SEC)
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#define MAX_CYC 0xFFFFFFFFUL
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#define MAX_TICKS ((MAX_CYC - CYC_PER_TICK) / CYC_PER_TICK)
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#define MIN_DELAY (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / 100000)
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BUILD_ASSERT(MIN_DELAY < CYC_PER_TICK);
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static struct k_spinlock lock;
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static u64_t last_count;
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static volatile struct soc_dsp_shim_regs *shim_regs =
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(volatile struct soc_dsp_shim_regs *)SOC_DSP_SHIM_REG_BASE;
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static void set_compare(u64_t time)
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{
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#if (TIMER == 0)
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/* Set compare register */
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shim_regs->dspwct0c = time;
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#elif (TIMER == 1)
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/* Set compare register */
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shim_regs->dspwct1c = time;
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#else
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#error "TIMER has to be 0 or 1!"
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#endif
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/* Arm the timer */
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shim_regs->dspwctcs |= DSP_WCT_CS_TA(TIMER);
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}
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static u64_t count(void)
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{
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return shim_regs->walclk;
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}
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static u32_t count32(void)
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{
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return shim_regs->walclk32_lo;
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}
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static void compare_isr(void *arg)
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{
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ARG_UNUSED(arg);
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u64_t curr;
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u32_t dticks;
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k_spinlock_key_t key = k_spin_lock(&lock);
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curr = count();
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#ifdef CONFIG_SMP
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/* If it has been too long since last_count,
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* this interrupt is likely the same interrupt
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* event but being processed by another CPU.
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* Since it has already been processed and
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* ticks announced, skip it.
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*/
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if ((count32() - (u32_t)last_count) < MIN_DELAY) {
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k_spin_unlock(&lock, key);
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return;
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}
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#endif
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dticks = (u32_t)((curr - last_count) / CYC_PER_TICK);
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/* Clear the triggered bit */
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shim_regs->dspwctcs |= DSP_WCT_CS_TT(TIMER);
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last_count += dticks * CYC_PER_TICK;
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#ifndef CONFIG_TICKLESS_KERNEL
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u64_t next = last_count + CYC_PER_TICK;
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if ((s64_t)(next - curr) < MIN_DELAY) {
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next += CYC_PER_TICK;
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}
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set_compare(next);
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#endif
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k_spin_unlock(&lock, key);
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z_clock_announce(dticks);
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}
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int z_clock_driver_init(struct device *device)
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{
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u64_t curr = count();
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IRQ_CONNECT(TIMER_IRQ, 0, compare_isr, 0, 0);
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set_compare(curr + CYC_PER_TICK);
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last_count = curr;
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irq_enable(TIMER_IRQ);
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return 0;
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}
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void z_clock_set_timeout(s32_t ticks, bool idle)
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{
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ARG_UNUSED(idle);
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#ifdef CONFIG_TICKLESS_KERNEL
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ticks = ticks == K_FOREVER ? MAX_TICKS : ticks;
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ticks = MAX(MIN(ticks - 1, (s32_t)MAX_TICKS), 0);
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k_spinlock_key_t key = k_spin_lock(&lock);
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u64_t curr = count();
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u64_t next;
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u32_t adj, cyc = ticks * CYC_PER_TICK;
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/* Round up to next tick boundary */
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adj = (u32_t)(curr - last_count) + (CYC_PER_TICK - 1);
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if (cyc <= MAX_CYC - adj) {
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cyc += adj;
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} else {
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cyc = MAX_CYC;
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}
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cyc = (cyc / CYC_PER_TICK) * CYC_PER_TICK;
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next = last_count + cyc;
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if (((u32_t)next - (u32_t)curr) < MIN_DELAY) {
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next += CYC_PER_TICK;
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}
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set_compare(next);
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k_spin_unlock(&lock, key);
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#endif
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}
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u32_t z_clock_elapsed(void)
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{
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if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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return 0;
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}
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k_spinlock_key_t key = k_spin_lock(&lock);
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u32_t ret = (count32() - (u32_t)last_count) / CYC_PER_TICK;
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k_spin_unlock(&lock, key);
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return ret;
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}
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u32_t z_timer_cycle_get_32(void)
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{
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return count32();
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}
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#if defined(CONFIG_SMP) && CONFIG_MP_NUM_CPUS > 1
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void smp_timer_init(void)
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{
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/* This enables the Timer 0 (or 1) interrupt for CPU n.
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*
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* FIXME: Done in this way because we don't have an API
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* to enable interrupts per CPU.
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*/
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sys_set_bit(DT_CAVS_ICTL_BASE_ADDR
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+ CAVS_ICTL_INT_CPU_OFFSET(arch_curr_cpu()->id)
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+ 0x04,
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22 + TIMER);
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irq_enable(XTENSA_IRQ_NUMBER(TIMER_IRQ));
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}
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#endif
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