This gets a little complicated as the driver could be
using PCI-E MMIO, MMIO specified by DTS, or I/O ports.
This driver doesn't use struct uart_device_config any
more.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
PCI devices on 64 bit systems can be mapped anywhere, not just in the
lower 4G of memory. Remove pointer size assumptions.
Also this removes the use of a struct uart_device_config to store the
(runtime) BAR address. That struct has other stuff in it, and the
only thing we need is the single MMIO address. It's also REALLY
confusing to have two "devconf" fields in the device storing values of
the same struct type, some fields of which are used from one of them
but some from the other!
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
When PCIe is enabled for UART, the port address is probed during
initialization and is written back into the device config struct.
However, the device config struct is supposed to be const and
read only. This results in page faults when MMU is enabled as
the struct cannot be written into. So fix this by storing port
address in device data struct if a particular UART instance is
of PCIE.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The init function returns successful even if the first
configuration function call fails. This may leave
a non-usable UART to be discoverable with
device_get_binding() which will definitely result
in lots of head scratching. So change the init function
to return properly.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The existing uart driver ns16550 did not have ISR locking that
effected IO APIC working in fixed delivery mode in SMP system
x86_64. This commit adds ISR locking mechanism using spinlock
for the interrupt related services.
The CONFIG_IPM_CONSOLE_STACK_SIZE is increased to lift
limitation of stack size experienced in IPM driver test with
this spinlock impelentation.
Fixes#23026
Signed-off-by: Jennifer Williams <jennifer.m.williams@intel.com>
Replace all occurences of BUILD_ASSERT_MSG() with BUILD_ASSERT()
as a result of merging BUILD_ASSERT() and BUILD_ASSERT_MSG().
Signed-off-by: Oleg Zhurakivskyy <oleg.zhurakivskyy@intel.com>
This reverts commit 8739517107.
Pull Request #23437 was merged by mistake with an invalid manifest.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Replace all occurences of BUILD_ASSERT_MSG() with BUILD_ASSERT()
as a result of merging BUILD_ASSERT() and BUILD_ASSERT_MSG().
Signed-off-by: Oleg Zhurakivskyy <oleg.zhurakivskyy@intel.com>
Update device data with the activated configuration, so that it
will be remembered for follow up configuration get requests.
Signed-off-by: Timo Teräs <timo.teras@iki.fi>
Change to code to use the automatically generated DT_INST_*
defines and remove the now unneeded configs and fixups.
Signed-off-by: Timo Teräs <timo.teras@iki.fi>
The sole purpose of init options has been to enable hardware flow
control on NS16750 when asked. Use the proper DTS tags for this.
Signed-off-by: Timo Teräs <timo.teras@iki.fi>
There is only one possible command, so just use if instead of switch
to avoid several MISRA-C violations and also avoid set dev_data wrongly
unused when UART_NS16550_DLF_ENABLED is defined.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The NS16550 UART driver is currently hard-coded as 8-n-1
with no flow control. The baud rate is set by what is in DTS.
This commit moves away from hard-coded and strictly DTS to
configurable using the UART configure API. Requires commit #bcb807.
Signed-off-by: Jennifer Williams <jennifer.m.williams@intel.com>
The UART configure API was added to uart.h and this commit
implements the initial framework for the configure API for
the ns16550 uart. This includes the configure() and config_get()
functions and uart device configuration structures of the uart
configure API for the ns16550.
Note this commit does not resolve the pre-existing hard-coded
8-n-1 implementation.
Signed-off-by: Jennifer Williams <jennifer.m.williams@intel.com>
Several macros were documented as deprecated but lacked the
infrastructure to produce deprecation warnings. Add the deprecation
marker, and fix the in-tree references to the deprecated spellings.
Note that one non-deprecated macro should have been deprecated, and
is, referring to a newly added line control bit.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
In some hardware,e.g. ARC HS Development kit,the
peripheral space of ns16550 only allowes WORD
access, byte acess will raise bus error.
This commit adds support for this case
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
move uart.h to drivers/uart.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
move sys_io.h to sys/sys_io.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Per guidelines, all statements should have braces around them. We do not
have a CI check for this, so a few went in unnoticed.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The per-UART configuration is boilerplate that is becoming a maintenance
nightmare as it grows. A template file is created, and instances are
created as needed by cmake at build time.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
A new function pcie_irq_enable() is added to be used in lieu of
irq_enable() when the target device is PCI(e)-attached. The function
attempts to use MSI, when configured in the kernel and supported by
the endpoint; failing that, it will verify that IRQ requested is in
fact routed to the device by the boot firmware before enabling it.
The NS16550 UART driver is updated to use pcie_irq_enable().
The PCI(e) shell is extended to dump information about wired IRQs.
The up_squared devicetree is fixed (reverted?) to IRQ5 for UART1.
The galileo enables MSI by default.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
This value always comes from DTS. No Kconfig symbol named
NS16550_REG_SHIFT ever existed.
Might've been missed in commit 603f068690 ("uart/ns16550: Use DT_ prefix
for remaining device configs").
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
The UARTs on the Apollo Lake SoCs have PLLs that feed the baud rate
generators. This patch allows a user to specify custom M/N values for
those PLLs when custom/high-speed baud rates are required.
I'm not entirely satisfied with the way the PCP values are configured,
because it requires tweaking data in both Kconfig and DeviceTree. For
the time being I've merely taken my cue from another similar feature
(the DLF register support) and have punted on figuring out the "right
way" to expose UART configuration to the application.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Previous rename from CONFIG_* to DT_* left a few remaining
CONFIG_*. So rename them manually now.
Fix#13753
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This is an application facing define, specific to this
driver, for the public uart_drv_cmd() API. Put it with
public headers.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
On behalf of : Timo Teräs <timo.teras@iki.fi>
UART_REG_ADDR_INTERVAL is SOC / chip implementation specific feature,
and its width does not always correspond to current settings for
IOPORT/non IOPORT access method.
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
1. optimize the baudrate calulation
2. For arc iot soc, the interval val is 4
3. before write any regs, the clk of uart must be enabled
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
poll_out function was returning the character that was sent. It
happens that it is always constant and the return of this functions is
never tested. Changing it to be a void function.
MISRA-C rule 17.7
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
These changes were obtained by running a script created by
Ulf Magnusson <Ulf.Magnusson@nordicsemi.no> for the following
specification:
1. Read the contents of all dts_fixup.h files in Zephyr
2. Check the left-hand side of the #define macros (i.e. the X in
#define X Y)
3. Check if that name is also the name of a Kconfig option
3.a If it is, then do nothing
3.b If it is not, then replace CONFIG_ with DT_ or add DT_ if it
has neither of these two prefixes
4. Replace the use of the changed #define in the code itself
(.c, .h, .ld)
Additionally, some tweaks had to be added to this script to catch some
of the macros used in the code in a parameterized form, e.g.:
- CONFIG_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS
- CONFIG_UART_##idx##_TX_PIN
- I2C_SBCON_##_num##_BASE_ADDR
and to prevent adding DT_ prefix to the following symbols:
- FLASH_START
- FLASH_SIZE
- SRAM_START
- SRAM_SIZE
- _ROM_ADDR
- _ROM_SIZE
- _RAM_ADDR
- _RAM_SIZE
which are surprisingly also defined in some dts_fixup.h files.
Finally, some manual corrections had to be done as well:
- name##_IRQ -> DT_##name##_IRQ in uart_stm32.c
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
irq_lock returns an unsigned int, though, several places was using
signed int. This commit fix this behaviour.
In order to avoid this error happens again, a coccinelle script was
added and can be used to check violations.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Zephyr UART drivers offer very low-level functionality. Oftentimes,
it would be useful to provide higher-level wrappers around UART
device which would offer additional functionality. However, UART
driver irq callback routine receives just a pointer to (low-level)
UART device, and it's not possible to get to a wrapper structure
(without introducing expensive external mapping structures). This
is an indirect reason why the current UARt wrappers - uart_pipe,
console - are instantiated statically just for one underlying UART
device and cannot be reused for multiple devices.
Solve this by allowing to pass an arbitrary user data to irq
callback, set by new uart_irq_callback_user_data_set() function.
Existing uart_irq_callback_set() keeps setting a callback which
will receive pointer to the device.
While public API maintains compatibility, drivers themselves need
to be updated to support arbitrary user data storage/passing (as
legacy uart_irq_callback_set() functionality is now implemented in
terms of it).
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
This extends the NS16550 driver to support 4 ports.
Also, this adds the necessary bits to enable PCI enumeration
on port 2.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
patch add clock frequency and interrupt property to uart
node in intel_s1000.dtsi. Include soc.h after types.h to
prevent build error.
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
Looks lik ARC arch snps_esmk can provide a 3rd port of this controller,
so let's add the necessary bits and pieces to get it instanciated if one
enable this port in DTS.
PCI settings are not introduced for that port as there is no known
arch/board exposing a 3rd port on PCI bus.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Fix the ns16550 uart driver and relevant SoCs accordingly.
All generic settings are now DTS based.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
TEMT is Transmitter Empty bit which is set only when the full FIFO
is empty. It makes sense to poll for THRE (Transmitter Holding
Register Empty) which is set when UART can buffer new character
for transmission (there is room in FIFO). This allows using the
FIFO in full.
Signed-off-by: Timo Teräs <timo.teras@iki.fi>
The LCR register specifies the format of the asynchronous data
communication exchange. Keep the data/stop bit and parity settings
intact during baud rate change.
Signed-off-by: Timo Teräs <timo.teras@iki.fi>
