The virtual COM port of the STlink in the Nucleo board is connected to
LPUART1, but the board was configured to use UART1 instead. For this
reason, hello world sample did not work.
In addition to that, PA2 was assigned to both LPUART1 and UART2. UART2
TX is now muxed to PA14.
Signed-off-by: Martin Jaeger <17674105+martinjaeger@users.noreply.github.com>
On nucleo_g071rb, flashing using pyocd requested to hold reset button
during flashing operation.
Using newly available pyocd arguments this is no more needed and
nucleo_g071rb can now be flashed in a fully automated way.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit adds support for the on-board flash MX25R8035F that is
directly connected to the efr32fg soc.
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
This commit adds support for the on-board flash MX25R8035F that is
directly connected to the efr32mg soc.
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
Add board support files for mimxrt1010_evk, the development board for
i.MXRT1010 (CM7) SoC.
- Add pinmux, dts and doc.
- Tested samples: hello_world, philosophers, synchronization,
basic/blinky, basic/button.
Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
Add support for specifying PWM flags for the NXP Kinetis FlexTimer
(FTM) PWM driver through the device tree.
All in-tree clients of this PWM controller are active-low LEDs.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The SRAM address and size are currently available as both
DT_SRAM_{BASE_ADDRESS,SIZE} and as CONFIG_SRAM_{BASE_ADDRESS,SIZE} (via
the Kconfig preprocessor).
Use the CONFIG_SRAM_* versions everywhere, and remove generation of the
DT_SRAM_* versions from gen_defines.py.
The Kconfig symbols currently depend on 'ARC || ARM || NIOS2 || X86'.
Not sure why, so I removed it.
It looks like no configuration files set CONFIG_SRAM_* at the moment, so
another option might be to use the DT_* symbols everywhere instead. Some
Kconfig.defconfig.series files add defaults to them though.
Also improve the help texts for CONFIG_SRAM_* to say that they normally
come from devicetree rather than configuration files.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This commit removes the ignore tags for the tests that work after the
changes in the PR #20267.
In the future, this ignored testing tag list will be further reduced
as critical bugs for the qemu_cortex_r5 platform are addressed
(see #20217).
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The Xilinx ZynqMP SoC embeds both Cortex-R "RPU" and Cortex-A "APU"
cores.
Since the current Zephyr architecture cannot support AMP of Cortex-R
and Cortex-A within the same project, the RPU and APU should be
considered separate platforms and handled accordingly.
This commit re-purposes the SOC_XILINX_ZYNQMP symbol as a helper symbol
indicating that Xilinx ZynqMP SoC is used, and adds a new symbol,
SOC_XILINX_ZYNQMP_RPU, for specifying the actual build target platform.
When Cortex-A support is added in the future, SOC_XILINX_ZYNQMP_APU
symbol should be added and used to conditionally handle APU-specific
code.
For more details, refer to the issue #20217.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
ZynqMP SoC embeds two separate processor types: Cortex-R for RPU and
Cortex-A for APU.
Since the current Zephyr architecture cannot support AMP of Cortex-R
and Cortex-A within one project, the RPU and APU should be considered
separate platforms.
This commit relocates the device tree nodes that are not common between
RPU and APU to a separate dtsi file (zynqmp_rpu.dtsi).
When Cortex-A53 APU support is added in the future, an additional dtsi
file (zynqmp_apu.dtsi) for specifying the APU device tree should be
added.
For more details, refer to the issue #20217.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Based on this commit
| commit dd6186f299
| Author: Bobby Noelte <b0661n0e17e@gmail.com>
| Date: Sat Sep 30 18:24:46 2017 +0200
|
| boards: nucleo_f030r8: reduce kernel memory usage
|
| nucleo_f030r8 fails in CI because applications need
| more RAM.
|
| Reduce kernel memory used by stacks and ISR vector table.
|
| Fixes#3923
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Enable the NXP FTM PWM outputs in the board pinmux files based on the
DT_INST_* defines instead of CONFIG_PWM_* to match the pwm_mcux_ftm
driver.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rename the NXP FTM instances in the KE1xF SoC to PWM to match the
other SoCs/boards using the FlexTimer as PWM generator.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
At the moment we have different images for
for Nucleo F030R8 and Nucleo F070RB boards,
the images have the same pixel size but different
file formats, e.g:
NAMES="f030r8 f070rb"
for i in $NAMES; do
file boards/arm/nucleo_$i/doc/img/nucleo_$i.jpg;
done
boards/arm/nucleo_f030r8/doc/img/nucleo_f030r8.jpg: JPEG image
data, Exif standard: [TIFF image data, little-endian,
direntries=0], baseline, precision 8, 500x367, frames 3
boards/arm/nucleo_f070rb/doc/img/nucleo_f070rb.jpg: JPEG image
data, JFIF standard 1.01, aspect ratio, density 1x1,
segment length 16, progressive, precision 8, 500x367, frames 3
The nucleo_f030r8.jpg file is larger:
for i in $NAMES; do
ls -1 -sh boards/arm/nucleo_$i/doc/img/nucleo_$i.jpg;
done
128K boards/arm/nucleo_f030r8/doc/img/nucleo_f030r8.jpg
40K boards/arm/nucleo_f070rb/doc/img/nucleo_f070rb.jpg
Applying simultaneous black/white threshold to the images
and comparing them with imagemagick tools shows that
the images have no significant difference.
for i in $NAMES; do
convert boards/arm/nucleo_$i/doc/img/nucleo_$i.jpg \
-threshold 80% /tmp/$i.png;
done
compare $(for i in $NAMES; do echo -n "/tmp/$i.png "; done) \
-compose src /tmp/diff.png
See also 'boards: arm: unify Nucleo-64 boards connectors image'
(https://github.com/zephyrproject-rtos/zephyr/pull/15926).
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
This patchset enables USART3 on the 96Boards STM32 Mezzanine.
It is broken out to J10 Grove Connector.
Changes:
- Enabled USART3 in board dts.
- Updated board index.rst with uart pinouts.
- soc dtsi: enabled usart3.
Test: Tested USART3 as console at 115200 baud
Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
Add Add STM32_OSPEEDR_VERY_HIGH_SPEED flag for SPI1_SCK to function
properly. This is needed for the proper communication with the LoRa
modem. Without this flag, the received data is mangled when burst
read is performed.
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
This adds support for the EC (embedded controller) on a Google
reference board with codename "kukui". This board uses the STM32F098RC
chip. We built an application for the board and verified UART
functionality on the board.
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Setup manual was modified, added detailed description how to launch
and program board, added more photos for better understanding
of the setup process.
Signed-off-by: Maksim Masalski <maksim.masalski@intel.com>
Add the green LED on the back of the reel_board to the device tree and
add PWM support for the front RGB LED.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add at86rf233 dts binding to enable IEEE 802.15.4 driver. The driver is
managed by sercom-4 at chip level.
see: SAM-R21_G.pdf section: 5.2 Internal Multiplexed Signals
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
MX25R64 supports maximum 33 MHz clock for READ operations in
high-performance mode. The previous 80 MHz speed should have been
8 MHz and was for DSPI/QSPI operations.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
This commit removes any ignored testing tags for working tests.
In the future, this ignored testing tag list will be further reduced
as critical bugs for the qemu_cortex_r5 platform are addressed
(see #20217).
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit adds a temporary hack to support CI testing of the
qemu_cortex_r5 platform.
The Xilinx QEMU, required to run the tests for this platform, is
currently not available in the default SDK for CI (version 0.10.3) and
attempting to run any tests with the AArch64 QEMU included in this SDK
will cause failures (see #20217).
Since the latest SDK (version 0.11.0-alpha-8) has been added to the CI
image to allow initial testing, this hack automatically detects this
and uses the Xilinx QEMU for testing the qemu_cortex_r5 platform.
When the Zephyr SDK 0.11.0 is available as the default SDK for CI in
the future, this commit should be reverted.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit modifies the 'qemu_cortex_r5' board qemu emulation to use
the arm-generic-fdt machine with the Xilinx-provided zcu102 device tree
instead of the hard-coded xlnx-zcu102 machine, which is very primitive
and cannot properly emulate the Cortex-R5 RPU of ZynqMP.
The QEMU zcu102 FDT (fdt-single_arch-zcu102-arm.dtb) in this commit was
generated from the v2019.2 release of the Xilinx/qemu-devicetrees.
Zephyr SDK version 0.11 Alpha 4 or above is required to use this, as
arm-generic-fdt is supported only by the Xilinx QEMU fork which was
added to the Zephyr SDK in the version 0.11 Alpha 4.
For more details, refer to the issue #20217.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Add support for the ST STM32G0316-DISCO development board. This board
features an ST STM32G031J6 MCU on a breakable SO8 to DIL8 module, a user
LED and a button.
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
SOC_FAMILY_NRF has no prompt. Assignments in configuration files have no
effect on symbols without prompts. A prompt means the symbol is
user-configurable.
SOC_FAMILY_NRF is instead enabled indirectly through being selected by
other symbols.
Detected through some work-in-progress improved error checking.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This patch enables SPI4 on the 96Boards STM32 Sensors Mezzanine.
SPI4 has been broken out to a Grove Connector on the board.
Changes:
- Updated board dts to enable spi4
- Updated board Kconfig
- Updated board documentation
- Update board pinmux
- Updated stm32f4 pinmux header file
- Updated stm32f401 dtsi
- Updated stm32f4 defconfig to enable PORTE GPIO
- Added board to spi_loopback test
Test: spi_loopback test passed
Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
Low frequency and high frequency clocks had separate devices
while they are actually handled by single peripheral with single
interrupt. The split was done probably because opaque subsys
argument in the API was used for other purposes and there was
no way to pass the information which clock should be controlled.
Implementation changes some time ago and subsys parameter was
no longer used. It now can be used to indicate which clock should
be controlled.
Change become necessary when nrf5340 is taken into account where
there are more clocks and current approach would lead to create
multiple devices - mess.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Renames the lpc usart shim driver to more accurately reflect the
flexcomm hardware IP and to prepare for instantiating it on an SoC
outside the LPC family.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Configure as GPIOs pins that by default are not GPIOs
Enable pinmux for port F
Enable ADC, PWM drivers by default, but keep SPI disabled.
Swap I2C instances since I2C0 is multiplexed with UART2
Select VTR3 as 1.8V
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
EEPROM drivers that support STM32L1 have been tested
on 96b_wistrio boards.
EEPROM support is added to the board documentation.
Signed-off-by: Kwon Tae-young <tykwon@m2i.co.kr>
