NPCX series ROM code changes the chip basic setting by firmware binary
header for loading the firmware from flash to RAM. Add the following to
improve the ec firmware header setting:
- Move the ECST which generates the firmware binary header to NPCX
common folder. All the following NPCX series chips can use this.
- Add ecst setting option in Kconfig.
Signed-off-by: Yuval Peress <peress@chromium.org>
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Z_ITERABLE_SECTION_ROM symbols were empty, meaning
that those symbols were not taking place in the linker script.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This CL limits the compiler to consider the eSPI/LPC host wake-up
functions, such as npcx_host_disable_access_interrupt and
npcx_host_disable_access_interrupt, only if eSPI bus module is selected.
Otherwise, we will encounter compiler errors if the communication
between host and ec is via SPI, not eSPI/LPC bus.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This commit fixes the ADC driver flow. And add internal
reference voltage to ADC driver API. And correct the
data buffer that only need to store raw data.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Set TRACE_MODE to asynchronous and enable trace output pin.
Add soc_config.c in stm32 soc direcotry.
Fixes#34342
Signed-off-by: Andrés Manelli <am@toroid.io>
NPCX clock has some limitations about the frequency range &
synchronization between core clock & other clocks. Add build assert to
check whether NPCX clock setting correct. This also fixed soc_clock.h
to consist with datasheet.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Cleanup along the same lines as the last change to APL/up_squared.
Make sure all hardware configuration is at the board level where it
belongs and not in the soc, don't play games with defaulting timer
drivers. Unify the configuration where possible and make it clearer
which setting goes with which driver.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The addition of a timer driver made a messy situation worse. Move
board-level configuration like clock rates and dividers into the board
and don't try to default it in the soc. Make it clear which kconfig
goes with which driver. Likewise don't try to do driver selection in
the soc, the board (or app) is in a better position to choose.
Also clean up and better unify the up_squared 32/64 bit settings.
Really only CONFIG_BOARD_NAME needs to care about the difference
between these devices.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Add QEMU board with single core ARCv3 HS6x 64 bit CPU
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Add the missing .cached section on cAVS 2.0 and 2.5 to fix
compiler warnings.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
PLATFORM_RESET_MHE_AT_BOOT and
PLATFORM_DISABLE_L2CACHE_AT_BOOT have to be defined on cAVS 1.8
too, without them secondary cores cannot be used.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
uncache_to_cache(), cache_to_uncache() and is_uncached() macros
are currently unused in Zephyr, besides the former two are
dangerous because they add and subtract an offset instead of
masking and unmasking a bit, which can lead to wrong addresses
if applied repeatedly. Remove these macros for now, we can
re-add them later if needed in their fixed versions.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Currently only cAVS 1.5 Kconfig selects ARCH_HAS_COHERENCE,
which is wrong. cAVS 1.8, 2.0 and 2.5 have to select it too.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Added support for GPIO driver for Intel Elkhart Lake
board.
The GPIO driver will support pin value read/write operations,
pin direction and interrupt configuration. ACPI enumeration
support and support for different GPIO communities is also
present.
Verified on ehl_crb.
Signed-off-by: U Divya <u.divya@intel.com>
spi1 and i2c0 share peripheral ID number 3.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
UART0, TWI0, and SPI0 have different peripheral IDs (2, 3, and 4
respectively) on this SoC and therefore should not be mutually
exclusive to use.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
There is a choice to log btmon logs over UART or RTT.
You can choose number of RTT buffer, set its name and size.
Replaced CONFIG_BT_DEBUG_MONITOR with CONFIG_BT_DEBUG_MONITOR_UART
for UART usage and CONFIG_BT_DEBUG_MONITOR_RTT for RTT.
Signed-off-by: Magdalena Kasenberg <magdalena.kasenberg@codecoup.pl>
SMP support on cAVS is implemented by using uncached addresses
for all writable data sections except for stack, i.e. for .data,
.bss and some other specialised ones. So far that has been
implemented for cAVS 1.5. This patch does the same for cAVS 1.8.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
According to RM0041.pdf clock tree for stm32f100xx devices is
different from both STM32F10X density and connectivity lines devices,
but is a combination of both.
Rework symbols definitions so that STM32F100xx is neither of those
and uses:
- CLOCK_STM32_PLL_MULTIPLIER as on SOC_STM32F10X_DENSITY_DEVICE
- CLOCK_STM32_PLL_PREDIV1 as on SOC_STM32F10X_CONNECTIVITY_LINE_...
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Fixes an issue with mcuboot where the SoC will freeze when the dpll is
disabled since `atmel_samd_init` was already run in the bootloader.
Signed-off-by: Abram Early <abram.early@gmail.com>
We need to clear interrupt status, before we enable the interrupt.
So I let ite_intc_isr_clear() to be global function.
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Allow SMP processing for SOF on ADSP. Note, that after this
SOF will build with SMP support enabled on all cAVS versions,
but secondary cores will remain disabled unless an SMP
topology is loaded by the host.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
With SOF secondary cores are booted later at run-time instead
of the traditional simultaneous booting of all the cores.
Adjust arch_start_cpu() to make that possible.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
To disable the IDC interrupt on the interrupt controller a bit
must be set in the MSD register instead of clearing the bit in
the MCD register, which has no effect.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
irq_enable() should be called with the composite IRQ code as its
argument, not just the Xtensa proper part of it.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
BT support requires lots of PROVIDE calls that cannot
be added into this linker file. All necessary includes
were moved into hal module to proper handled as needed.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
During configuring the low-voltage power supply of IO pads, the npcx
GPIO driver needs to set the related PORTx_OUT_TYPE bit to 1, i.e.
select to 'Open Drain IO type', also. This CL provides a mechanism that
configuring these bits via 'def-lvol-io-list' node automatically in case
the flag of gpios that have been configured to low-voltage power supply
doesn't contain GPIO_OPEN_DRAIN.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Move the STM32F0 specific ram vector table sections into a dedicated
linker snippet included by the new `SRAM_VECTOR_TABLE` symbol.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add a new Kconfig symbol that explicitly controls whether the vector
table should be placed in RAM. This eliminates the side effect of
`IS_BOOTLOADER` controlling vector table location. Making the condition
a positive assertion also allows the config to be used in CMakeLists
conditions (`zephyr_linker_sources_ifdef()`, etc).
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
