Now that we have shim defined for each platform, no need to support all
platforms within the same struct. This change exposes some bugs where we
were relying on the old structure and calling into unused register space
for example for SRAM initialization on some SoC generations.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Cleanup soc.h and move interrupt defines into own headers. Rename some
of the defines for ACE to have a unified namespace.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The DW register block was duplicated into the ACE header while we had
the same thing in the driver. Move everything to the driver as the first
step with further improvements planned on top of this.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The file uses architecture specific IRQ calls without including
appropriate headers.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
sys/util.h is not needed by soc.h, and was causing troubles with
redefinitions of ARRAY_SIZE (from HAL) in CI.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some files were using macros defined in sys/util.h without including it,
e.g. for MHZ().
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some SoCs define stuff in soc.h, used in drivers or SoC code. Note that
soc.h is not introduced here as a catch-all header. soc.h optimizations
or removal is out of the scope of this patch.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some files make use of NMI API (NMI_INIT()) without including the
appropriate headers.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
With the incoming removal of kernel.h/types.h from init.h, lots of files
start to show compile errors because they relied on indirect
definitions, including errno.h.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some files make use of CMSIS APIs/definitions without explicitely
including CMSIS headers.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The sys* ops like sys_clear_bit are indirectly included via arch CPU
header. Other stuff like find_msb_set end up included via this header as
well.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Do FW communication outside of memory window setup to accomodate for
additional IPC commands and headers.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This is not guaranteed to match the physical layout of the memory, so
get them individually based on node label.
For initialization, use bbzero.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Some windows might need to be set as writtable, so add a flag read-only
to DTS bindings which is set to true for all windows right now. This can
be set to false where needed.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This was all done as part of the soc and called from the soc. Define
this type of console under drivers/console and use it in the SoCs
supporting that via SYS_INIT instead of calling the console code
directly.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Instead of just declaring the memory window register in DTS and have
everything else all over the place (headers, Kconfig, etc.) this change
defines the memory window instances in DTS and uses the device model to
initialize the windows. Code is still part of the SoC, given that we do
not have a driver subsystem suitable for this type of device yet.
Move FW status to own workflow and separate from window setup.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Clean up and refactor x86 SoC headers in preparation of adding
new platforms in the future.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
add common mec_gpio.h to allow access to common gpio_regs
structure for both mec15xx and mec17xx, used in pinctrl driver
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
This is an AArch64 board. We also add RK3399 SoC support,
as well as a very simple Synopsys 8250dw UART driver.
Signed-off-by: Henri Xavier <datacomos@huawei.com>
The Inter-DSP Communication (IDC) is being used to send
sched IPI to other CPU cores. When a core receives an IDC,
it needs to ACK it by clearing the BUSY bit in TDR, and also
needs to the BUSY bit in TDA to signal done after processing.
These two steps are needed to complete one IDC message.
If we do only one (and not both), the other side will not be
able to send another IDC message as the hardware still thinks
the core is processing the IDC message (and thus will not send
another one). So add the step to clear the BUSY bit in TDA so
we can have multiple sched IPIs.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit updates the intel_adsp build script to invoke the
`fix_elf_addrs.py` Python script using the Python executable detected
by the build system.
This ensures that the script is run using the same Python installation
used by the Zephyr build system.
Signed-off-by: Stephanos Ioannidis <stephanos.ioannidis@nordicsemi.no>
The platform has support for pinctrl, but it is selecting both pinmux
and pinctrl. Legacy applications requiring pinmux should enable it
manually.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
() The check for whether the CPU is already active before halting
was incorrect. It should only fail if the CPU is not active,
but the CHECKIF() conditional was inverted. So invert it.
() Also need to set the entry in the bookkeeping array to false
once a CPU is considered powered down.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The conditionals to check if the CPA bit is already set or cleared
are incorrect. This results in the code always asserting. So fix
those.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add options about Internal RC(IRC) oscillator.
- GD32_HAS_IRC_32K/40K indicates IRC types.
- GD32_LOW_SPEED_IRC_FREQUENCY is the numeric value of frequency
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Linker scripts contains a `.last_section` section that is placed in rom
region as NOLOAD for the purpose of retrieve the actual number of bytes
contained in the image. See d85efe0b10
However, a previous section may cause the location counter to be
incremented for alignment purposes. This can result in the size of the
image to be 0x10FA but location counter to be 0x1100 because it has been
aligned for next section placement.
Therefore, two new Kconfig settings are introduced.
Those settings request the linker to will write a pattern in
`.last_section`. Together with removing NOLOAD and writing a patten to
the section then we ensure that data is written after alignment of
location counter, and thereby forces the image size to be in sync with
the location counter.
The default pattern used will be 0xE015 (end of last section).
Some systems may fill up the flash completely, or simply write data at
the end of the flash, which in both cases can result in overflow.
Therefore, the new settings can be disabled.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Allow building for nRF non-secure and TF-M enabled without having the
platform partition enabled.
In this configuration the soc_secure functions have no valid
implementation, leave it as a compilation error if the application
includes the functions.
Add missing dependency on soc_secure functions being available for
SOC_HFXO_CAP_INTERNAL configuration.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Make Kconfig produce an error when GPIOs cannot be forwarded in the
current configuration instead of silently excluding the forwarding.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
It's useful for RAMABLE_REGION to have a uniform name when
CODE_DATA_RELOCATION is supported, because otherwise the build system
needs to be aware of how the region name differs between architectures.
Since architectures tend to prefer one of 'SRAM' or 'RAM' for that
region, prefer to use 'RAM' as the more general term.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
This will trigger link commit immediately after start
to fix hda start flow.
Applies to link out only.
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
On ACE, there is another layer of interrupt masking where
this masks, in addition to the DesignWare controllers.
So we need to un-mask during IPC init or else we are not
going to get any host IPCs.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Zephyr encodes multi-level interrupts in a certain way, and
the driver is not utilizing the encoding correctly. So fix
it.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit removes the `k_mem_pool` section for the memory pool API,
which was removed in the v2.5.0 release.
Signed-off-by: Stephanos Ioannidis <stephanos.ioannidis@nordicsemi.no>
console can't handle the amount of data coming from many tests, so
introduce a delay beween testcases.
Use ZTEST_TEST_DELAY_MS to delay test execution.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
...Z_THREAD_STACK_BUFFER.
This is currently a symbolic change as Z_THREAD_STACK_BUFFER
is simply an alias to Z_KERNEL_STACK_BUFFER without userspace,
and Xtensa does not support userspace at the moment.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
