Commit graph

5973 commits

Author SHA1 Message Date
Daniel DeGrasse
1cee7be552 drivers: pinctrl: Enable pinctrl for RT11xx series
RT11xx series has similar pin configuration peripheral to RT10xx, with
some differences in register layout. Create new pinctrl definition
header file, and reuse existing driver code for RT10xx.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-25 15:47:54 -05:00
Daniel DeGrasse
3a6919e3aa drivers: pinctrl: update rt pinctrl to support GPR register
iMX.RT parts use a GPR register for some pinmux settings. Update pinctrl
driver to support this GPR register definition.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-25 15:47:54 -05:00
Jaska Uimonen
b22d8bfc46 soc/intel_asdp: take ownership of i2s and dmic registers
Take ownership of i2s and dmic registers as otherwise they are
not accessible.

Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
2022-03-25 14:40:31 -04:00
Daniel DeGrasse
da40ffb4a8 soc: enable noncacheable OCRAM region for nxp iMX.RT
OCRAM can be used for DMA, and in this case it should be marked as
noncacheable. Add KConfig symbol and appropriate linker scripts to
enable OCRAM region to be defined as noncacheable, and initialized with
data from flash at boot.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-25 10:40:59 +01:00
Gerson Fernando Budke
0521aa0fbc drivers: pinmux: Drop sam0 pinmux in favor of pinctrl
Drop sam0 pinmux driver and all related entries in favor to use new
pinctrl API.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2022-03-24 15:45:37 -07:00
Gerson Fernando Budke
c1ad9c39e4 drivers: pinctrl: Drop obsolete atmel sam/sam0 entries
Drop all old and obsolete atmel sam/sam0 pinctrl entries.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2022-03-24 15:45:37 -07:00
Gerson Fernando Budke
10aa57857d drivers: pinctrl: Update Atmel sam0 driver to new API
This update current Atmel sam0 pinctrl initiative to current Zephyr
pinctrl API. It update current devicetree bindings and add the sam0
pinctrl driver.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2022-03-24 15:45:37 -07:00
Gerson Fernando Budke
cb201430cf drivers: pinctrl: Update atmel sam driver to new api
This update current Atmel sam pinctrl initiative to current Zephyr
pinctrl API. It update current devicetree bindings and add the sam
pinctrl driver.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2022-03-24 15:45:37 -07:00
Alexey Brodkin
35f53b8456 ARC: QEMU: Add the second UART support
This makes the second UART of ARC QEMU's "virt" platfrom available
in Zephyr. But please note to get it used corresponding change needs
to be applied to QEMU itself, see:
https://github.com/foss-for-synopsys-dwc-arc-processors/qemu/pull/62

PR for Zephyr's SDK-NG is posted here:
https://github.com/zephyrproject-rtos/sdk-ng/pull/422

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2022-03-24 08:27:40 -04:00
Filip Kokosinski
8388bb7c24 soc: riscv: sifive-freedom: fix SYS_CLOCK_HW_CYCLES_PER_SEC value
This commit fixes the default value of SYS_CLOCK_HW_CYCLES_PER_SEC
option. The previous value of 32768 is not consistent with the
documentation of FE310 SoC. Only FE310-based boards rely on the default
value of this option; other boards from the Freedom series define it
themselves.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2022-03-24 10:46:34 +01:00
Filip Kokosinski
38f38e0be8 boards: FE310-based boards: transition to pinctrl driver
This commit makes the transition from the pinmux driver to the pinctrl
driver. It also modifies UART, SPI and I2C drivers used in FE310-based
boards to use the new pinctrl API.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2022-03-24 10:46:34 +01:00
Filip Kokosinski
a5cc185b9b drivers: pinctrl: add SiFive pinctrl driver
Add a pinctrl driver used in FE310-based boards.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2022-03-24 10:46:34 +01:00
Yuval Peress
2374544bcc posix: Select CPU_HAS_FPU for POSIX arch
Add the ability to run native-posix tests using the FPU.

Signed-off-by: Yuval Peress <peress@google.com>
2022-03-24 10:44:38 +01:00
Mulin Chao
8a4013b2e1 drivers: adc: Set correct interrupt type and remove spurious interrupts
In npcx adc driver, we select 'Scan' (Multiple Channels Operation Mode)
mode by default. It means that selected channels in ADCCS will be
converted automatically. Then, read the measured data from CHNDAT
registers if EOCCEV (Event is set after all selected channels are
converted.) flag in ADCSTS is set.

But we enable the wrong interrupt type, INTECEN, during adc
initialization. Ec will send the interrupt after each channel in ADCCS
is converted. It has no harm to the current driver since the driver
reads all selected channels and turns off ADC converter only after
EOCCEV is set in ISR. But it does generate spurious interrupts.

This CL enables the correct interrupt type, INTECCEN, during adc
initialization. Ec only sends the interrupt after all of channels in
ADCCS are converted.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2022-03-24 10:43:54 +01:00
Matthias Fend
a3f7a01ac8 soc: mimx8ml8_m7: add .resource_table section to linker script
This is required to include the resource table in the build output. The
Linux remoteproc framework explicitly looks for this section while loading
the elf and may complain if the resource table is missing.

Signed-off-by: Matthias Fend <matthias.fend@emfend.at>
2022-03-24 10:41:39 +01:00
Dylan Hung
a24ab24322 soc: arm: Add Aspeed ast10x0 series support
Aspeed ast10x0 series SoCs contain a ARM Cortex-M4F processor.  This
processor operates at 200MHz and executes on SRAM.

This patch adds support for ast1030 as the first SoC of this series
which is targeted but not limited at the bridge IC in a server system.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I668af1ff8a36a05da791c3329ae08f5ae712bdd4
2022-03-23 12:50:28 +01:00
Daniel DeGrasse
8979f87c6e soc: disable pinmux driver for nxp kinetis SOCs
disable pinmux driver for nxp kinetis SOCs, since all boards use pinctrl

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-22 12:36:04 +01:00
Daniel DeGrasse
bde2bbed6f soc: kinetis: do not redefine PORT_PCR_ODE for KW24/22 series
KW24 and KW22 series support open drain pins, while rest of kinetis KW
SOCs do not. Don't redefine PORT_PCR_ODE for these SOCs

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-22 12:36:04 +01:00
Ruibin Chang
4b75cf8f47 ITE drivers/interrupt_controller: add wuc interface
Add wakeup controller interface for ITE it8xxx2 chip.

Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
2022-03-21 16:35:03 -07:00
Nazar Kazakov
f483b1bc4c everywhere: fix typos
Fix a lot of typos

Signed-off-by: Nazar Kazakov <nazar.kazakov.work@gmail.com>
2022-03-18 13:24:08 -04:00
Andrzej Głąbek
a5234f3647 soc_nrf_common: Extend and rename the NRF_DT_ENSURE_PINS_ASSIGNED macro
Extend the macro with checks for DT properties related to pin
assignments that are defined but would be ignored, depending on
whether PINCTRL is enabled or not, what presumably indicates
a resulting configuration different from what the user expects.

Add also a possibility to indicate that the pinctrl-1 property
should not be checked because the caller does not support the
sleep state.

Rename the macro so that its name better reflects its function.
Update accordingly all drivers that use it.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2022-03-18 16:26:21 +01:00
Joakim Andersson
6ac77d6a4e soc: nordic_nrf: Add query items for HW peripheral CTRLAP
Add Kconfig items that can be used to query if the current SoC
support the HW peripheral CTRLAP.

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2022-03-18 10:37:31 +01:00
Jay Vasanth
9a67af9008 soc: arm: microchip_mec: Remove unused soc_espi_v2.h
Remove unused MEC172x header file soc_espi_v2.h

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-03-18 10:22:52 +01:00
Guy Morand
965d41a195 soc: arm: nxp_imx: Select MCUX_IGPIO driver for mimx8mm6
This automatically enables the gpio_mcux_igpio driver when gpio is
enabled on this platform.

Signed-off-by: Guy Morand <guy.morand@bytesatwork.ch>
2022-03-17 16:32:58 -05:00
Tim Lin
0cc2cf2499 ITE: chip_chipregs: Add the declaration of register bit
Add the declaration of register bit.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2022-03-17 16:31:36 -05:00
Tim Lin
f2c42663b4 ITE: drivers/i2c: I2C driver divided into two compatibles
As mentioned in #42882, the I2C of IT8XXX2 is designed for two different
IP blocks, so this PR divides this I2C driver into two compatibles.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2022-03-17 15:53:34 -05:00
Sylvio Alves
30c45b0dae intc: esp32c3: use source as interrupt value
Using IRQ as source for interrupt values can
fail when installing irq_connect_dynamic, as
IRQ can previously be enabled. This updates
the logic to use source map and allows
default irq_enable() and irq_disable() to call
esp32c3 interrupt allocator implementation.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-03-17 11:40:31 +01:00
William Patty
01ebcda726 soc: riscv: riscv-privilege: add support for mtvec vectored mode
Enable support for mtvec vectored mode for privilege SOCs. This
is an optional feature and takes up addtional code space. It is
necessary to support this feature for privilege SOCs that only
support mtvec vectored mode.

Change was tested on qemu_riscv32 and qemu_riscv64 boards with
CONFIG_RISCV_MTVEC_VECTORED_MODE enabled.

Signed-off-by: William Patty <wpatty24@gmail.com>
2022-03-17 11:12:32 +01:00
Rander Wang
8d821a587f soc: intel_adsp: update UUIDs of BRNGUP and BASEFW
The SOF ipc4 driver and Windows driver can't work with
SOF built with zephyr and ipc4 configuration on cAVS 1.8+
platforms. Because the UUIDs of BRNGUP and BASEFW are
copied from APL (cAVS 1.5), which is incompatible with
cAVS 1.8+ platforms.

This patch updates BRNGUP and BASEFW to use cAVS 1.8+ UUIDs.

Signed-off-by: Chao Song <chao.song@linux.intel.com>
Signed-off-by: Rander Wang <rander.wang@intel.com>
2022-03-16 13:46:00 -04:00
Gerard Marull-Paretas
5a71eeb35c pm: policy: move constraints to policy API
The pm_constraint_* APIs were effectively used by the policy manager
only. This patch renames the API to the policy namespace and makes its
naming more explicit:

- pm_constraint_set -> pm_policy_state_lock_get()
- pm_constraint_release -> pm_policy_state_lock_put()
- pm_constraint_get -> pm_policy_state_lock_is_active()

The reason for these changes is that constraints can be of many types:
allow/disallow states, impose latency requirements, etc. The new naming
also makes explicit that the API calls will influence the PM policy
behavior.

All drivers and documentation have been updated accordingly.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-03-16 15:26:47 +01:00
Tomasz Bursztyka
173cfad8cb soc: Check and fix const qualifier on ISR
Re-running the script that checks for the const qualifier missing on
ISR's parameter.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2022-03-16 12:33:12 +01:00
Andrzej Głąbek
fd7633126e drivers: pinctrl: nrf: Add support for PWM, QDEC, and QSPI peripherals
Add support for configuring pins to be used by the nRF PWM, QDEC, and
QSPI peripherals.
A new custom property "nordic,invert" is added to the pin configuration
group binding to allow configuring PWM channel outputs as inverted.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2022-03-15 18:38:01 +01:00
Immo Birnbaum
b9f9d4a835 soc: arm: xilinx_zynq7000: add MMU region for PS GPIO controller
Add a 4k indentity mapping in the MMU for the Processor System GPIO
controller if the parent device node is enabled in the device tree.

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
2022-03-15 08:44:46 -07:00
Hake Huang
6be3085e73 soc: add pinctrl header file definition for RT series
Pinctrl requires header file with Z_PINCTRL_STATE_PINS_INIT macro
defined. Add header file for mcux RT pinctrl implementation.
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-15 10:12:57 -05:00
Sylvio Alves
210ed711a3 soc: esp32: add snippets into linker script
Add linker script snippets includes.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-03-14 19:19:24 -04:00
Krzysztof Chruscinski
f7b44a36f8 soc: xtensa: sample_controller: Cleanup backend config
Removing backend config from board Kconfig.defconfig and moving
it to xtensa_sim backend configuration in logging. Without this
change define persisted even when logging was not using backends
and that impacted what is compiled in.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2022-03-14 14:08:49 -04:00
Peng Fan
01002a3c8d nxp: imx: support i.MX8MP EVK board
Support i.MX8MP EVK A53 with/without jailhouse hypervisor
 - Add dts/dtsi
 - Add board file

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-03-14 11:28:35 +01:00
Peng Fan
9be846bf46 soc: arm64: imx8m: share the dummy file
Move the file from board to soc to make it could be shared by
i.MX8M family. When MCUX_HAL supported in future, this file could
be dropped.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-03-14 11:28:35 +01:00
Peng Fan
b63c363989 arm64: nxp_imx: drop a53 linker file
We could reuse the common linker script, no need use i.MX8M specific
one. BTW i.MX8M family is based on A53 core.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-03-14 11:28:35 +01:00
Daniel DeGrasse
8b7f23da28 soc: rt10xx: Enable USB2 controller clock
Enable USB2 controller clock on RT10xx SOC init, if nodelabel has
status="okay"

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-11 14:50:11 -08:00
Daniel DeGrasse
8156299bda soc: rt11xx: enable usb pll clock
USB pll clock should be enabled if USB driver is used. Add required
configuration for USB pll clock.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-11 14:50:11 -08:00
Julien Massot
ccddf12b9c soc: arm: add fvp_aemv8r_aarch32
This is mostly the same than the aarch64 one, excepted that we
force the armv8r fvp to run in aarch32 profile. So that we can simulate
the Cortex-R52.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2022-03-11 10:59:48 +01:00
Yegor Yefremov
b4dfdb5afb soc: arm: nxp_lpc: fix typos
Typos were found with codespell utility.

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
2022-03-10 17:19:49 -05:00
Erwan Gouriou
ed6cc6dce3 soc/arm/st_stm32: stm32wb: Remove stack reset from shutdown
BLE stack reset should now be done in hci close function.
Remove from shutdown procedure.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-03-10 13:28:41 -05:00
Kai Vehmanen
ec7451b485 soc/intel_adsp: add support for Intel Jasper Lake
Add a variant of Intel cAVS2.0 used in Jasper Lake based
products.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2022-03-10 09:26:41 -06:00
Peng Fan
84081ffddc soc: arm64: nxp_imx: Add i.MX8M Mini SoC A53 support
Add minimal SoC support for the NXP i.MX8M Mini series Cortex-A53 Core.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-03-09 09:56:12 -06:00
Navin Sankar Velliangiri
90a11851ec soc: arm: nxp: add LPC55S06 support
Add initial support for the NXP LPC55S06.

Signed-off-by: Navin Sankar Velliangiri <navin@linumiz.com>
2022-03-09 09:46:17 -06:00
Gerard Marull-Paretas
dffaf5375c kconfig: tweak Kconfig prompts
Tweak some Kconfig prompts after the removal of "Enable...".

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-03-09 15:35:54 +01:00
Gerard Marull-Paretas
95fb0ded6b kconfig: remove Enable from boolean prompts
According to Kconfig guidelines, boolean prompts must not start with
"Enable...". The following command has been used to automate the changes
in this patch:

sed -i "s/bool \"[Ee]nables\? \(\w\)/bool \"\U\1/g" **/Kconfig*

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-03-09 15:35:54 +01:00
Andrzej Głąbek
70fb3124db drivers: serial: nrfx: Ensure that instances have some pins assigned
Add build assertions that will ensure that every peripheral for
which a driver instance is created has some pins assigned to it.
Neither pinctrl-0 nor *-pin properties can be currently marked as
required in devicetree, so these assertions will help users avoid
invalid configurations where it could be hard to figure out why
the UART is not working.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2022-03-09 12:05:22 +01:00