The existing SAI diver cannot initialize the PLL on the
board, so the PLL settings will not be performed in the
driver.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Porting gp_renesas_isr_context variable used in FSP interrupt source
to unify with RZ/V2H and prevent build error since they share the same
hal_renesas source code.
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
- Add support for gpio interrupt on RX130.
- Add support for gpio-keys input subsys on RSK_RX130_512KB boards.
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
What is changed?
- Add initial support for the MPS4 Corstone-315 FVP platform, including
board and SoC definitions.The qualifier to build/run application
with board mps4/corstone315 is
`mps4/corstone315/fvp` for secure and
`mps3/corstone315/fvp/ns` for non-secure.
- FVP testing with corstone315 uses the ARM FVP
`FVP_Corstone_SSE-315`.
Why do we need this change?
- This enables FVP support for corstone315.
- A separate FVP variant was added for corstone315 as the TFM board
used for non-secure variant differs for FPGA and FVP.
TFM board `arm/mps4/corstone315` support is present but no FVP support
yet. We can test this by building TF-M with
-DTFM_PLATFORM=arm/mps4/corstone315 and then lauching FVP:
FVP_Corstone_SSE-315 --data "bl1_1.bin"@0x11000000
--data "cm_provisioning_bundle.bin"@0x12024000
--data "dm_provisioning_bundle.bin"@0x1202aa00
--data "bl2_signed.bin"@0x12031400
--data "tfm_s_ns_signed.bin"@0x38000000
Signed-off-by: Shaunak saha <ssaha@tsavoritesi.com>
Fixes: commit a73f20214 ("drivers: wifi: siwx91x: Fix boot_config")
Disabled the 160 MHz feature due to stability issues (mode change)
Signed-off-by: Muzaffar Ahmed <muzaffar.ahmed@silabs.com>
Add gdbstub support to Meteor Lake and a base for other ACE
platforms. Based on the Tiger Lake implementation, but some registers
do differ.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Uses SRAM debug region to pass GDB messages to host, which is exposed
via PTY by cavstool with -d arg or using the SOF kernel driver via a
debugfs file.
Signed-off-by: Noah Klayman <noah.klayman@intel.com>
[guennadi.liakhovetski@linux.intel.com: update to current "main"]
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Add a debug window slot descriptor for the debug window area in the
first page, where descriptors themselves occupy the first few
hundreds of bytes. This area begins 1024 bytes after the beginning of
the debug window until the end of the page and is therefore 3 * 1024
bytes large. Descriptor 15 will be used to describe it and it will be
used for the GDB stub.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
All debug window slot indices should be defined in
adsp_debug_window.h, move them there and use them consistently.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
When the FLEXCOM is activated in the DT, configure it's register
region with strong ordered, read and write access.
Signed-off-by: Tony Han <tony.han@microchip.com>
Create and select the proper module device tree file which loads the
correct radio config for the MGM240P module.
Signed-off-by: Tamas Jozsi <tamas.jozsi@silabs.com>
This enables the clock_control driver build on bl60x.
It is currently deferred init, due to being incompatible
with current SDK-based boot, to avoid later giant PR.
Signed-off-by: Camille BAUD <mail@massdriver.space>
The current CMakeLists.txt uses hardcoded flash addresses for the
bootloader and application, which may not match the slot defined
in the DTS file. This can lead to inconsistencies when flashing
and running images.
This update introduces support for using CONFIG_FLASH_LOAD_OFFSET
and applies CONFIG_BUILD_OUTPUT_ADJUST_LMA if specified,
ensuring that the final image address aligns with the DTS
and runtime expectations.
Note: For ESP32-C6, a custom workaround is included since the
LPCORE does not support MCUboot images.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Modify the STM32 pinctrl driver and SoC-specific pinctrl macros
to introduce support of the st,stm32n6-pinctrl variant.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Set the LTDC buffer alignment to 256 in order to avoid an
issue when accessing to PSRAM via XSPI.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
The SMH attribute when using the XSPI PSRAM is set to EXTERNAL (2)
within the driver hence set default for both LTDC and video
buffer SMH attribute to 2 if all conditions are validated.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Several subsystems have configuration options that allow large buffers
to be placed in specialized memory sections. When PSRAM is enabled, the
MBEDTLS heap and LVGL heap and buffer can be relocated to custom sections
within the PSRAM segment.
Enabling `CONFIG_ESP_SPIRAM` together with any of the following options:
* `CONFIG_MBEDTLS_HEAP_CUSTOM_SECTION`
* `CONFIG_LV_Z_MEMORY_POOL_CUSTOM_SECTION`
* `CONFIG_LV_Z_VDB_CUSTOM_SECTION`
will place the corresponding buffers into the `.mbedtls_heap`,
`.lvgl_heap`, and `.lvgl_buf` sections, respectively.
If none of these custom section options are enabled, the buffers will
fall back to the `.ext_ram.bss` section.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Since the LPSPI drivers no long use MCUX at all, remove the MCUX
branding, to avoid confusion. In the future if an implementation uses
the MCUX SDK driver, it should specifically be called by MCUX in the
name.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Increase the long workqueue stack size to prevent it from being
overflown for example in the GATT database hashing. This leaves
us with a bit less than 200B of headroom as of today
Signed-off-by: Jori Rintahaka <jori.rintahaka@silabs.com>
Struct girq_regs has an array field of length 1 at its end. Since this
field is never used in the code base, we can replace it with a non-array
field of its original element type to remove the flexible-array-like
behaviors and avoid using a flexible array file in the middle of a
struct or defining an array of flexible array struct type.
Fixes zephyrproject-rtos#84251
Signed-off-by: Ella MA <xutong.ma@inria.fr>
Set regulatory domain to default US for IW610 and RW610 socs
and WW for IW416 and IW612 socs.
Signed-off-by: Abhinav Kulkarni <abhinav.kulkarni@nxp.com>
Add a linker script for the stm32mp2x soc series. It includes the
standard arm cortex-m linker and adds standard zephyr relocation
sections.
Replace the rom_start section name with .isr_vectors in the linker
script. This is necessary for the zephyr firmware to be started by the
remote proc driver which expects the section containing the vector table
to be named .isr_vectors.
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
Add initial soc support for the stm32mp2x series, including
initial Kconfig entries and default configuration files.
This enables Zephyr to recognize and build for the stm32mp2x series,
taking the stm32mp257f_ev1 as a baseline.
Includes:
- Kconfig and defconfig files for SoC selection and defaults
- soc.h for hal headers
- CMakeLists.txt for build system integration
- soc.yml update to register the new SoC
System Clock is configured statically from DTS. So no initialization
hook or soc.c needed.
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
Add initial support for Renesas RZ/V2N
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Add SoC support and device trees for Texas Instruments AM2434 SoC. Both R5
and M4 cores are supported here.
Signed-off-by: Amneesh Singh <a-singh7@ti.com>
Some devices have multiple pinctrl regions; for instance, main pinctrl and
mcu pinctrl. Currently there can only be a single pinctrl instance picked
form a DT label. This patch makes the pinctrl driver initialise one
instance for each node with correct compatible string.
Signed-off-by: Amneesh Singh <a-singh7@ti.com>
Added support for deriving `SYS_CLOCK_HW_CYCLES_PER_SEC` from the
Device Tree by reading the `clock-frequency` property in the `itim` node.
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
The driver originally supported only it8xxx2 series. This updates
introduces compatibility allow it to also support it51xxx series
with minimal changes.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Disable support to local ISR declaration on Espressif SoCs.
Code relocation is not yet supported, causing build fail.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
If a bootloader is used, it will configure the SMU and SAU.
The application cannot also configure it, since it can't know
what alias (S vs NS) to access the CMU through. Only connect
the interrupt to the application's vector table if a bootloader
is present.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
This commit adds support for configuring the power/performance
profile for the siwx91x device using a generic
'power-profile' property in DeviceTree.
The property is available for NWP nodes,
allowing flexible selection of power management
profiles per application or board via overlay.
Signed-off-by: S Mohamed Fiaz <fiaz.mohamed@silabs.com>
