The nRF54H20 EXMIF peripheral requires word accesses. Doing accesses of
byte or half-word sizes results in bus fault.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
RC32K and RCX low power clocks require runtime calibration to work
correctly.
Frequency of those clock can differ from chip to chip, one constant
value from Kconfig may not be best when low power clock (sourced
from RCX or RC32K) is used for system tick.
This code modifies global z_clock_hw_cycles_per_sec variable that
is used when TIMER_READS_ITS_FREQUENCY_AT_RUNTIME is enabled
in Kconfig.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
In preparation for simulated nRF54L targets,
let's add kconfig options aking to the ones
we have for the nRF52 and 53 devices.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add the Kconfig options and use the aliased
addresses for the bootcode regions of the IMX7D
and IMX6SX SOCs to allow the Linux rproc
framework to load the irq-vectors into
the correct memory areas.
Activating this option might enlarge the bin
file if the zephyr,flash and rom_start chosen
region addresses are not matching.
It is up to the user to enable this feature
based on code location choices (OCRAM, DDR, TCM...).
Signed-off-by: Jérémy LOCHE - MAKEEN Energy <jlh@makeenenergy.com>
Align SYS_CLOCK_HW_CYCLES_PER_SEC with other SMP nSIM
configurations and set it to 1000000.
This significantly reduce verification time on HS5x platforms.
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Add DT node entries to RW for DAC and ADC.
Support the SOC required initialization of the DAC and ADC on RW.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Mask for FLEXSPI clock divider was being used when setting the FLEXSPI
clock selector value. Correct this to use the mask for the selector
instead of the divider.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
For DA1469x if PM config is selected PM_DEVICE must also
be selected for GPIO to work when device enters/exists
deep sleep.
Previously GPIO and regulator drivers selected PM_DEVICE
when PM was enabled.
Now it is moved to SOC instead.
PM_DEVICE selection in GPIO could result in circular dependency
for mcux if MEMC_MCUX_FLEXSPI (which is already dependent on PM_DEVICE)
was to be additionally dependent on GPIO.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Currently, only DCD bootheader was supported to configure the SDRAM.
On IMX RT1170, XMCD can be used as an alternative boot header to DCD.
XMCD is more advanced than DCD and enhances SDRAM access speed.
This is benefit for SDRAM access application.
Signed-off-by: Trung Hieu Le <trunghieu.le@nxp.com>
`SB_CONFIG_VPR_LAUNCHER` can now be used in building a VPR target,
to enable automatic building of image that will launch the VPR.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
iMXRT1042 SOC should be clocked at 528 MHz maximum. Correct the clock
setup to use the system PLL.
Fixes#70755
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Allow configuration of the system pll on the iMXRT10xx series parts, via
a fractional pll node under the CCM module.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce z_page_frame_set() and z_page_frame_clear() to manipulate
flags. Obtain the virtual address using the existing
z_page_frame_to_virt(). This will make changes to the page frame
structure easier.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
The ILM_MAX_SIZE of different chip variants can be declared in the
Kconfig of the respective variant.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Hardware-specific properties should stay in sync with the definitions
provided by MDK. Existing measures for this include:
* The `validate_base_addresses.c` file included in every build;
* The `nordic-nrf-ficr-nrf54h20.h` header generated from SVD.
If there's information that cannot be extracted from SVD, it may have to
be validated against C types. Add `validate_binding_headers.c` for this
purpose, which automagically includes all `dt-bindings` headers included
by DTS in a given build.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
The HAS_MCUX_CSI (as well as all the HAS_MCUX_XXX) config was obsolete
and has been replaced by the DT_HAS_NXP_IMX_CSI_ENABLED (i.e.
DT_HAS_XXX_ENABLED). Drop it as well as all the dependencies on it.
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
Used multiple places in the tree. The idea is to determine if this node
corresponds to a specific node (e.g: flexspi) so that specific
configurations can get done. Without the fix, the macro expansions were
defaulting to false.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
Commit 149df6b61b ("soc: nordic: nrf54h20: Disable USBHS core cache")
inadvertedly removed default MPU regions defined in arm_mpu_regions.c.
Without the SRAM_0 region defined all builds with asserts enabled result
in failed assertion even before the kernel inits. The failed assertion
is the very last step of arch_kernel_init() when MPU areas are marked
for dynamic regions. Because the failure occurs so early, the device
appears completely dead.
Fix the issue by bringing the default regions to nrf54h20 custom
regions file.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Moves a non-SoC Kconfig to the normal Kconfig file, as this symbol
has nothing to do with the SoC selection itself
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Add `CHECK_DT_REG()` entries for a few additional peripheral types:
BELLBOARD, CCM, GRTC, HSFLL, UICR, and VPR.
For peripheral instances outside of the Global Domain, such as DPPIC020,
use domain-specific defines like NRF_RADIOCORE_DPPIC020 when validating.
These are always defined by the MDK, while NRF_DPPIC020 isn't guaranteed
to exist in those cases. Revise existing macro checks accordingly.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
If no HSFLL needs trimming, then `trim_hsfll()` should be compiled out.
This makes it easier to reuse the rest of `soc.c` out of tree.
Furthermore, some HSFLL instances can be trimmed before booting Zephyr,
so the FICR client properties in the DT binding should not be required.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
External XTAL usage is missing a Bootstrap Cycle configuration
in Kconfig, causing build to failure when CONFIG_RTC_CLK_SRC_EXT_CRYS
is selected.
Fixes#72190
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Configure USBHS core registers as non-cachable to prevent D-Cache from
inhibiting volatile accesses to the USBHS core registers.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
The nRF54H20 implements a variant of the SPI DW peripheral that
has slightly different register layout. Enable it in the defconfig.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
Introducing MDIO and PHY support for stm32, phy driver gets
error (-116) if it tries to read phy chip id, since MDIO IP is
part of ETH IP, and eth hw module is still not initialized.
Forcing a priority that allows possibly connected PHY chip to be
detected properly at initial boot.
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
The ipc driver device data (struct intel_adsp_ipc_data) contains a
semaphore. Upon device init, the device data is zeroed out. This is safe
for other fields, but the semaphore should be properly initialized
before use.
This lack of initialization leads to a system crash when CONFIG_POLL is
enabled (e.g. to enable CONFIG_SHELL), IPC driver handles an interrupt
and executes k_sem_give() on a uninitialized semaphore object. This will
eventually lead to null dereference in z_handle_obj_poll_events().
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
An area of flash memory on the RA4M1 MCU is used to store information
used to configure the device following a reset. This patch instructs
the linker to reserve this memory area and provides kconfig options
that are used to populate it (at build time) with the desired device
configuration.
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
This commit updates the device tree and memory header file
for the Intel MTPM 1.5 platform to define the LSBPM and
HSBPM registers.
Changes include:
- Added node definitions for 'lsbpm' and 'hsbpm' in
intel_adsp_ace15_mtpm.dtsi
- Updated adsp_memory.h
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
This commit updates the device tree and memory header file
for the Intel LNL 2.0 platform to define the LSBPM and
HSBPM registers.
Changes include:
- Added node definitions for 'lsbpm' and 'hsbpm' in
intel_adsp_ace20_lnl.dtsi
- Updated adsp_memory.h
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
This commit updates the device tree and memory header file
for the Intel cAVS 2.5 platform to define the LSBPM and
HSBPM registers.
Changes include:
- Added node definitions for 'lsbpm' and 'hsbpm' in
intel_adsp_cavs25.dtsi and intel_adsp_cavs25_tgph.dtsi
- Updated adsp_memory.h
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
