Commit graph

5973 commits

Author SHA1 Message Date
Adrian Warecki
3de2ce59bc adsp: hda: Extend buffers allowed address space
Changed asserts to allow buffers to be placed in the entire allowed address
space.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2024-06-12 14:32:35 +03:00
Henrik Brix Andersen
58db527d31 Revert "soc: imx93: enable flexcan driver"
This reverts commit 69360d2f38 which is
causing CI build errors.

Fixes: #73955

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2024-06-12 11:54:38 +02:00
Jose Alberto Meza
f854b8b799 drivers: samples: espi: Adjust terms per eSPI specification 1.5
Replace CONFIG_ESPI_SLAVE by CONFIG_ESPI_TARGET
Replace CONFIG_ESPI_SAF by CONFIG_ESPI_TAF
Replace ESPI_BUS_SAF_NOTIFICATION with ESPI_TAF_BUS_NOTIFICATION in API

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2024-06-11 19:46:08 -04:00
Johan Hedberg
fcddefd7f0 Bluetooth: drivers: Convert NXP HCI driver to new API
Convert the hci_nxp.c HCI driver to use the new HCI driver API. Also move
the driver binding under dts/bindings/bluetooth, like all other HCI driver
bindings.

Signed-off-by: Johan Hedberg <johan.hedberg@gmail.com>
2024-06-11 19:42:49 -04:00
Johan Hedberg
b7b606bdaf Bluetooth: drivers: Convert ST STM32WBA driver to new API
Convert the hci_stm32wba.c driver to the new HCI API. Unlike in most cases,
the devicetree node is already enabled on the SoC level (rather than board
level). This is in order to mirror how the Kconfig option was originally
enabled, i.e. on the SoC level.

Signed-off-by: Johan Hedberg <johan.hedberg@gmail.com>
2024-06-11 19:42:49 -04:00
Johan Hedberg
130ae9e120 Bluetooth: drivers: Convert Ambiq Apollo driver to new API
Convert the Ambiq Apollo HCI driver to the new HCI API.

Signed-off-by: Johan Hedberg <johan.hedberg@gmail.com>
2024-06-11 19:42:49 -04:00
Johan Hedberg
97c3a1e4be Bluetooth: drivers: hci: Get rid of Kconfig choice
The drivers should be independent after the move to the new HCI driver
API. Having them as a choice also has unexpected consequences with some
drivers being unexpectedly enabled.

Signed-off-by: Johan Hedberg <johan.hedberg@gmail.com>
2024-06-11 19:42:49 -04:00
Scott Worley
7c0b038d6b soc: microchip: mec: Common SoC init updated to MEC5 HAL v0.2
Microchip MEC5 HAL version 0.2 standardizes HAL API and register
define names. Updated the SoC common initialization code using
new HAL API names.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2024-06-11 20:04:46 +03:00
Emilio Benavente
d85cb222e4 drivers: timer: updated lptmr_timer binding
Updated the lptmr timer binding from
nxp,kinetis-lptmr to nxp,lptmr.

Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
2024-06-11 17:04:26 +03:00
Rafał Kuźnia
6551492a3f soc: nordic: configure run once for nrf54h20
Erase and reset must run only once during flashing.
This prevents a situation, where the next flashed image erases the
previous one.

Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
2024-06-11 14:01:35 +01:00
Marcin Szymczyk
41071584a6 soc: nordic: vpr: remove Zifencei RISC-V extension
VPR does not implement Zifencei extension, remove it.

Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
2024-06-11 03:37:03 -07:00
Reto Schneider
e90c89d453 soc: silabs: Remove SOC_VENDOR_SILABS
Until now, the support for Silicon Labs SoCs is limited to the Gecko
families.

This commit allows upstreaming support for non-Gecko based SoCs produced
by Silicon Labs (i.e. SiM3U1xx).

Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
2024-06-10 15:15:34 -05:00
Alessandro Manganaro
7e9d07537d soc: st: stm32: stm32wbax: Updating hci interface with Cube FW 1.3.1
Updating hci interface according STM32WBA Cube FW 1.3.1

Signed-off-by: Alessandro Manganaro <alessandro.manganaro@st.com>
2024-06-10 15:04:36 -05:00
Marek Matej
9f1a4e3e4f soc: espressif: esp32s3: add cross segment call check
Add build check that would detect unwanted calls
from the `iram0.loader_text`, which is the last
bootloader segment to be alive.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-06-10 16:58:28 +03:00
Marek Matej
61bb79c7ea soc: espressif: esp32s3: fix memory utilization
Fixed bootloader memory layout.
Improved memory utilization.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-06-10 16:58:28 +03:00
Celina Sophie Kalus
a5c67391bb soc: stm32h7: m4: Always enable hardware semaphore clock
When BCM4 bit is set to zero, the hardware semaphore clock is never
enabled on startup. The hardware semaphores might still randomly work,
but very unreliably, and the locking procedure will need several retries
despite no competition on the hardware semaphores. This leads to wasted
clock cycles on the M4 and sometimes even random kernel panics.

This can be solved by always enabling the hardware semaphore clock in
the init procedure of the M4, regardless of whether it is used within
the initialization or not. On the M7, it is already always enabled.

Signed-off-by: Celina Sophie Kalus <hello@celinakalus.de>
2024-06-10 16:56:59 +03:00
nagendra modadugu
161c56fa31 soc: opentitan: update manifest format
Fix calculation of the app entry point.

Signed-off-by: nagendra modadugu <ngm@meta.com>
2024-06-07 19:05:34 -04:00
Anas Nashif
0c0475ff62 soc: xlnx: remove duplicate soc entry
xc7z010 is duplicated.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-06-07 19:02:59 -04:00
Anke Xiao
4873de287a soc: nxp: kinetis: add mke17z9 soc support
Updated the soc.yml and kconfig.soc to support mke17z9

Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
2024-06-07 09:55:56 +02:00
Ioannis Damigos
b7fbd91d9e soc/da1469x: Fix CONFIG_SYS_CLOCK_*_PER_SEC defines
The following configuration options:

SYS_CLOCK_HW_CYCLES_PER_SEC
SYS_CLOCK_TICKS_PER_SEC

should get their values according to lp_clock node's
clock-src property.

Signed-off-by: Ioannis Damigos <ioannis.damigos.uj@renesas.com>
2024-06-07 09:54:30 +02:00
Flavio Ceolin
8100871856 soc: intel_adsp: Avoid duplicate adsp_memory_regions
This header is the same for all ACE platforms. Move it
a common folder.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-06-07 09:52:42 +02:00
Flavio Ceolin
6069f946be soc: intel_adsp: Avoid duplicate header
adsp_memory.h is pretty much the same for all ace platforms.

Generalize it getting register address from devicetree and
and move it to a common place.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-06-07 09:52:42 +02:00
Stanislav Poboril
5774f47e89 soc: rt11xx: support nxp_enet in soc
Support NXP ENET_1G on RT11xx soc.

Fixes: #66348

Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
2024-06-06 20:08:27 -04:00
Karsten Koenig
16e7e46478 soc: nordic: nrf54h: Retrigger TASK_FREQ_CHANGE
A single trigger of the TASK_FREQ_CHANGE task might not be enough, so
trigger twice to make sure the frequency gets updated.

Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
2024-06-06 15:21:51 -05:00
Fin Maaß
1d88d7d139 soc: riscv: litex: add reboot
this makes it possible to reboot a
litex SoC.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-06-06 15:46:40 +01:00
Grzegorz Swiderski
742c728c7e dts: nordic: Add RESETINFO
Add devicetree nodes for the Reset Information registers on nRF54H20,
along with a new binding.

Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
2024-06-06 10:03:15 +02:00
Sebastian Bøe
e1347ded48 soc: nordic: nrf53: Remove broken PM_S2RAM support
Remove dead code that cannot be enabled.

Kconfig prevents us from enabling PM_S2RAM on 53 because it is not
supported any more.

But we still have some dead code left over in soc.c, so we delete this
code.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2024-06-06 10:02:58 +02:00
Francois Ramu
f909c4aee2 soc: st: stm32 common soc config introduce stm32h7R/h7S devices
Add the new STM32HRSX serie from STMicroelectronics

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2024-06-06 00:41:43 -07:00
Francois Ramu
4f995bd0ff soc: arm: stm32h7RS introduce stm32h7R/h7S devices
Add the new STM32HRSX serie with stm32H7R3, stm32H7R7,
stm32H7S3, stm32H7S7 devices from STMicroelectronics
Same MPU regions as stm32h7 device.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2024-06-06 00:41:43 -07:00
Tim Lin
76ced4a82d drivers: pinctrl: ITE: Add a property configure pin current strength
Add the property of drive-strength to drive a high or low current
selection. If this property is not configured, it is the default
setting. According to the SPEC, the default drive current selection
varies from different pins.
Define the high level 0b: 8mA
           low  level 1b: 4mA or 2mA

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2024-06-06 00:41:35 -07:00
Daniel DeGrasse
c77b956de5 soc: nxp: imxrt11xx: support configuration of ARM PLL
Add support for configuration of the ARM PLL on the iMXRT1170/1160
series SOCs. This PLL is used to generate the M7 core frequency, and is
an integer pll. Provide default configurations for the RT1160 and RT1170
targeting 600MHz and 1GHz respectively.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2024-06-06 00:41:17 -07:00
IBEN EL HADJ MESSAOUD Marwa
1e556a85df soc: st: stm32: add stm32h533xx support
Add STM32H533XX familly support

Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
2024-06-05 17:36:43 -05:00
Abderrahmane Jarmouni
323fcf94f9 soc: st: stm32: complete wkup pins cfg before poweroff
Complete wake-up pins configuration before powering off
the system when the CONFIG_STM32_WKUP_PINS flag is enabled.

Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
2024-06-05 17:35:55 -05:00
Abderrahmane Jarmouni
ae17e48036 soc: st: stm32: common: introduce a wake-up pins driver
Implement GPIO pins configuration as sources for STM32 PWR wake-up pins
behind the scenes exclusively from devicetree information for all series
using the public stm32_pwr_wkup_pin_cfg_gpio() function.
Introduce macros for parsing & storing DT wake-up pins config in C structs.
Introduce user-configurable STM32_WKUP_PINS Kconfig flag.

Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
2024-06-05 17:35:55 -05:00
Sven Ginka
c3d7b1c978 soc: atmel: sam: Add invalidate d-cache at z_arm_platform_init
Before that fix, the SOC was unable to boot properly.
Starting turned directly into z_arm_usage_fault().
Fixes zephyrproject-rtos#73485

Signed-off-by: Sven Ginka <sven.ginka@gmail.com>
2024-06-04 22:41:06 -04:00
Peter Mitsis
0bcdae2c62 kernel: Add CONFIG_ARCH_HAS_DIRECTED_IPIS
Platforms that support IPIs allow them to be broadcast via the
new arch_sched_broadcast_ipi() routine (replacing arch_sched_ipi()).
Those that also allow IPIs to be directed to specific CPUs may
use arch_sched_directed_ipi() to do so.

As the kernel has the capability to track which CPUs may need an IPI
(see CONFIG_IPI_OPTIMIZE), this commit updates the signalling of
tracked IPIs to use the directed version if supported; otherwise
they continue to use the broadcast version.

Platforms that allow directed IPIs may see a significant reduction
in the number of IPI related ISRs when CONFIG_IPI_OPTIMIZE is
enabled and the number of CPUs increases.  These platforms can be
identified by the Kconfig option CONFIG_ARCH_HAS_DIRECTED_IPIS.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2024-06-04 22:35:54 -04:00
Chekhov Ma
69360d2f38 soc: imx93: enable flexcan driver
- Add flexcan dts node and pinctrl.

Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
2024-06-04 19:14:16 -04:00
Axel Le Bourhis
ca53f5ee8e soc: rw6xx: Enable NXP_BLE_MONOLITHIC
Enable monolithic build for all BLE apps.

Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
2024-06-04 19:12:45 -04:00
Sadik Ozer
6a8674ce12 soc: Add the MAX32680 SoC
Add MAX32680 Kconfig and dts files

Co-authored-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
2024-06-04 19:12:21 -04:00
Declan Snyder
e8a71d9d83 soc: renesas: Fix linker error from multiple IRQ17
Fix linker error caused by the smartbond timer driver
being enabled at the same time as the smartbond timer counter
driver. For some reason putting SMARTBOND_TIMER=n in a conf
file does not fix this, this change has to be made to the
Kconfig.defconfig to not add this default y case in order
to fix the error. At least that is all I could figure out,
and not sure why the .conf doesn't override it.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-06-04 14:04:09 -05:00
Kai Vehmanen
6ad9b6ccab soc: intel_adsp: tools: add intel_adsp_ace30 support to cavstool.py
Add support for intel_adsp_ace30 platforms into cavstool.py.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-06-04 14:03:32 -05:00
Yong Cong Sin
6a3cb93d88 arch: remove the use of z_arch_esf_t completely from internal
Created `GEN_OFFSET_STRUCT` & `GEN_NAMED_OFFSET_STRUCT` that
works for `struct`, and remove the use of `z_arch_esf_t`
completely.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-06-04 14:02:51 -05:00
Yong Cong Sin
3998e18ec4 arch: rename all esf struct to struct arch_esf
Rename every architecture's esf struct to `struct esf`.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-06-04 14:02:51 -05:00
Ian Morris
422a709d92 soc: renesas: ra: added support for segger rtt
Added support for Segger RTT to Renesas RA family of Microcontrollers.

Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
2024-06-04 14:00:30 -05:00
Nazar Palamar
7c3b66eac8 soc: psoc6: update pinctrl for PSoC6 MCU (legacy)
update pinctrl for PSoC6 MCU (legacy)

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
2024-06-04 16:35:39 +02:00
Piotr Wojnarowski
0f3fe4daab riscv: Align _isr_wrapper to 64 bytes for CLIC
The CLIC requires that mtvec.base is aligned to 64 bytes.
_isr_wrapper is used as mtvec.base, so align it to 64 bytes.

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2024-06-04 13:41:49 +02:00
Sadik Ozer
84a0dee00b soc: Add the MAX32655 SoC
Add MAX32655 Kconfig and dts files

Co-authored-by: Maureen Helm <maureen.helm@analog.com>
Co-authored-by: Okan Sahin <okan.sahin@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
2024-06-04 13:40:44 +02:00
Flavio Ceolin
adabe57f4d soc: intel_adsp/ace: Fix SOC_TOOLCHAIN_NAME symbol
Set the appropriated toolchain name for each ace target.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-06-04 13:40:04 +02:00
Anas Nashif
d35a2b89f3 intel_adsp: dmic: enable support for ptl use new headers
headers for dmic are now part of the SoC and maintained per generation,
so create one header for PTL and build the code for PTL in some of the
drivers (dmic_nhlt).

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-06-04 13:40:04 +02:00
Flavio Ceolin
9637b8b0bc intel_adsp: ace30: Bring up ACE 3.0 (PTL)
This commit adds definition of ACE 3.0 Panther Lake board.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-06-04 13:40:04 +02:00