Replace CONFIG_ESPI_SLAVE by CONFIG_ESPI_TARGET
Replace CONFIG_ESPI_SAF by CONFIG_ESPI_TAF
Replace ESPI_BUS_SAF_NOTIFICATION with ESPI_TAF_BUS_NOTIFICATION in API
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Convert the hci_nxp.c HCI driver to use the new HCI driver API. Also move
the driver binding under dts/bindings/bluetooth, like all other HCI driver
bindings.
Signed-off-by: Johan Hedberg <johan.hedberg@gmail.com>
Convert the hci_stm32wba.c driver to the new HCI API. Unlike in most cases,
the devicetree node is already enabled on the SoC level (rather than board
level). This is in order to mirror how the Kconfig option was originally
enabled, i.e. on the SoC level.
Signed-off-by: Johan Hedberg <johan.hedberg@gmail.com>
The drivers should be independent after the move to the new HCI driver
API. Having them as a choice also has unexpected consequences with some
drivers being unexpectedly enabled.
Signed-off-by: Johan Hedberg <johan.hedberg@gmail.com>
Microchip MEC5 HAL version 0.2 standardizes HAL API and register
define names. Updated the SoC common initialization code using
new HAL API names.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Erase and reset must run only once during flashing.
This prevents a situation, where the next flashed image erases the
previous one.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
Until now, the support for Silicon Labs SoCs is limited to the Gecko
families.
This commit allows upstreaming support for non-Gecko based SoCs produced
by Silicon Labs (i.e. SiM3U1xx).
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Add build check that would detect unwanted calls
from the `iram0.loader_text`, which is the last
bootloader segment to be alive.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
When BCM4 bit is set to zero, the hardware semaphore clock is never
enabled on startup. The hardware semaphores might still randomly work,
but very unreliably, and the locking procedure will need several retries
despite no competition on the hardware semaphores. This leads to wasted
clock cycles on the M4 and sometimes even random kernel panics.
This can be solved by always enabling the hardware semaphore clock in
the init procedure of the M4, regardless of whether it is used within
the initialization or not. On the M7, it is already always enabled.
Signed-off-by: Celina Sophie Kalus <hello@celinakalus.de>
The following configuration options:
SYS_CLOCK_HW_CYCLES_PER_SEC
SYS_CLOCK_TICKS_PER_SEC
should get their values according to lp_clock node's
clock-src property.
Signed-off-by: Ioannis Damigos <ioannis.damigos.uj@renesas.com>
adsp_memory.h is pretty much the same for all ace platforms.
Generalize it getting register address from devicetree and
and move it to a common place.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
A single trigger of the TASK_FREQ_CHANGE task might not be enough, so
trigger twice to make sure the frequency gets updated.
Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
Add devicetree nodes for the Reset Information registers on nRF54H20,
along with a new binding.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Remove dead code that cannot be enabled.
Kconfig prevents us from enabling PM_S2RAM on 53 because it is not
supported any more.
But we still have some dead code left over in soc.c, so we delete this
code.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Add the new STM32HRSX serie with stm32H7R3, stm32H7R7,
stm32H7S3, stm32H7S7 devices from STMicroelectronics
Same MPU regions as stm32h7 device.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the property of drive-strength to drive a high or low current
selection. If this property is not configured, it is the default
setting. According to the SPEC, the default drive current selection
varies from different pins.
Define the high level 0b: 8mA
low level 1b: 4mA or 2mA
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add support for configuration of the ARM PLL on the iMXRT1170/1160
series SOCs. This PLL is used to generate the M7 core frequency, and is
an integer pll. Provide default configurations for the RT1160 and RT1170
targeting 600MHz and 1GHz respectively.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Complete wake-up pins configuration before powering off
the system when the CONFIG_STM32_WKUP_PINS flag is enabled.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Implement GPIO pins configuration as sources for STM32 PWR wake-up pins
behind the scenes exclusively from devicetree information for all series
using the public stm32_pwr_wkup_pin_cfg_gpio() function.
Introduce macros for parsing & storing DT wake-up pins config in C structs.
Introduce user-configurable STM32_WKUP_PINS Kconfig flag.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Before that fix, the SOC was unable to boot properly.
Starting turned directly into z_arm_usage_fault().
Fixes zephyrproject-rtos#73485
Signed-off-by: Sven Ginka <sven.ginka@gmail.com>
Platforms that support IPIs allow them to be broadcast via the
new arch_sched_broadcast_ipi() routine (replacing arch_sched_ipi()).
Those that also allow IPIs to be directed to specific CPUs may
use arch_sched_directed_ipi() to do so.
As the kernel has the capability to track which CPUs may need an IPI
(see CONFIG_IPI_OPTIMIZE), this commit updates the signalling of
tracked IPIs to use the directed version if supported; otherwise
they continue to use the broadcast version.
Platforms that allow directed IPIs may see a significant reduction
in the number of IPI related ISRs when CONFIG_IPI_OPTIMIZE is
enabled and the number of CPUs increases. These platforms can be
identified by the Kconfig option CONFIG_ARCH_HAS_DIRECTED_IPIS.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Enable monolithic build for all BLE apps.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
Fix linker error caused by the smartbond timer driver
being enabled at the same time as the smartbond timer counter
driver. For some reason putting SMARTBOND_TIMER=n in a conf
file does not fix this, this change has to be made to the
Kconfig.defconfig to not add this default y case in order
to fix the error. At least that is all I could figure out,
and not sure why the .conf doesn't override it.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Created `GEN_OFFSET_STRUCT` & `GEN_NAMED_OFFSET_STRUCT` that
works for `struct`, and remove the use of `z_arch_esf_t`
completely.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The CLIC requires that mtvec.base is aligned to 64 bytes.
_isr_wrapper is used as mtvec.base, so align it to 64 bytes.
Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
headers for dmic are now part of the SoC and maintained per generation,
so create one header for PTL and build the code for PTL in some of the
drivers (dmic_nhlt).
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit adds definition of ACE 3.0 Panther Lake board.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
