Use the series-agnostic STM32 LL headers from the STM32Cube HAL module
instead of series-specific ones in STM32 SoC-specific code. Also remove
inclusion of `stm32XXxx.h` in a few files which already include `soc.h`
who is tasked with doing this inclusion.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Adds snippets-text-sections.ld to linker scripts. So that
the mem_map test can run on qemu_xtensa/dc233c/mmu.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Introduce register structures and macros for the long countdown timer to
support counter functionality in npcx and npck series.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Adds separate memory regions for rtc ram memory areas and reworks linker
scripts to make use of their starting addresses and lengths
Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
Enable dynamic configuration of region mapping with a 1:1
virtual-to-physical address mapping.
This configuration is aligned with the static declaration of the
MMU table using MMU_REGION_FLAT_ENTRY macro.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
When the MCAN is activated in the DT, configure it's register region
with strong ordered, read and write access.
As CANx accesses the lower or upper 64K SRAM is selected by bits in
register 'SFR_CAN_SRAM_SEL', also configure SRAM and SFR region with
strong ordered, read and write access.
Signed-off-by: Tony Han <tony.han@microchip.com>
* ARM Cortex-M3 processor
* Up to 32 kB Flash and 4 kB RAM memory
* Energy efficient and autonomous peripherals
* Ultra low power Energy Modes
* Fast wake-up
Signed-off-by: Lukas Woodtli <woodtli.lukas@gmail.com>
LLEXT-related sections should only be added to the linker script when the
associated CONFIG_LLEXT is enabled. This has been done by checking for this
Kconfig symbol in every linker file, but this creates a lot of boilerplate
for no good reason.
Use the much simpler solution: move the check inside the common linker file
and remove existing "#ifdef CONFIG_LLEXT" checks in all linker files.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Interrupts would only be unlocked when resuming from suspend-to-idle.
Even though other states *should* never be entered, make sure interrupts
are unlocked anyways to conform with the expectations of the PM framework.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The ATOMIC_OPERATIONS_* Kconfig option is not a choice, so it does not
have a default. However, the file that determines which actual atomic
operations backend will be used does default to
ATOMIC_OPERATIONS_BUILTIN:
3e537db71e/include/zephyr/sys/atomic.h (L26-L41)
Since we want to ensure that all SoCs intentionally select the atomic
operations backend they want to use, select it at the SoC level for all
SoCs, as well as for the Cortex-M arch when the Armv8-M baseline profile
is selected.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Instead of gluing to the one in the HAL which is not very flexible to
configure, define the container header in the zephyr SOC code. This
fixes the bug of CONFIG_NXP_FLEXSPI_ROM_RAMLOADER not working.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The IQR vector table changed size since a825e01 and it is
causing issues with downstream applications, for example,
data stored in bin specific field is shifted by
the ARCH_IRQ_VECTOR_TABLE_ALIGN, so I make
ARCH_IRQ_VECTOR_TABLE_ALIGN constant.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
There is new exception debugging mechanism for RISC-V which needs
additional member in arch_esf structure. VPRs handle stacking
partially in hw so exact position of some stack members needs
to be at the end of arch_esf, so explicit padding is needed.
Aligned also ESF_SW_IRQ_SIZEOF when exception debug is used.
Signed-off-by: Łukasz Stępnicki <lukasz.stepnicki@nordicsemi.no>
Place the 'vectors' region configuration behind the 'sram' and
'rom_region' configurations so that the MPU region for the
vectors takes precedence over the 'sram' region due to higher
region index = higher priority when resolving memory properties
/ permissions for overlapping regions. This is required for the
vectors to work properly if the SRAM base address is also at 0x0.
Fixes#96688.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Fix the issue regarding passing the TRNG peripheral instance to the driver.
Increase the SYSTEM_WORKQUEUE_STACK_SIZE when CONFIG_BT is set.
According to the log of thread analyzer for beacon sample, 1048 bytes
are needed. So, it's been increased to a safer value.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
kCLOCK_Sysctl must be enabled for FLASH_CacheClear,
FLASH_CacheSpeculationControl and FLASH_CheckECC to have an effect.
Signed-off-by: Allen Zhang <chunfeng.zhang@nxp.com>
This commit fixes a change introduced in #97025
where too many definitions where removed.
Fixes issue #98382
Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>
The fix resolves the drift test failure as part of kernel
timer behaviour and timer api test suite.
Moved sleeptimer-related source files to RAM using zephyr_code_relocate
when CONFIG_SILABS_SISDK_SLEEPTIMER is enabled, and removed duplicate
listing from PMGR backend.Updated Kconfig to select SRAM_VECTOR_TABLE
and CODE_DATA_RELOCATION_SRAM for the sleeptimer service.
Signed-off-by: S Mohamed Fiaz <Fiaz.Mohamed@silabs.com>
Radio interrupts were only initialized if CONFIG_ARM_SECURE_FIRMWARE=y,
but should be initialized independently of security configuration.
Move initialization from soc_prep_hook() to soc_early_init_hook(),
there is no reason to configure interrupts earlier.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Remove redundant enabling of NRF_RTC_TIMER in SoC specific files
and replace it with default y in the NRF_RTC_TIMER definition.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Setup most clocks with common_clock_set_freq().
PLL and mux are preset.
Signed-off-by: Winteri Wang <dongjie.wang@nxp.com>
Signed-off-by: Ruoshan Shi <ruoshan.shi@nxp.com>
use CONFIG_RISCV_ISA_EXT_F to set CONFIG_CPU_HAS_FPU.
Same for CONFIG_RISCV_ISA_EXT_D and
CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Change the default coex mode when there is neither WiFi or BT activated.
Switch from BLE_ONLY to WLAN_ONLY. It fix a bug where we can't go in
deepsleep if we didn't select CONFIG_WIFI.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Update the default MAIN_STACK_SIZE to 2048 bytes to accommodate
the initialization requirements of the network coprocessor (nwp),
particularly when power management is enabled. It resolves a bug
where we can't boot when PM is enabled with multiple active
peripherals.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
For all STM32 drivers and SoC, replace the MODIFY_REG macro (defined in
the STM32 HAL) by stm32_reg_modify_bits defined in Zephyr.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For all STM32 drivers and SoC, replace the READ_BIT macro (defined in
the STM32 HAL) by stm32_reg_read_bits.
Fixes some cases where the return value was tested like a boolean
despite not being one.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add a set of bitops functions in order to replace the STM32 HAL bitops
macros throughout the drivers.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
`CONFIG_EXTRA_EXCEPTION_INFO` that was added in #78065 doesn't
seem necessary, as we were already storing and printing the
callee-saved-registers before that. All `CONFIG_EXTRA_EXCEPTION_INFO`
does in RISCV is to add an additional `_callee_saved_t *csf` in the
`struct arch_esf`, which overhead is negligible to what's being enabled
by `CONFIG_EXCEPTION_DEBUG`.
Let's remove `CONFIG_EXTRA_EXCEPTION_INFO`, and have that extra
`_callee_saved_t *csf` in the `struct arch_esf` as long as
`CONFIG_EXCEPTION_DEBUG` is enabled.
TL;DR: it doesn't make sense to not enable `CONFIG_EXTRA_EXCEPTION_INFO`
when `CONFIG_EXCEPTION_DEBUG` is enabled, so let's merge them.
Then, since `*csf` is always available in the `struct arch_esf` when
`CONFIG_EXCEPTION_DEBUG=y`, we can simply rely on that pointer in
`z_riscv_fatal_error()` instead of an additional argument in
`z_riscv_fatal_error_csf()`, rendering the latter redundant and thus
can be removed.
Additionally, save the callee-saved registers before jumping to
to `z_riscv_fault()`, so that callee-saved-registers are printed on
generic CPU exception as well.
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Remove SOF-specific region mappings. These should be handled inside of
SOF (external module), instead of Zephyr. This way, we avoid creating
a cyclic dependency between the two.
Needed for #91061.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Changes initialization to use a function from hal_infineon. This
initialization function will initialize the AutAnalog system if needed
as well as the SystemInit.
Signed-off-by: John Batch <john.batch@infineon.com>
