These devices have non-standard cache lines (128 bytes), and were
inheriting an incorrect setting for this kconfig.
Also clean up some related feature kconfigs which were being ignored
and not set =y.
Signed-off-by: Andy Ross <andyross@google.com>
This is a pre-existing (but rarely used) Zephyr linker tag. Support
it instead of reinventing something similar.
Signed-off-by: Andy Ross <andyross@google.com>
The Linux SOF driver owns this space, but puts buffers here which the
DSP is expected to read and write. Give it a space in the default MPU
mapping.
Note that this assumes that the DMA region is numerically above the
linkable DRAM region in the address space. That's true for existing
devices, but likely to be broken in the future.
Signed-off-by: Andy Ross <andyross@google.com>
The SOF source code is confusing. On some hardware these devices have
distinct IRQs assigned, and on others they seem to share an ISR for
all. Leave the existing assignments in place for SOF-compatibility,
but union all the devices into a single ISR path that will poll each
(there are only two). This will work in all configurations, and we
can figure out the proper architecture at leisure.
Signed-off-by: Andy Ross <andyross@google.com>
SOF needs this information for rimage to work, it contains data needed
by the kernel loader and not firmware per se. Note that contra other
SOF platforms, this leaves the data in the live firmware image so it
can be inspected at runtime. That's not needed by core SOF code, but
is handy for debugging. And these devices have a ton of DRAM space
available.
Signed-off-by: Andy Ross <andyross@google.com>
Add support for STM32H757 SoC, which shares its design
with STM32H747 with added cryptography peripherals.
Signed-off-by: Grzegorz Runc <g.runc@grinn-global.com>
The EFR32MG24B210F1536IM48 has 4 more GPIOs than the
EFR32MG24B310F1536IM48, and does not support the high accuracy
mode for the IADC.
Signed-off-by: Daniel Fuchs <software@sagacioussuricata.com>
Add support for .cold and .coldrodata sections, used to implement
a cold module. Assigning code and read-only data to those sections
makes them suitable for use in a cold module, stored and executed in
slow memory.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Add a manifest for a "cold" module, that will be executed in DRAM
without copying it to SRAM for the whole duration of the firmware
life-time.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Before copying modules to SRAM, check whether they're built for it,
skip modules, that aren't.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Build is failing due to wrong calls to appcpu
stall and clock gating. This fixes it
by using proper registers.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add UF2 Family ID for Raspberry Pi 2350 and build
UF2 image by default for Pico 2 board
Signed-off-by: Ryan Grachek <grachek@gmail.com>
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
On RP2350, the alt function value can be up to 0x1F, so store as 5 bits.
Signed-off-by: Peter Johanson <peter@peterjohanson.com>
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
A significant amount of the pin muxing is duplicated between the RP2040,
the RP2350A, and RP2350B. Reflect this in the file structure, with a
`-common` suffix used to to indicate this.
Macros are defined in ascending order of the function index in the
relevant table in the datasheet. SoC/SoC-series specific macros are
defined in their respective tables. Functions that are not currently
used (e.g. the new HSTX) are intentionally not defined here as they do
not (currently) have any use in the Zephyr tree (i.e. there's no drivers
that make use of this functionality).
clang-format has been run over the existing definitions to reduce the
noise generated by CI. These are cosmetic changes; I've tried to retain
attribution to the relevant authors where applicable.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
RP2350 is Raspberry Pi's newest SoC. From the datasheet:
"RP2350 is a new family of microcontrollers from Raspberry Pi that
offers significant enhancements over RP2040. Key features include:
• Dual Cortex-M33 or Hazard3 processors at 150 MHz
• 520 kB on-chip SRAM, in 10 independent banks
• 8 kB of one-time-programmable storage (OTP)
• Up to 16 MB of external QSPI flash/PSRAM via dedicated QSPI bus
...
"
This commit introduces some changes to support the existing RP2040 and
what is describe by Raspberry Pi as the "RP2350 family". Currently there
are 4 published products in the family: RP2350A, RP2350B, RP2354A, and
RP2354A. Within Zephyr's taxonomy, split the configuration as follows:
Family: Raspberry Pi Pico. This contains all RP2XXX SoCs,
SoC Series: RP2040 and RP2350.
SoC: RP2040 and, for now, just the RP2350A, which is present on the Pico
2, where the A suffix indicates QFN-60 package type. This structure is
reflected in `soc/raspberrypi/soc.yml`, and somewhat assumes that there
won't be a RP2050, for example, as a RP2040 with more RAM.
This is foundation work ahead of introducing support for Raspberry Pi's
Pico 2 board, which is fitted with a RP2350A and 4MB of flash.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
nRF54L05 and nRF54L10 devices that are emulated on nRF54L15
needs to have manually disabled remaining RAM blocks
that are outside of their RAM region definitions.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
RAM retention is disabled for all RAM blocks
before entering System OFF to achieve lowest power consumption.
RAM retention can still be enabled using retained_mem driver.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
This reverts commit b33b3b17f7, turns out
it's causing issues in CI all over the place, the condition needs more
thinking.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add the DWARF v5 sections to the linker scripts of
imx, imxrt, acp_6_0 and xtensa_sample_controller.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Add a compiler warning when building for an STM32 series MCU with PM
enabled but STM32_ENABLE_DEBUG_SLEEP_STOP=y. That option greatly
increases the power consumption during sleep, which is probably
undesirable when building with PM=y, and it can be activated silently
as a side effect of other options (namely RTT) making it tricky to find
out.
Add a warning to expose the situation.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Remove the PS GPIO controller's static MMU region entry from the
mmu_regions table for both the XC7Zxxx and XC7ZxxxS variants of the
Zynq 7000.
The PS GPIO controller's device driver has been switched over to
using a named DEVICE_MMIO mapping.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Now that MbedTLS is capable of automatically enabling
CONFIG_ENTROPY_GENERATOR (when available), we can remove forced
enablements in boards|soc deconfig files.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
This is based on the introduction of a helper Kconfig symbol in
"subsys/random/Kconfig" which is named CSPRNG_AVAILABLE. When this is
enabled it means that there is a "zephyr,entropy" property defined in the
device-tree, therefore Mbed TLS can select ENTROPY_GENERATOR to allow
the platform specific driver to be included into the build.
This commit also changes other locations where CSPRNG_ENABLED was used
moving it to CSPRNG_AVAILABLE in order to solve dependency loop
build failures.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
Creation of the new zephyr\soc\nxp\common\nxp_nbu.c driver which manage
the interruption of the NBU. This modification is mandatory to support a
coex application which includes Bluetooth and 802.15.4 on the same
narrow band path.
Signed-off-by: Xavier Razavet <xavier.razavet@nxp.com>
Wakeup pin indices are 1-based, but `LISTIFY` is 0-based. Consequently, the
last element of the pin-to-register-bit lookup table was never populated.
Signed-off-by: Samuel Coleman <samuel.coleman@rbr-global.com>
BICR (Board Information Configuration Registers) are located within the
application UICR region (ref. MRAM mapping, table 38).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Enable CONFIG_HAS_MCUX_IGPIO because device driver CONFIG_GPIO_MCUX_IGPIO
depends on it, so that the driver can be enabled by dts nodes.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
LinkServer can flash only the first time, cannot flash again.
Fix it by setting default mcu security status as unsecure.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
nRFs exposes now all power domains, following their actual name in the
specification. Add support for all of them in the GPD service. Note that
this is a breaking change: running this code requires a new SCFW as IDs
have changed in nRFs and so SCFW.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The clock controller/manager registers are updated with
the correct divider values by bootloader via hand-off
data, so now we can use the clock controller to get the
clock value of each peripheral during the run time.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
CMakeLists.txt uses the C compiler parameter -include,
This is causing issues for other toolchains and needs to generalized.
Signed-off-by: Robin Kastberg <robin.kastberg@iar.com>
Updates for AMP targets
- use common AMP Kconfig
- update APPCPU linker script
- place AMP common area in the reserved space
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Multiple AMP related updates:
- use common AMP Kconfig
- rework the APPCPU linker script
- use MCUboot image format for APPCPU image
- fix multi-processing startup code
Signed-off-by: Marek Matej <marek.matej@espressif.com>
This is the initial commit to support pinctrl driver for Renesas RZ/G3S
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This adds minimal support for a new SoC Renesas RZ/G3S
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
