Add stm32l1_disco and nucleo_l152re overlays for testing
sleep/stop/standby modes:
- samples/boards/st/power_mgmt/blinky;
- samples/boards/st/power_mgmt/wkup_pins;
I've measured consumption for each low-power mode:
- low-power sleep ~1.72mA;
- stop mode ~324uA;
- standby mode ~2.2 uA;
It's possible to use RTC as idle timer to exit from stop mode.
Signed-off-by: Oleh Kravchenko <oleg@kaa.org.ua>
Adds additional MPU memory permissions to userspace applications by
default. This change addresses an MPU fault encountered when running
tests/kernel/common and tests/drivers/adc/adc_api.
This approach opens additional memory locations up to user space access.
This assumes that end users of applications will tune the MPU regions for
the needs of that application.
Signed-off-by: John Batch <john.batch@infineon.com>
If the application uses slot 1 (i.e. in Direct XIP mode),
boot radio slot 1 instead of slot 0.
Signed-off-by: Tomasz Chyrowicz <tomasz.chyrowicz@nordicsemi.no>
Currently the linker script for ACE defines memory regions for
literals in interrupt vector memory. This wastes memory and leads to
link failures when CONFIG_USERSPACE is enabled. Remove those regions
to reclaim 8 bytes per vector and fix linking. Also remove duplicated
level 4 interrupt vector sections and replace spaces with TABS.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
There is no reason to place sli_siwx917_soc.h under #ifdef. Then, we can
get rid of the #if in the body of soc_early_init_hook().
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Variable CONFIG_SOC_PART_NUMBER is only used in CMakeLists.txt of
hal_silabs. In fact, this variable can be easily calculated from CONFIG_SOC
by changing lower case in upper case.
So, let's drop this useless variable.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
SOC_GECKO_SDID is no more referenced since commit 955aca6c0 ("soc: silabs:
Initialize clock manager HAL from DT"). We can safety drop it.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
mspm0 family of SoC series is split into three category,
mspm0g - high performance
mspm0l - low power
mspm0c - entry level
With G already part added, add support for L series of SoC's.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
mspm0 series (currently g, l and c) shares the common SoC
level init functions and pin control/muxing configurations.
To avoid duplication for each series, create a common path
and move the SoC and pin control definitions.
Other common functionalities like Power Management, Power off
handling will be added in future, which will be common across
series.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Flash size and address is extracted from dts, which will be common
for all the upcoming series of SoC's like MSPM0L, MSPM0C. Move the
flash address and size to soc level defconfig.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Systick is already enabled before late hook got called. In certain
circumstances systick could flooding the core and thus only handling
systicks. Enabling cache earlier using soc_early_init_hook ensures
that systick get handled quicker.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
m33 must ensure the TCM is ECC clean by initializing all dtcm memories
Otherwise, it can only run it by loading m33 under uboot.
Based on this fixed, we can run M33 by mkimage into flash.bin.
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
We want to simplify the maintenance burden and confusion of having
more than one driver for the same kernel timer peripheral used on
all Microchip MEC parts. The XEC version of the driver was converted
register definitions in the driver. Register access is performed using
Zephyr sys_read/write architecture specific inline routines. Driver DT
YAML was updated to use phandle for the 32-bit basic timer used for
ARCH_HAS_CUSTOM_BUSY_WAIT support, basic timer max value property,
and GIRQ interrtup aggregator hardware information.
SoC part Kconfigs, chip level/board level DTSI updated to use the
unified driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
All parts in the Microchip MEC family support ARM JTAG/SWD/SWO.
We add Kconfig logic to allow building projects with Segger's
RTT debug for Cortex-M.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Add ae350/clic soc, which shares the same peripherials as AE350 PLIC
platform but uses CLIC instead of PLIC, with different IRQ number.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Turn MCX series into families.
Reasoning:
1. The MCX SOCs are quite different from each other and having them all
under one family in the HWMv2 hierarchy is fruitless because there
are so many differences that it is confusing to try to introduce
family-level code and configs since they would each only apply to a
subset of the series. There is almost nothing that can be shared
between all of them. Which is why there are comments in the MCX
family files saying not to put anything in them. This is a technical
waste.
2. Therefore, turning all of them into families is almost 0 effort and
makes sense. It will allow these different types of MCX to be
further subdivided into series in the future as the MCX portfolio
expands and such division will be necessary as new SOCs within each
letter family are released.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add a STM32_APP_IN_EXT_FLASH to determine that an application
is eXecuting in Place on an external xspi flash.
That will control the clock init of this external xspi controller.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
So we can enable features for both the real and simulated
targets based on these same options.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
In preparation for simulated nRF54LM20 targets, let's add kconfig
options aking to the ones we have for the nRF54L15 devices.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
After removing NATIVE_APPLICATION, only NATIVE_LIBRARY is
possible with SOC_POSIX.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Following changes in e35ac8f and 14c1b4a to how external Q/OSPI Flash
nodes are declared in DT for boards with STM32 SoCs, FLASH_BASE_ADDRESS
needs to be set manually similar to XSPI Flash, so that it does not
default to (dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) which gives 0.
This change is critical for running apps with MCUboot from external
Q/OSPI Flash.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
fix ulpm driver polarity issue.
when pin-pol set to falling need to set the POL bit to 1.
when pin-pol set to rising need to set the POL bit to 0.
Signed-off-by: Titan Chen <titan.chen@realtek.com>
Some ESP32 images may not end with a segment whose
load_addr is 0xFFFFFFFF, especially if the flash was not fully
erased or the image tool does not write an explicit end marker.
This can cause the loader to process leftover or unrelated data as
additional segments, resulting in boot failures.
Update the IS_LAST() macro to treat any segment not matching
a valid memory region as the end of the segment list.
This ensures only valid segments are loaded and any trailing
invalid data is safely skipped.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
There is no need to call stm32_pwr_wkup_pin_cfg_pupd() because
the SoC does not have a pull-up/pull-down on the WKUP pin.
Call LL_PWR_ClearFlag_SB() before entering StandBy power mode.
Signed-off-by: Oleh Kravchenko <oleg@kaa.org.ua>
Some of ESP32 Radio calls present in blobs needs to be
executed from IRAM or RAM instead of flash to avoid
cache disabled issues.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This Kconfig was deprecated in Zephyr 3.5, remove allowing it to
be selected but keep the symbol as the HAL needs to be updated
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Check for STM32F1 series was done with "#ifdef SOC_SERIES_STM32F1X"
but this symbol comes from Kconfig.
Use the correct "CONFIG_SOC_SERIES_STM32F1X" instead.
Signed-off-by: Oleh Kravchenko <oleg@kaa.org.ua>
Move the IronSide APIs to soc/nordic from drivers/firmware since
these are vendor specific APIs. The header files are now included
from <nrf_ironside/*.h>. Adjust code that uses these APIs accordingly.
Also move the DT binding for "nordic,ironside-call" from
bindings/firmware to bindings/misc.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Utilize a code spell-checking tool to scan for and correct spelling errors
in `Kconfig` files within the `soc` and `subsys` directory.
Additionally, incorporates a fix recommended by the reviewer.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
The marking procedures can be reverted, since at this stage
it is already allowed to use the stack.
The MSP is temporairly set to interrupt stack in `reset.S` file before
calling s2ram procedures..
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
This reverts commit e68d110f7c175f2a9275659d023c9d37d1e4b4f1.
Fix for compiling i2s drivers on the NXP mimxrt1010_evk board.
For mimxrt1011, the defines kCLOCK_Sai2... are not defined as the sai2
peripheral does not exist. Trying to compile gives error. Fixed by adding
check for device tree node around code that uses the defines. Also added
same for sai1 and sai3. Thanks @lucien-nxp, @ZhaoxiangJin from NXP.
Signed-off-by: Imran Sajjad <imran.sajjad@iconfitness.com>
Don't force select INIT_SYS_PLL at SOC level. Instead use default y so
that board can unset it. Keep previous case where we would default y
which was only on RT1040. Also, this config is not used in RT1170 soc,
so move it to RT10xx series kconfig instead of family level. And it
appears to be on all the RT10xx, so ifdef is not needed.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Don't force select the INIT_VIDEO_PLL config so that board level can
unset it. Also clean up the code a bit in soc.c files.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The LDO config should not be forcefully selected at SOC level. Instead,
use soft default y so that board definition can unset it if desired.
Also, in the soc.c, the LDO code should be on both the rt1160 and
rt1170, so the definitions should exist, and ifdef is not needed. So can
switch to IS_ENABLED to decrease configuration complexity of the source
code.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The DCDC should be on all the platforms and the functions and structs
should therefore be defined on all the platforms. So the ifdef is not
needed, we can remove it to increase code compilation coverage unity
across configurations slightly. Compiler should optimize out the block
when IS_ENABLED is false statically.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Don't forcefully select this config in SOC level. Make it softer default
y so board can unselect it.
The config should not be possible if there is no arm pll, namely on
RT101x and RT102x. So add dependency clause about this.
And of course, code for this was a mess, clean up a bit.
Also remove the ifdeffry for selecting a default value for the two SOCs,
because they already put the same default value in the SOC Devicetree
DTSI, so that code had no purpose as long as a board didn't completely
redefine the SOC DT.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Initial motivation for this commit was to not force select
the INIT_ENET_PLL config from SOC level to allow for board level
configuration which might want it to be off.
While doing that, I discovered that RT11xx actually does not have
anything called by "ENET PLL" in the reference manual. So I have
removed the config for RT11xx. The default clock source for this soc.c
code for RT11xx is PLL1 DIV2, which I changed to just be configured if
ethernet is enabled, which was the reason to configure this pll as it
stands now, even though it is not specific to ethernet (although the
DIV2 output is mostly for ethernet). Another config is therefore not
needed.
For RT10xx, the situation is a lot more complicated. There is a lot of
discrepancy again between what is considered the "ENET PLL" both
conceptually and literally between the RM, SDK, and Zephyr config. And
also the code to define the config struct was a complete mess. So I have
simplified the code and changed it so that the config is only a soft
default to y instead of selected forcefully. Also, for the case of the
RT1010 and RT1020 series, the SDK is appearing to configure PLL6 (again
there is no clear ENET PLL meaning on these platforms) 500M output
through this "enet pll" configuration function. So similarly instead of
always enabling this output for those platforms, I added a new config
which can be set or unset by board level.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The original logic relied on the tick passed in. This method
is inaccurate as the tick value passed in was the exit latency.
Update the code to calculate the remaining time left and set
a counter using this value.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
