Add config file to host WiFi specific settings.
Introduce CONFIG_ESP_WIFI_MAX_THREAD_PRIO to be used
as a cap for the LL driver runtime.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
The power_down() function will lock dcache for the hpsram_mask
array. On some platforms, the dcache lock will fail if the array
is on cache line that can be used for window register context
saves.
Work around this by aligning and padding the hpsram_mask to cacheline
size.
Link: https://github.com/thesofproject/sof/issues/9268
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
After flashed EC image, we needed to manually press the reset button
on it8xxx2_evb. Now, without pressing the button, we can disable
debug mode and trigger a watchdog hard reset for running tests.
After flash EC, running below tests can pass (without pressing the button):
west build -p always -b it8xxx2_evb tests/drivers/watchdog/wdt_basic_api
west build -p always -b it8xxx2_evb tests/kernel/timer/timer_api
west build -p always -b it8xxx2_evb tests/kernel/fatal/exception
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
For stm32 platforms where the sysclock is less or equal to
32MHz, the Ticks per second is reduced to 8000 (instead of
10000).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Many xtensa target jump from soc code directly into cstart and depend on
architecture code being initialized in arch_kernel_init(). Instead of
jumping to cstart, jump to newly introduced prep_c similar to all other
architectures, where common platfotm initialization will happen.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This update is to support clock API for RA8
Move the clock initialize function into clock driver
Peripheral clock now has 2 more property in clock cell for enable
and disable clock to peripheral module
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
This change adds the device tree property for specifying oe-override
(output-enable override behavior), as well as defines for possible values
of the property.
RP2040 GPIOs can be configured to automatically invert the output-enable
signal from the selected peripheral function. This is useful for tasks like
writing efficient PIO code, such as in the i2c example in the rp2040
datasheet.
Signed-off-by: Yiding Jia <yiding.jia@gmail.com>
cplusplus-rom linker initialization was wrongly placed
in RAM area when it should be in ROM area.
Fixes#75853
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
In addition to Kconfig options (soon to be deprecated), allow
configuring the regulators using DT.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Previously, the `soc.c` files for the IMXRT11xx, IMXRT5xx/CM33, and
IMXRT6xx/CM33 did not register the log module. This caused build
errors when DEBUG logging was enabled, as the `power.c` file attempted
to access a non-existent SOC log module for debug messages.
This commit fixes the issue by registering the log module in the
`soc.c` files for the specified SoCs, thereby resolving the build
errors.
Signed-off-by: Apoorv Singh <apoorv.singh@gin.de>
Fix formatting for `soc.c` files for the IMXRT11xx, IMXRT5xx/CM33, and
IMXRT6xx/CM33 by running 'clang-format'.
Signed-off-by: Apoorv Singh <apoorv.singh@gin.de>
Convert NXP System Timer Module driver to a native driver.
Timer prescaler in tests is updated because short relative alarms
sometimes give false positives.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Allow developer to use the baremetal Bluetooth functionalities of the
CC13X2 and CC26X2 series SoCs without having to use the full Zephyr
Bluetooth stack.
Signed-off-by: Benedikt Streicher <streicher.b@posteo.de>
Convert NXP SWT watchdog driver to a native driver and extend the
SWT supported functionalities and configuration options.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Convert power management to native drivers retaining existing
functionalities. Presently only SoC reset support and power control
initialization is supported, but these drivers will be extended to
support power management as well.
MC_ME and MC_RGM peripherals are common enough to be reused by other NXP
S32 devices, whereas PMC has specific implementations for each SoC
series.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Allow CONFIG_NRF_APPROTECT_LOCK and
CONFIG_NRF_SECURE_APPROTECT_LOCK with TF-M with all the SOC's
that support TF-M.
Signed-off-by: Markus Lassila <markus.lassila@nordicsemi.no>
Split SIUL2 instance index for the MSCR and IMCR registers as required
by some pins. Pinmux macros definitions in hal_nxp must be updated
accordingly.
Fixes#76147
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
It seems this SiP variant is not sold by espressif directly, but it is
used by the Odroid Go. The Odroid Go documentation calls this a "custom"
model [1].
There already exists a SiP specific device tree include file:
zephyr/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r4.dtsi
[1] https://wiki.odroid.com/odroid_go/odroid_go#specifications
Signed-off-by: Gero Schwäricke <gero.schwaericke@posteo.de>
DMM shall be initialized as early as possible to allow drivers to
use it. For example, uart may need it early since it starts
RX during initilization in some configurations.
Making dmm_init() public and calling it in soc init function.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add support of sys_poweroff API on m46x series.
It could support SPD standby or DPD deep power down mode.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Remove the ‘HAS_MCUX_ACMP’ Kconfig, and also remove it from
driver and soc Kconfig files. It is not needed since we already
depend on 'ACMP' enabled in the dt file, the 'HAS_MCUX_ACMP'
kconfig is a relic of the past before devicetree was stable.
Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
When not using BT, users may want to enable the cpunet core. Until now,
this has been done at board level (so duplicating unnecessary code)
using CONFIG_BOARD_ENABLE_CPUNET. The board-level options were usually
enabled automatically for BT, however, this was unnecessary as BT driver
already takes care of the setup.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Convert pin control, GPIO and external interrupt controller drivers
based on SIUL2 peripheral to native drivers. This must be done in a
single commit to preserve atomicity, as these drivers depend on each
other.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The total number of IRQs for this chip is 110.
Refer to the reference manual table 46 for IRQs.
Signed-off-by: Rahul Arasikere <arasikere.rahul@gmail.com>
Place zephyr library in ILM. This can improve performance.
test:
Print the message 10000 times with 1ms sleep interval to compare the
time difference before and after adding RAM code on the it82002bw evb.
RAM code size save time
original: 1954 bytes
libzephyr.a: +16974 bytes -608ms
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Place kernel library in ILM. This can improve performance.
test:
Print the message 10000 times with 1ms sleep interval to compare the
time difference before and after adding RAM code on the it82002bw evb.
RAM code size save time
original: 1954 bytes
libkernel.a: +8941 bytes -649ms
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Place serial library in ILM. This can improve performance.
test:
Print the message 10000 times with 1ms sleep interval to compare the
time difference before and after adding RAM code on the it82002bw evb.
RAM code size save time
original: 1954 bytes
libdrivers__serial.a: +2282 bytes -226ms
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Initialize TCM and SRAM contents only after a destructive reset (e.g.
PoR reset). SRAM retains content during functional reset through a
hardware mechanism, therefore accesses do not cause content
corruption errors.
Fixes#75912
Signed-off-by: Manuel Argüelles <marguelles.dev@gmail.com>
In S32K1 devices, Arm Systick clock frequency is equal to the
CPU core clock frequency, and its value can be obtained from
devicetree.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
