Currently the code suggests, that setting the SRAM disabling mask to
0 skips powering off SRAM, whereas in fact it's the address of the
mask variable that's checked for NULL. Make this consistent and let
platforms select whether SRAM power down should be selected.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
The IMR is used by the firmware to hold its own copy for hot-booting
and for an "L3 heap," used for slow large allocations like loadable
libraries. The beginning of the L3 heap is currently hard-coded and
now the firmware has grown too large to fit into the dedicated area
so that it gets overwritten by heap allocations. This is a critical
bug that needs an urgent solution, for which we increase the offset,
but a real fix must calculate the L3 heap offset automatically.
BugLink: https://github.com/thesofproject/sof/issues/9308
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
After recent nsim SoCs & boards reorganization the SOC_SERIES_*
config is missing for vpx5 SoC which leads to cmake errors
when building against nsim/nsim_vpx5 configuration.
Fix that and align soc series name in soc.yml
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
The source files required for this features are not present
in the tree for this SOC.
So if CONFIG_PM or CONFIG_POWEROFF are enabled, there would
be a cmake failure.
Let's just indicate these features are not supported in
kconfig.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
CLIC should be the first level interrupt controller because it replaces
the basic RISC-V local interrupt.
The interrupt level in CLIC controls preemption between IRQs, rather than
specifying the number of nested interrupt controllers.
Removed CONFIG_MULTI_LEVEL_INTERRUPTS and the incorrect interrupt level.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
A recent commit fb53d2ef8d ("ace: power: replace pseudo-assembly
movi") contained a bug: the Xtensa "movi" assembly instruction must
be written with the immediate argument already shifted left by 8, the
compiler doesn't do that automatically. This still somehow worked on
MTL but failed on LNL. Fix both occurrences.
Fixes: #75700
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
SARADC was kept enabled to feed RNG entropy peripheral,
adding instability to Wi-Fi connection. So we disable it
before app runs as RNG driver already got initial entropy values.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Getting the required alignment size for memory region node
and device node needs to be handled by a separate macro.
Otherwise alignment of single byte is reported for any region.
Add a test that checks for this particular issue.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
The series-specific Kconfig files were not included, leading
to RTT not being considered available.
Fixes#75511.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
risc-v idle call is being fetched from arch/ implementation.
This soc file is not used and can be removed.
Fixes#75540
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
- Added a flash runner configuration for rw, mcx, lpc, kinetis and imxrt,
used for sysbuild multi-image projects like MCUBoot.
- Solved the mass erase issue.
- The sysbuild project "west flash --erase" command caused
the mass_erase->flash_img1->reset->mass_erase->
flash_img2->reset sequence.
It was fixed to the mass_erase->flash_img1->
flash_img2->reset sequence.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
This removes the prompts for the mt8195 and related kconfigs,
so these cannot be overridden from command line (though
technically they cannot be disabled as they are being selected).
This also prevents them from appearing in the build .config
file as not being set even when we are being for other SoCs.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit fixes a bug with the declaration of the Kconfig option
MEMC_STM32.
The option is defined in two files:
- `drivers/memc/Kconfig.stm32`, wich depends on
- `MEMC`
- `DT_HAS_ST_STM32_FMC_ENABLED`
-`soc/st/stm32/Kconfig.defconfig`, wich depends on
- `MEMC`
- `SOC_FAMILY_STM32`
So, if you have `CONFIG_MEMC=y` in your Kconfig options and you are on a
STM32 SoC, `CONFIG_MEMC_STM32` will be enabled, even if there is no
STM32 FMC enabled.
This Kconfig option causes the driver for the STM32 FMC to be compiled,
regardless of the presence of an enabled node for the FMC.
However, the driver fails to compile if there is no FMC node in the
devicetree. So, if you compile a project with `CONFIG_MEMC=y` on a board
with an STM32 SoC and no enabled FMC, the build will fail.
This commit deletes the Kconfig declaration in the `Kconfig.defconfig`,
as it isn't useful and is the one provoking the bug.
It also add in the `Kconfig.stm32` the compatible `st,stm32h7-fmc`, wich
use the same driver and so need to be enabled by the same Kconfig
option.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
Currently the code in soc.c depends on the MMU of the CPU being enabled,
but this is not enforced. It is thus possible to cause a build error by
manually disabling it (as is required for some LLEXT tests, see #75289).
Make sure this is averted by explicitly selecting ARM_AARCH32_MMU in the
SoC Kconfig.
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
When switching off memory banks we cannot use movi with arbitrary
immediate arguments, they will be converted by the compiler to memory
accesses. Only constants within the allowed range should be used.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Only disable TCP/UDP software checksum if the ethernet
driver enabled. This is to avoid interfere with net tests
which don't need the on board driver to function
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
This commit makes the RV32M1 SoC rely on the default behavior of relying on
the `CONFIG_RISCV_ISA_EXT_*` config options, and removes the
`zephyr_compile_options` override when the standard toolchain is used.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
According to the RV32M1 Series Manual, Rev 1.1 RV32M1 series supports the C
extension, and doesn't support the A extension. Apply fixes accordingly.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Fixes an issue whereby multiple boards would be grouped when using
a regex to group them, and adds missing nRF91 entries to the list
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
The power_down() function attempts to lock the hpsram_mask on-stack
variable in data cache, which causes an exception. Moving it to .bss
by making it static fixes it.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
For SOCs that do not implement a custom `__reset` function,
select `INCLUDE_RESET_VECTOR` so that Zephyr provides a default
implementation that simply jumps to `__initialize`
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
cpuppr can only use slow peripherals and uses RAM3 as RAM so
it does not need to use DMM.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
DMM was enforcing cache line alignment all memory regions, including
those which were not cacheable. Fixing it by using memory attribute
from the device tree to determine if alignment needs to be applied.
Because of that memory usage was significantly increased because
even 1 byte buffers (e.g. for uart_poll_out) was consuming 32 bytes
(cache line size).
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
SYSTEM_WORKQUEUE_STACK_SIZE increase is required to fix not
only BLE Ext Adv (70935), but also other BLE use cases according
STM32WBA HCI driver
Signed-off-by: Alessandro Manganaro <alessandro.manganaro@st.com>
ESP32 requires proper alignment between sections. There are some
scenarios, as reported in #74533, that the section can
get shifted, causing runtime failure.
Making sure SECTION_PROLOGUE is used with ALIGN_WITH_INPUT
will guarantee its consistency.
Fixes#74533
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
- Fix the build issues with the insufficient memory for
the MCUboot.
- Fix the sysbuild with MCUboot tests on all ESP32xx SoCs.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Setting a boolean Kconfig option default to "n" after having set it to "y"
does not make the option disabled. Instead, avoid setting default to "y"
for SoCs known not to have dedicated USB RAM.
Fixes: #73912
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
* Move ctors and init_array from the CPP library
to the kernel library, as this is common for both C
and C++ and it is the kernel who is running it.
* Rename the hidden kconfig option CPP_STATIC_INIT_GNU
STATIC_INIT_GNU instead.
* If STATIC_INIT_GNU is not selected verify there is
constructors left behind.
* Rename common-rom-cpp.ld to common-rom-init.ld
* Rename z_cpp_init_static to z_init_static,
and have the kernel always call it.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Signed-off-by: Keith Packard <keithp@keithp.com>
Replace the MMU initialization call with the new MMU re-initialization
API during the core context restore process in the ACE power management
code.
The previous code was directly calling `xtensa_mmu_init()` upon
restoring the core context, which is not appropriate when the MMU
context may have been preserved during low-power states. The new
`xtensa_mmu_reinit()` API is designed to re-establish the MMU context
without overwriting the existing page table, ensuring that any runtime
changes to the MMU configuration are retained.
Changes made in this patch:
- Removed the call to `xtensa_mmu_init()` from the
`_restore_core_context()` function.
- Added a call to `xtensa_mmu_reinit()` after restoring the
miscellaneous registers.
This update aligns the ACE power management code with the correct MMU
handling procedures when recovering from low-power states, as per the
recent changes in the Xtensa MMU support.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch updates the power control and status register bitfield
definitions in the ACE30 PTL ADSP power management header to match the
documented hardware specifications. The previous definitions contained
discrepancies that did not align with the actual hardware layout,
potentially leading to incorrect assumptions and usage within the
firmware.
Changes made in this patch:
- Renamed 'rsvd0' to 'rsvd4' to accurately represent the reserved bits
starting at bit position 4.
- Removed the 'rsvd6' field, which was incorrectly defined and is not
present in the hardware register layout.
- Adjusted the bit widths for 'ioxpgs' and 'mlpgs' to correctly reflect
the number of bits these fields occupy in the hardware.
- Introduced a new 'rsvd15' field in both 'ace_pwrctl2' and
'ace_pwrsts2' structures to account for the remaining reserved bits,
ensuring the structure sizes accurately represent the full register
width.
By correcting these bitfield definitions, the firmware's power
management code will now be consistent with the actual hardware design,
improving reliability and maintainability of the codebase.
Signed-off-by: Ievgen Ganakov <ievgen.ganakov@intel.com>
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
The implementation of formula, to calculate HFXO INTCAP code,
had a rounding error. That may lead so small deviation of HFXO
clock accuracy.
The IPS formula uses capacitance values in piko Fartd units.
That requires use of floating point data types. To avoid that
implementation of the formula uses femto Farats (1000 smaller unit).
In the former implementation conversion from femto Farad to piko Farad
was done just after reading of the desired capacitance from DTS.
To make sure the calculations are correct the change of unit must be
done at very end. Also rounding must be applied.
Also the formula was split and more comments were added to make the
implementation clear.
The commit fixes the implementation of the IPS formula.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
There were two errors in calculations of LFXO INTCAP code:
- The value provided by DTS files is internal desired capacitance.
The value from DTS has to be "encoded" before use in INTCAP
calculations formula. The formula for encoding is:
CAPACITANCE_CODE = (<desired_value> - 4pF) / 0.5
Subtract of 4 is related with lowest value in the allowed range.
Division by 0.5 is related with change to steps size.
In former code the subtration of 4pF was missing.
- The mid_val calcuation was wrong due offset_k left shift by 4.
It should be left shift by 3 to get total left shift of 9.
That matches the left shift of former part of the equation.
Final integer value was calculated by right shift 10, it should
be right shift 9. Then rounding was done by use of mod by (1 << 10)
It should be mod by (1 << 9) and compared with (1 << 8), that is
half of 0-512 range.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
- Fix flash_fill() for lpc55 and mcxnx4.
- Set FLASH_FILL_BUFFER_SIZE to the minimal size of data
which can be written to a device (by default is only 32).
- Fix the [flash_map.test_flash_area_erase_and_flatten]
failed test of tests/subsys/storage/flash_map.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Time it takes to "erase" one "page" of rram is too low.
Where getting timeouts.
"erase" of rram is done by writing all the words.
one "page" is 4096 bytes meaning 1024 32bit words.
worstcase time it takes to write one 32bit word from
0x00000000 to 0xffffffff is about 42us, giving 42ms
to write 1024 words.
Signed-off-by: Martin Tverdal <martin.tverdal@nordicsemi.no>
Fix linking error due undefined tdata entry.
After #72642, tdata could be undefined due to
missing TLS check.
Fixed#74852
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The generic stack pointer checker in the architecture code is
enough so we can remove the platform specific one. Besides,
xtensa_dc233c_stack_ptr_is_sane() does not do much checking
either.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When TLS is used, `__tdata_start` is PROVIDED by
"thread-local-storage.ld" using absolute address, which
makes it land in wrong flash address. This causes risc-v startup
code to fail during memcpy/memset.
This PR overrides `__tdata_start` to use ADDR, which will
make sure it is placed in DROM region due to AT keyword.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Currently iterable sections as per the documentation are added with
zephyr_linker_sources(SECTIONS ...) after bss/noinit.
This commit allows putting sections after common-rom.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
