Rename symbols so that they reflect purpose of defined memory regions.
Point region symbols to nodes in the DT. Move bogus IDT section before
DSP's ITCM. Move common ROM and RAM sections before the heap.
The move had to be done as these sections and the heap did overlap.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
Add dummy interrupt controller, clock control, pin control, Flexcomm 0,
Flexcomm 2, SAI0, SAI1, SAI2 into SoC's DT. Enable relevant nodes in
board's DT and include pinctrl definitions. Add default LED and button
nodes. Set /hifi4's real frequency. Add memory nodes for device's main
SRAM.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
Add desired Kconfig implications for the mimxrt798s/hifi4 domain. Add
pinctrl_soc.h and set up an include path for it.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
A recent commit inadvertently broke GDB stub on ACE. Revert that
part of the faulty commit.
Fixes: commit cfd6a0673c ("SoC: Intel: ACE: remove unused litelals
parts in interrupt vectors")
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
MCUBoot currently always builds the image as confirmed,
but image confirmation should be explicitly handled by the application
or subsystems.
This change disables the default behavior to avoid premature confirmation
during build time.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The sy1xx SoC enabled CONFIG_RISCV_SOC_EXCEPTION_FROM_IRQ and provided
its own __soc_is_irq implementation. However, the behavior matches the
default implementation, making the override unnecessary.
This commit removes the custom implementation and disables the config
option to remove unnecessary code.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
The __soc_is_irq function is only used when
CONFIG_RISCV_SOC_EXCEPTION_FROM_IRQ is enabled, which is not the case
for any WCH SoC. The implementation is therefore dead code.
Additionally, the implementation matches the default fallback behavior,
so no functional change would occur even if the config were enabled.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
Reorganize and update soc folder files for SDK-independance
Reorganize and update hal_bouffalolab files for SDK-independance
Reorganize and update soc dts files for SDK-independance
Update serial and pinctrl driver files for SDK-independance
Update ai_wb2_12f, bl604e_iot_dvk, and dt_bl10_dvk
to new bl60x support
and fixup openocd config of ai_wb2_12f
Signed-off-by: Camille BAUD <mail@massdriver.space>
litex supports little CSR ordering, also support
it in zephyr. historical the default is big ordering.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
This commit added support for Apollo510 SDIO host driver and
ambiq board configuration in fs_sample and disk_performance
Signed-off-by: Fan Wang <fan.wang@ambiq.com>
Create Kconfig variable NXP_INPUTMUX, which selects the fsl_inputmux
driver. Imply the MCUX component symbol from it. Imply that variable
from the NXP PINT, SmartDMA and LPC DMA drivers and from the mimxrt685s
SoC.
This needed to be done for the mimxrt700_evk/mimxrt798s/hifi4 domain, as
the INPUTMUX peripheral handles IRQ assginments and its driver
(fsl_inputmux) is used directly by the domain's soc.c. Instantiating the
currently dependent drivers (for PINT and SmartDMA) isn's possible nor
reasonable on the said target.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
Configure the CTRLSEL value and the clock pin so that the TRACE pins
work when the TDD gets used.
Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
Added support for the IronSide TDD service which allows configuring and
powering the trace and debug domain of the nrf54h20.
Also provide option to start the trace and debug domain in the soc start
sequence.
Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
Use this approach for a simpler flow and to make relocation of images
into RAM easier.
Also do not force-select CONFIG_XIP (which is a default anyway), since
RP2350 can boot from SRAM.
Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>
Add needed backtrace helpders routines and enable
backtrace for the Xtensa Fusion F1 DSP in the
IMXRT595S.
Signed-off-by: Mike J. Chen <mjchen@google.com>
The default 'near' mode results in zero exit latency ticks, which
prevents `sys_clock_set_timeout` from being called. This causes
the system to remain stuck in deep sleep modes. Use ceiling method
to obtain a nonzero exit latency tick count.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Fixed build fail since 4c93fcd35b.
Fixed test run fail on Ambiq platforms.
Added Ambiq section in the test.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
Transition nrf54h away from the soc specific gpd
(global power domain) driver which mixed power domains, pinctrl
and gpio pin retention into a non scalable solution, forcing soc
specific logic to bleed into nrf drivers.
The new solution uses zephyrs PM_DEVICE based power domains to
properly model the hardware layout of device and pin power domains,
and moves pin retention logic out of drivers into pinctrl and
gpio, which are the components which manage pins (pads).
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add a new shared_heap section. Update the xtensa_soc_mmu_ranges structure
to include a new memory range for the shared heap.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
GIC redistribute and ITS on i.MX 95 is DMA noncoherent, so enable
CONFIG_GIC_V3_RDIST_DMA_NONCOHERENT and CONFIG_GIC_V3_GIC_DMA_NONCOHERENT.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Made some order in the Kconfig's for silabs series 2 socs.
Made a distinction between silabs "generic family" (e.g. xg21) and silabs
"device family" (e.g. efr32mg21).
Signed-off-by: Yishai Jaffe <yishai1999@gmail.com>
Since the change to HWmv2 we do not need to have this options in the
top level anymore. Let's move them into the top level Nordic SOC
Kconfig file.
(Note they moving into into each individual soc Kconfig would
add a dependency on SOC_FAMILY_NORDIC_NRF which is not set for
bsim targets)
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add build asserts for "memory-regions" property in nrf drivers which is
required on targets with DMM for saadc, pdm, pwm, twim, twim_rtio, twis,
tdm, uarte, spim and spis. On targets where the property is not required
the assertion macro expands to nothing.
Signed-off-by: Michał Bainczyk <michal.bainczyk@nordicsemi.no>
Add initial support for i.MX 95 15x15 LPDDR4x EVK board. This board
uses the i.MX 95 15x15 SoC that shares many similarities to the
already supported i.MX 95 19x19 SoC used for the i.MX 95 19x19
LPDDR5 EVK.
This enables Zephyr to boot and run on the i.MX 95 15x15 EVK and
provides a foundation for further peripheral enablement and
application development.
Signed-off-by: Aziz Sellami <aziz.sellami@nxp.com>
Adds SoC support for the STM32C091, and the STM32C092 SoCs
which are part of the STM32C0 series.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Booting the radio core when it is not programmed will typically
cause a reset loop. This can happen when programming multiple
images to a device, and the app core image is programmed before
the radio core.
With this change we avoid the reset loop in that case.
Signed-off-by: Håkon Amundsen <haakon.amundsen@nordicsemi.no>
Add support for generating UICR and associated artifacts in a
format compatible with IronSide SE, to be used for Nordic SoCs
in the Haltium family.
The main feature added with this is the ability to configure certain
global domain peripherals that are managed by the secure domain
through setting UICR.PERIPHCONF. This register points at a blob of
(register address, register value) pairs which are loaded
into the peripherals by IronSide SE ahead of the application boot.
The added helper macros in uicr.h can be used to add register
configurations to the PERIPHCONF. Entries added through these macros
are then extracted by a script, post-processed and placed in a blob
located at specific part of MRAM.
A default PERIPHCONF configuration has been added for the nrf54h20
soc to support the standard BLE use case (matching the configuration
in the soc devicetree).
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
With IronSide SE there is only one defined UICR which is at
the location of the APPLICATION UICR. Update the devicetree
definition accordingly, and use the "nordic,nrf-uicr" compatible
on the node since the domain distinction added by the v2 compatible
is no longer relevant.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
This replaces the legacy SDFW compatible board configuration with the
IronSide SE compatible one, thus removing support for running samples
and tests on nRF54H20 devices with the old firmware.
All applications are expected to work on `nrf54h20dk/nrf54h20/cpuapp`
out of the box. For other board targets, all applications are expected
to boot, but may require additional peripheral configuration in UICR.
Build system support for the new UICR format is to be added separately.
Co-authored-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Add soc_early_init_hook() function to update the SystemCoreClock variable,
which represents the reference clock.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Default MPU configuration marks whole flash area as cacheable. When
reading from an erased section of flash, cache controller may fill cache
lines with ECC corrected data. To prevent this, disable caching on
storage section so that ECC workaround can be applied during reads and
correct data is returned.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
To reduce the SEMC clock to a usable speed we had to divide down
the output clock of System PLL2 PFD1. To do this I had to override
the hardcoded defaults. This commit adds the flexibility to
override them in your board files.
Signed-off-by: Bas van Loon <bas@arch-embedded.com>
Errata ERR050396 causes data corruption if writes happen to TCM memory
so work around it by not marking AXI transaction cacheable. Workaround
taken from NXP SDK example.
Signed-off-by: Bas van Loon <bas@arch-embedded.com>
