Refactor and merge the SoC support files for the Atmel SAM E70 and SAM V71
product series. These SoCs are part of a larger product family (SAM
E70/S70/V70/V71) and share a common set of peripherals.
Support for the two remaining product series (SAM S70/V70) is not part of
this refactoring as these will require further additions to the Atmel HAL.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add initial SoC support for the TI J722s SoC series MCU-domain
Cortex-R5 core.
TRM for J722s: https://www.ti.com/lit/zip/sprujb3
Signed-off-by: Andrew Davis <afd@ti.com>
Add initial SoC support for the TI J722s SoC series MAIN-domain
Cortex-R5 core.
TRM for J722s: https://www.ti.com/lit/zip/sprujb3
Signed-off-by: Andrew Davis <afd@ti.com>
The tp register has been remove from the common RISC-V stack frame so
remove it from the VPR specific variant declared via
SOC_ISR_STACKING_ESF_DECLARE. This saves 4 bytes and allows removing a
lot of padding to get the 16B aligned size.
Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
The CM33 has a XCACHE controller to manage the External
cache. Remove unused Kconfigs as we can use Zephyr API's
to manage the CM33 cache,
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This commit adds MBOX device tree entry for MCXN947.
Adds support for MCXN in NXP ipm and mbox drivers.
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
STM32WB0 series was missed when SoC initialization code was migrated
from SYS_INIT routines to the new soc_early_init_hook method
(c.f. commit c6a03606c2)
Update that series' initialization code to align it with all others.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Add `VECTOR_TABLE_SIZE` Kconfig option to define the number of interrupt
and exception vectors based on the actual hardware specification.
Signed-off-by: Jianxiong Gu <jianxiong.gu@outlook.com>
mbedtls is now used in BLE samples, increasing the stack depth needed
of the calling threads. This was causing stack overflows in several BLE
samples.
Increasing the main stack size for common samples, but also the shell
stack size for samples calling bt API from the shell thread like the
bt shell.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
mbedtls is now used in BLE samples, increasing the stack depth needed
of the calling threads. This was causing stack overflows in several BLE
samples.
Increasing the main stack size for common samples, but also the shell
stack size for samples calling bt API from the shell thread like the
bt shell.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
M33 early init for GPIO for secure access configuration,
so that driver can operate pins.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Chunlei Xu <chunlei.xu@nxp.com>
Move the SAM V71 register name fixup from the SoC code into the PWM driver
next to the other PWM driver fixup.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
The Atmel SAM0 SoC enable peripherals clocks in distinct places: PM and
MCLK. The old devices had defined the peripheral clock enable bit at PM.
On the newer devices this was extracted on a dedicated memory section
called Master Clock (MCLK). This change excludes the dedicated bindings
in favor of a generic approach that cover all cases.
Now the clocks properties is complemented by the atmel,assigned-clocks
property. It gives the liberty to user to customize the clock source
from a generic clock or configure the direct connections.
All peripherals drivers were reworked with the newer solution.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Some platforms require special clock selection options. This could be
made using the already defined assigned-clocks from Linux clocks.
See 93ee800895/dtschema/schemas/clock/clock.yaml (L24)
This introduces the vendor atmel,assigned-clocks and
atmel,assigned-clock-names properties to generalize those conditions
in Zephyr for Atmel sam0 SoC series.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add SPIRAM noinit output sections on related targets so the user can
allocate variables with macros EXT_RAM_BSS_ATTR and EXT_RAM_NOINIT_ATTR.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Some time ago a new shim for nRF UARTE was added (uart_nrfx_uarte2.c)
which used nrfx_uarte.c driver underneath. It was supposed to support
nrf54x platforms. However, later on legacy driver (uart_nrfx_uarte.c)
was extended to support nrf54x platforms and it takes less code size,
has better performance and more features. Shim uart_nrfx_uarte2 will
no longer be supported. As new shim is the default and there is a
Kconfig to pick the legacy shim (CONFIG_UART_NRFX_UARTE_LEGACY_SHIM=y)
it cannot be deprecated in the normal way. Additional Kconfig option
is created (DEPRECATED_UART_NRFX_UARTE_LEGACY_SHIM) which is enabled
if CONFIG_UART_NRFX_UARTE_LEGACY_SHIM=n and it selects DEPRECATED.
A warning was also added to the CMakeLists.txt.
Patch removes use CONFIG_UART_NRFX_UARTE_LEGACY_SHIM in tests.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add new fields to the `esp_image_load_header_t`
* provide IROM and DROM fields to fix debugging features
* extend the header to up to 96 Bytes for future use
Signed-off-by: Marek Matej <marek.matej@espressif.com>
add lpspi clock enablement code
DMA3/4 access different domain is controlled by TRDC, release all
the domain access permission for DMA3/4, and add privilege and secure
information in dma access request signal by DAC module
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
This PR includes changes in all Espressif's SoCs to enable
keeping data in RTC memory after deep-sleep.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This macro is defined in a few places which leads to macro redefinition
error e.g. when compiling prometheus network sample for NPCX boards.
Provide one definition of IS_BIT_SET() in util_macro.h to fix the
problem.
Signed-off-by: Patryk Duda <patrykd@google.com>
Mostly a revert of commit b1def7145f ("arch: deprecate `_current`").
This commit was part of PR #80716 whose initial purpose was about providing
an architecture specific optimization for _current. The actual deprecation
was sneaked in later on without proper discussion.
The Zephyr core always used _current before and that was fine. It is quite
prevalent as well and the alternative is proving rather verbose.
Furthermore, as a concept, the "current thread" is not something that is
necessarily architecture specific. Therefore the primary abstraction
should not carry the arch_ prefix.
Hence this revert.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Moves the LV_DRAW_DMA2D_HAL_INCLUDE to the soc instead of the development
kit since the hal include is the same across all boards using the soc.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
- Add Flash HP support for ra6-cm4, ra6-cm33, ra4-cm33 (except
r7fa4w1ad2cng)
- Add config to set the minimal size of data which can be written
for RA4E2, RA4M2, RA4M3, RA6E1, RA6E2, RA6M1, RA6M2, RA6M3, RA6M4,
RA6M5
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
This change adds support for segger rtt, similar to other supported
soc's. This was lacking when evaluating tracing.
Without this addition the system fails to build, indicating that
HAS_SEGGER_RTT is missing. Adding CONFIG_HAS_SEGGER_RTT in prj.conf is
not allowed.
Signed-off-by: Bart De Vos <bart.devos@verhaert.com>
Add CONFIG_SECOND_CORE_MCUX_LAUNCHER. This Kconfig is only enabled when
using sysbuild targeting the Cortex-M4 core on the RT11xx series, and
results in loading a minimal application to the Cortex-M7 core that
boots the Cortex-M4 core. This makes developing on the M4 core simpler,
as the user can now simply target the core with sysbuild enabled and
flashing the application will work as expected.
Signed-off-by: Daniel DeGrasse <daniel@degrasse.com>
Silabs Series-2 (all the EFR32xg2x chips) use the new clock driver
introduced in commit bda8ae8c3f ("drivers: clock_control: silabs: Add
clock control driver"). This driver get all the configuration from the
Device Tree.
The CMU (Clock Management Unit) options (CMU_HFXO_FREQ, CMU_HFRCO_FREQ,
CMU_NEED_LFXO, CMU_HFCLK_HFXO, etc...) are now only used for Series-0
and Series-1. It does not make sense to bother the users with them.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Although I/DCACHE aren't included under cm33 architecture,
NXP design and integrate Code Cache/Sys Cache for cm33 to
speed up the core execution efficiency.
For the convenience of developers, we believe that software
developers can directly use Code/Sys Cache as arm's I/D Cache.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
If no PCI device with DSP capability is reported, also try to
find compatible devices using PCI_CLASS=40300. This is mostly
useful on preproduction systems where incorrect PCI class data
is reported.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Enable CONFIG_GIC_SAFE_CONFIG by default for Cortex-A Core platforms
as the most targets are to run multiple OSes together with Zephyr on
different Cortex-A Cores.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
For the same reason that this script can't zero the SRAM region (it
spontaneously reboots my 8186 device) we can't scan the SRAM for the
winstream header. It's never there anyway, it lives in .rodata.
This is likely a hardware bug, but as it's an older platform and this
is test code it's probably best to just keep it as a workaround.
Signed-off-by: Andy Ross <andyross@google.com>
Enable a winstream console via the new "STATIC" platform API, and add
code to the loader script to read it (largely cribbed with
modifications from the same feature in cavstool.py, we have nowhere to
share code like this, alas).
The older logging feature is still present as an "oldlog" mode to the
script. We can leave it for a bit as a failsafe (e.g. for debugging
issues with winstream) and remove it later.
Signed-off-by: Andy Ross <andyross@google.com>
