This commit adds the pinctrl driver for WCH CH32V003.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
This puts the syscall helpers into the vector code section, and
is a tiny TLB optimization. Before this, worst case scenario is
that there would 2 instruction TLB misses when both the syscall
helpers and the vector code pages are not in TLB cache. With
this change, there would be at most 1 instruction TLB miss as
now the syscall helper and the vector code (which includes
exception handling code and xtensa_do_syscall()) are now in
the same page, and the same TLB entry.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Most likely there is no point of synchronizing RTC if net core is
not enabled. Same for the bootloader.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Put the default value for BT_AUTO_PHY_UPDATE and BT_AUTO_DATA_LEN_UPDATE
to "n" at SOC level since they cause "controller busy" due to starting
several parallel BLE procedures during connection by
"perform_auto_initiated_procedures" function. At the moment, ST controller
does not support parallelism, i.e. host should not initiate a new procedure
before previous one is completed.
Disable CONFIG_BT_HCI_ACL_FLOW_CONTROL at SOC level.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
The `Kconfig.defconfig` is not good place for put `select PINCTRL`.
Drop `select PINCTL` from `Kconfig.defconfig` and add it at each
driver's Kconfig.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
The MMU mapping in SoC covers 0x0 which prevents catching NULL
pointer accesses. Since there are no hardware registers at
the very first page of memory, we move the starting point one
page later.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This change disables USB debug path at default, in order to prevent SoC
from entering debug mode when there is signal toggling on GPH5/GPH6.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
`_current` is now functionally equals to `arch_curr_thread()`, remove
its usage in-tree and deprecate it instead of removing it outright,
as it has been with us since forever.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
NXP PORT IP instantiations often have different features absent, IE
input buffer, open drain, or slew rate support. Check if the relevant
PCR register bitmasks are defined in the common pin control file, and
define the bitmasks to 0x0 (no effect) if they are not. This allows us
to further consolidate the pinctrl_soc.h headers for SOCs using the PORT
IP.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
These two new ICs are variants of the nRF54L15 with different memory
sizes:
- nRF54L05: 500KB RRAM, 96KB RAM
- nRF54L10: 1022KB RRAM, 192KB RAM
- nRF54L15: 1524KB RRAM, 256KB RAM
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
There are many common options to all ICs of the 54L series. Consolidate
them in a single entry so that they do not need to be re-typed for each
SoC series member.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
add flexspi.c file to get flexspi clock rate.
Enable flexspi1 clock if don't boot from flash.
Use custom fixed mpu_regions.c file to config MPU for CM7
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Split the cached area and assign both parts IROM and DROM meaning. This
is necessary to overcome the esptool section merging issues.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Add `hifive_unmatched//s7` (earlier selected by default, using
`hifive_unmatched`) and `hifive_unmatched//u74` targets.
Define work-area for other 4 cores in openocd.cfg
Update twister platform white/black lists, to support new targets
Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Add `hifive_unleashed//e51` (earlier selected by default, using
`hifive_unleashed`) and `hifive_unleashed//u54` targets.
Define work-area for other 4 cores in openocd.cfg
Update twister platform white/black lists, to support new targets
Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Remove the renesas,ra-pinctrl driver, which is no longer
needed after migrating to the FSP-based implementation.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Since the Option Setting Memory area is set in FSP, the Kconfig value
switches between using the FSP implementation or the existing
Option Setting Memory implementation.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Add a common part for AMD board ACP_6_0_ADSP.
Add support for ACP_6_0_ADSP BOARD,
which represents ACP_6_0 soc.
This has a 1 Xtensa HiFi5 core, with 200-800MHz
1.75 MB HP SRAM / 512 KB IRAM/DRAM,
1 x SP (I2S, PCM), 1 x BT (I2S, PCM), 1 x HS(I2S, PCM), DMIC as
audio interfaces.
Signed-off-by: DineshKumar Kalva <DineshKumar.Kalva@amd.com>
DCDC regulator on nRF54L may not always works as intended.
Tune the fix addressing that.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
DCDC regulator on nRF54L may not always works as intended.
Apply a fix addressing that.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
To configure APPROTECT on nRF54L15 different set of MDK symbols
must be used. Additionally, nRF54L15 does not support loading
APPROTECT configuration from the UICR in runtime.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
The nrfx_gppi module is an abstraction over nrfx_ppi and nrfx_dppi
drivers. It now has a Kconfig option that is separate from nrfx_dppi and
by default it enables all PPI/DPPI instances, if available.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
The hal_nordic revision was updated to bring in NRFX v3.8.0.
Aligned the uses of single-instance API to use multi-instance instead.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
This commit enables the TPIU clock source in Apollo3 and
Apollo4 soc initialization if LOG_BACKEND_SWO is used.
Signed-off-by: Aaron Ye <aye@ambiq.com>
What is changed?
Use CMSIS SystemCoreClock via a dedicated flag instead of using
soc flags.
Why do we need this change?
This change is part of cleaning soc specific code out of arch folder.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
The production version of the nRF54H20 SoC is now available, so remove
the initial Engineering B (EngB) preview version.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Nordic SoCs implement an event system, for which the system can
optimize for low latency/high power or low power.
Add soc level implementation of reference counted API which will
optimize for low latency if any part of the system requires it.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Before that fix the names for UDMA could be misleading.
With that fix the namespace is clear and easy to follow.
Same applies for peripheral addresses and pad config.
Signed-off-by: Sven Ginka <s.ginka@sensry.de>
