Binary Info embeds program meta information in flash,
which can be viewed with RaspberryPi Pico's `picotool`.
Metadata is automatically collected from pinctrl.
It can be override by the Kconfig configurations, such as
```
CONFIG_RPI_PICO_BINARY_INFO_OVERRIDE_PROGRAM_NAME="my program name"
```
When this feature is enabled, pinctrl groups are restricted to
consisting of pins with a single rpi_pico function.
In other words, SPI's MISO and MOSI can be in the same group,
but I2C's SDA cannot be included in this group.
This is rarely an issue in normal use,
and can be resolved by dividing them into separate groups.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Since e150ffb92c, Zephyr only really
supports native_simulator based targets when building native/posix
arch based targets.
So this comment is not relevant anymore. Let's remove it.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Fix the Kconfig dependency for CYW20829 so that enabling the
low-power system timer automatically disables the Cortext-M SysTick
Signed-off-by: Merin George <merin.george@infineon.com>
Add initial support for the Elan em32f967 SoC based on ARM Cortex-M4.
Minimal SoC definition for upstream:
- soc.h, Kconfig, and CMakeLists.txt provided for completeness
- This PR does not implement drivers or UART functionality
Signed-off-by: Johnny Chuang <johnny.chuang@emc.com.tw>
NO_POSIX_CHEATS was a macro used to avoid including the content of a
header (`posix_cheats.h`) which allowed building applications in the
POSIX architecture without the native simulator, avoiding collisions
between some embedded symbols and those from the host C library.
Support for this way of building, and this header and macro were
removed in e150ffb92c, but these users
were forgotten. This was harmless, but let's just clean it up now.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add macro definitions to map generic ADC instance names to hardware
specific SARADC base addresses, enabling driver portability.
Signed-off-by: Ha Duong Quang <ha.duongquang@nxp.com>
Add API for indicating that a deterministic interrupt will occur at
certain point in time in the future. Implementation is ensuring that
there will be no latency due to NVM memory waking up. There are 2
ways of ensuring that:
- setting low latency power mode in RRAMC (higher power consumption
in idle (not available in non-secure build)
- using PPI and GRTC to trigger the RRAMC wake up task right before
an expected interrupt
Module has a pool of GRTC channels and dynamically allocates and
frees those channels when events are registered and unregistered.
If GRTC channel is not available then algorithm falls back to power
mode setting (in secure build).
API offers registering an event using relative and absolute timing.
API can be used from Zero Latency interrupts.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Adjust the pin function bitfield to 4 bits to fit all RZ/V SoCs
(RZ/V2L, V2H, V2N). PFC bitfield of RZ/VH, V2N have 4 bits, so
the current 3-bit width does not fit them.
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Add the SOC_IT8XXX2_RAM_CODE_NOINLINE Kconfig option to prevent
functions marked with __soc_ram_code from being inlined when LTO
is enabled.
This ensures RAM code functions remain in the RAM section instead of
being merged into callers by the compiler.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit enables multi level interrupts:
- Enable multi level interrupts
imx943 is a two level interrupts system and
some interrupts(eg. edma interrupts) depend on irqsteer.
- Increase irq number from 405 to 790
Actually there are 407(IRQ 0 ~ IRQ 406) interrupts
from nvic(first level interrupts),
The second level interrupts are extended by irqsteer,
it extends 32 x 12 = 384 interrupts,
So first level interrupts + second level interrupts
= 407 + 384 = 791(IRQ 0 ~ IRQ 790) interrupts
Signed-off-by: Biwen Li <biwen.li@nxp.com>
S32K566 is a member of the S32K5 family which expands
s32k3 series to higher performance and larger memory.
Zephyr port for S32K5 will support cortex-M7 and cortex-R52
After reset, swt_startup is enabled and starts running,
disable it using the watchdog hook.
Signed-off-by: Ha Duong Quang <ha.duongquang@nxp.com>
Co-authored-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Perform call to LL_DBGMCU_{Dis,En}ableDBGStandbyMode() for STM32WBA series
in the common code, as done with other series. While at it, also add
missing call to LL_DBGMCU_{Dis,En}ableDBGStopMode().
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Update system clock related variables
otherwise Cy_SysLib_Delay or Cy_SysLib_DelayUs are incorrect
Signed-off-by: Kevin Chan <kevin.chan3@infineon.com>
Enabled modes:
idle: SLEEP
suspend: DEEP-SLEEP
standby: POWER-DOWN with CPU retention
OS Time Base: OSTIMER with 32K clock source
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
The boot container was using a non-standard symbol name
`__rom_start_address` for the ROM start address. This symbol
is not defined when build with `-DCONFIG_CMAKE_LINKER_GENERATOR=y`.
This commit use the symbol `__rom_region_start` which is
available for both cases.
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
The arbitrary ordering of ILINK may cause the .last_section
to be placed between the gaps of consecutive sections in the ROMABLE
region.
This commit adds a workaround for Renesas RA devices, which have OFS
registers placed in FLASH. Adding a small .rom_padding section at
the beginning of the ROM_REGION stabilizes the placement order and
ensures that all ROM sections remain within the expected region.
Signed-off-by: Thinh Le Cong <thinh.le.xr@bp.renesas.com>
Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
Switch OFS-related linker sections from GROUP FLASH to GROUP ROM_REGION
to avoid overlapiping placement with .text when build with GNU and
CONFIG_CMAKE_LINKER_GENERATOR=y of RA boards that have OFS in FLASH
Signed-off-by: Thinh Le Cong <thinh.le.xr@bp.renesas.com>
Add parameter to the link_layer_register_isr() to force
or not the link layer isr registration in case of multiple
function calls.
This change fixes the interrupt service when resuming
from a PM standby state.
Update Bluetooth hci_stm32wba.c driver and
IEEE 802.15.4 ieee802154_stm32wba.c driver accordingly.
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
Add initial support for the FocalTech FT9001 ARM Cortex-M SoC including:
- SoC Kconfig and dtsi integration points
- Early init and core setup
- Pinctrl base definitions
This prepares the tree for the FT9001 board and drivers.
Signed-off-by: Robert Cheng <robert.cheng@focaltech-electronics.com>
Configure the GAU (General Analog Unit) clock from T3 PLL 256M with
a divider of 4 to achieve 64MHz, replacing the previous configuration
that used the main clock at 260MHz main clock with a divider of 1.
The GAU ADC has a maximum clock frequency limit of 64MHz. The previous
260MHz clock configuration caused incorrect conversion results when
operating at 12-bit and 14-bit resolutions. Using the T3 PLL 256M
source divided by 4 provides the correct 64MHz clock frequency.
This change also corrects a typo in the comment from "Attack clock"
to "Set 64M GAU clock from T3 PLL 256M and reset".
Signed-off-by: William Tang <william.tang@nxp.com>
Program I2S link for DSP offload, allowing to run DSP tests using
the I2S/SSP interface. On ACE1.5 and older, no additional programming
is required, I2S link is available by default.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
When os_timer is enabled in dts, then os_timer will be used as
OS tick timer.
To make systick as the default OS tick timer, currently os_timer
is not enabled in dts. When users want to use os_timer as
OS tick timer, they need to override the dts.
Improve the method, enable the os_timer is dts, but not enable
in Kconfig by default. If need to use os_timer as OS tick, just pass
CONFIG_MCUX_OS_TIMER=y
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
It is better to let the FLEXSPI2 memory region in the final
linker file be generated from dts, in this way user/developer
can place the data in the region in code more easily.
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
Remove duplicated #include directives within the same
preprocessor scope across the Zephyr tree.
Duplicates inside different #ifdef branches are preserved
as they may be intentional.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The GDB is not compiled by default and a recent change in the slot manager
series contained a typo in ifdef and missed by not compiling the GDB
support.
Fixes: ebb5625bee ("intel_adsp: Add debug slot manager")
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Fix build issue from the below commit:
c520b3da1a
soc: nxp: imx943: m33: add and reuse api to initialize clocks
error: soc_clock_enable defined but not used.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
If a warm reboot is issued (e.g., via mcumgr reset), the sam
controller just hangs because of loop in reboot.c. This can
be devastating if no watchdog is present to reboot the controller.
Signed-off-by: Jaro Van Landschoot <jaro.vanlandschoot@basalte.be>
Move most of the code that is used to interface with IronSide SE on the
nRF54H20/nRF9280 from the soc/nordic directory to the hal_nordic
repository. The interface code is now provided by the new IronSide
support package. Build system code and glue code that makes use of
Zephyr APIs is now located in the modules/hal_nordic directory.
Update the directory path for IronSide SE interface code in
MAINTAINERS.yml to match the move from soc/nordic/ironside to
modules/hal_nordic/ironside.
Also included are some refactoring changes and cleanup to match the new
supporting code.
C code and Kconfigs have been renamed to *ironside_se* / *IRONSIDE_SE*
to match the supporting code changes. Users of these APIs in zephyr
have been updated to match.
Individual configurations for different "IronSide services" have been
removed as the API serialization for all of these is now provided in
a single C file / header file (ironside/se/api.h).
The ironside_boot_report_get() API has been removed. The boot report
structure can be accessed through the IRONSIDE_SE_BOOT_REPORT macro.
Most configs relating to UICR / PERIPHCONF have been moved under the
"IronSide SE" menu to make it clear that these are part of the
IronSide SE interface.
The macros that in uicr.h that were used to add entries to the
PERIPHCONF section have been removed. The supporting code now provides
PERIPHCONF_XYZ() macros that can be used to initialize structures that
go into this section, and the zephyr part now only contains a macro
UICR_PERIPHCONF_ENTRY() that is used to place an arbitrary structure
into the section. The gen_periphconf_entries.py script used to generate
PERIPHCONF entries based on devicetree has been updated to use the new
macro system.
IronSide SE integration code/configs is now guarded by HAS_IRONSIDE_SE.
Note that the UICR build system integration that relies on Sysbuild
remains under the soc/nordic directory for now, but will be moved to
the modules/hal_nordic directory once it is clear how the integration
will look there.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
This patch is a workaround to a know issue when Bluetooth and pm
is activated.
We actually need to set the tx power to the Bluetooth controller
(network coprocessor) before sending power saving request to the
coprocessor.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Power profile property doesn't need to be defined in device three.
It is a configuration value that is defined if we want pm with
Bluetooth and/or Wifi .
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
