Use DRAM region 1 as the default spill area for the `.noinit`
section if appcpu is not present
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
add support for SHUTDOWN operating mode in TI MSPM0 series for power-off
operation. Uses HWINFO for reset cause detection to handle shutdown IO
release on low power wakeup.
Signed-off-by: Sanjay Vallimanalan <sanjay@linumiz.com>
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
TI MSPM0 series supports range of power modes (RUN/SLEEP, STOP, STANDBY)
supporting low power operations. Provides automatic restoration to
RUN mode on wakeup from any low power state.
Signed-off-by: Sanjay Vallimanalan <sanjay@linumiz.com>
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Other targets that define this symbol do it in the Kconfig file, and
gate it with a SOC_ model or series symbol. Defining a default in the
Kconfig.soc instead applies it on every build, which is not desired.
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
Add support for halting the Radio core immediately after reset. This
ensures that a debugger can attach and take control from the very
first instruction.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
PM on the nrf54h20 has minimal utility if power domains and devices
are not managed at runtime, as these prevent the soc from entering
sleep states in the first place. Enable PM_DEVICE by default if PM,
which in turn enables PM_DEVICE_RUNTIME for devices and power
domains.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add image properties data structure to Series 2 binaries.
This data structure is used by the SE or bootloader to enforce
secure boot, and by other tools to extract image information.
Use the app version if set, or fall back to the kernel version
for the image version field. Set image type based on Kconfig
options.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Added support for the IronSide bootmode service which allows requesting
a reboot into secondary firmware boot mode. In this mode, the secondary
configuration defined in UICR is applied instead of the primary one.
The service provides the ironside_bootmode_secondary_reboot() function
that can pass message data to the boot report of the CPU booted in the
secondary boot mode.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Do not directly include and use APIs from ksched.h outside of the
kernel. For now do this using more suitable (ipi.h and
kernel_internal.h) internal APIs until more cleanup is done.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The CMC interface controls the entry and exit of the
CPU's low-power mode and the identification of the wake-up source.
To ensure the normal operation of the system's low-power timing sequence,
when transfer IDLE_RUN to IDLE_SLEEP, it is necessary to ensure
that the system is not awakened by the wake-up source during this stage.
Therefore, an IRQ MASK needs to be set on the CMC
Before the CPU enters the low power mode, a wake up mask needs to be set
according to the situation where the interrupt controller is enabled
at that time.
After the cpu exits the low power mode, resume needs to be performed
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
The insertion of MCUBOOT header will shift the rom code ahead with
0x800 bytes because of memory alignment
Signed-off-by: Andre Heinemans <andre.heinemans@nxp.com>
z_prep_c does not return, mark it as such consistently across
architectures. We had some arches do that, others not. This resolves a
few coding guideline violations in arch code.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not use private API prefix and move to architecture interface as
those functions are primarily used across arches and can be defined by
the architecture.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Cleanup init.c code and move early boot code into arch/ and make it
accessible outside of the boot process/kernel.
All of this code is not related to the 'kernel' and is mostly used
within the architecture boot / setup process.
The way it was done, some soc code was including kernel_internal.h
directly, which shouldn't be done.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Restructure the IronSide boot report interface with enhanced error
reporting and boot context information.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Enables low power stop mode for C0.
Code is taken from F4 family, tested on nucleo-c71rb with
samples/basic/blinky.
Power consumption in run mode 3.7 mA, in stop mode ~87 uA.
Signed-off-by: Tomáš Juřena <jurenatomas@gmail.com>
Fixeszephyrproject-rtos/zephyr#92663
Disabled LFXO via devicetree allows pin 0.00 and 0.01 to work correctly
as gpio by assigning it to the app core instead of peripheral. Removed
deprecated Kconfig options so DT is the only config path now.
Signed-off-by: Ivynya Lu <ivy.lu@level.co>
Add initial support for the Versal Net SoC APU, which is based on
the Arm Cortex-A78 processor. It includes basic wiring for memory
regions, UART, interrupt controller, and timer.
The versalnet_apu.dtsi file defines peripherals shared across the SoC,
while versalnet_a78.dtsi captures peripherals private to the Cortex-A78
processor. These device trees lay the groundwork for further APU-based
development on the Versal Net platform.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
soc power management rework to support power states
removing dependency on ST system clock manager (SCM).
Signed-off-by: Alessandro Manganaro <alessandro.manganaro@st.com>
Add a stupid binding for doc purposes. Terrible coupling when we have to
configure DT in order to generate documentation properly. At least we
get rid of one of the stupid HAS_MCUX_ kconfigs in the process.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Memory region configuration: Configure the flags of each memory
regions present on the device using the mechanism provided by
the xuantie core (chapter 9.2 of E907 manual).
This enables matching more closely the real memory space of
the device than the defaults.
Signed-off-by: Camille BAUD <mail@massdriver.space>
- Update TTC0 clock frequency to 100MHz to align with the Configurable
Example Designs (CED) for kv260 board as used in Vivado.
- Add support for deriving SYS_CLOCK_HW_CYCLES_PER_SEC from Device Tree
Signed-off-by: Ajay Neeli <ajay.neeli@amd.com>
For the ULPM set, it asks for a 10ms ready time for the module.
Use k_busy_wait instead of k_msleep to ensure we wait enough clock cycles.
Signed-off-by: Elmo Lan <elmo_lan@realtek.com>
Apply the same modifications made to the ZynqMP's memory
regions to the cortex_r8_virtual SoC which was mainlined
while the fixes for the ZynqMP were being developed
(minus the OCM mapping, as there's no indication that this
type of memory was considered).
The cortex_r8_virtual appears to be a stripped down copy
of the old qemu_cortex_r5 codebase, therefore, the duplicated
MPU regions have the same flaws as qemu_cortex_r5 or any
actual ZynqMP-based target for that matter.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Overhaul the MPU region definitions that are being
configured when the MPU is set up:
- drop local attribute definitions in favor of those
already provided in arm_mpu_v7m.h
- actually tie the RAM region to the device tree
- set up a (potentially overlapping) R/O region for
.text and .rodata, which hasn't existed so far
- Consider XIP
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Add ethernet support for RA6M4, RA6M5.
Add soc script for generating Renesas Partition Data (RFP file).
Signed-off-by: Ta Minh Nhat <nhat-minh.ta.yn@bp.renesas.com>
Singed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
The high frequency clock was always restored before handling the
interrupts to make sure that the system clock is as expected. However,
the response time to interrupt when we were in EM2 was a between 300 and
600 us. By default, we use the low interrupt latency.
Signed-off-by: Bastien Beauchamp <bastien.beauchamp@silabs.com>
