RT11xx SOC definitions did not enable USDHC controller. Select Kconfig
symbols required to enable it.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
A Cortex-M specific function (sys_clock_isr()) was defined as a weak
function, so in practice it was always available when system clock was
enabled, even if no Cortex-M systick was available. This patch
introduces an auxiliary Kconfig option that, when selected, the ISR
function gets installed. External SysTick drivers can also make use of
this function, thus achieving the same functionality offered today but
in a cleaner way.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
data cache mode setup and enabling should be done only when
CONFIG_ESP_SPIRAM is enabled. Otherwise, memory layout will
conflict with defaults.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
The default config for cavs25 should be a 4 core config. Variants that
have less cores, need to override the config option to a smaller value.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
ARC_HAS_ACCL_REGS should set to y to protect ACCL and ACCH registers
during irq. These registers could be used as GPRs by compilers and
therefore need store/restore during irq.
Signed-off-by: Yuguo Zou <yuguo.zou@synopsys.com>
The device PM callback needs to be used only to suspend/resume devices.
If the system cannot be suspended because UART is in a particular
state, the pm_constraint_set/release API should be used. For NPCX UART,
the chip can't enter low power idle state until UART completes the data
transmission.
This commit changes NPCX UART to use pm_constraint_set/release & fixes
UART lost data from low power idle.
Fix#40621
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This adds the SoC specific bits to enable GDB stub,
mainly the description for the register file, and
memory regions.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
RT600 uses the mcux flexspi driver, which can produce RWW hazards when
calling code linked into flash (such as the logging subsystem). Disable
logging in flexspi driver by default for RT600 series.
Fixes#40744
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit adds support for IMX6SX PWM.
The PWM module is the same module present on the IMX7D and so dts
bindings has been renamed following the one present on linux.
Signed-off-by: Antonio Tessarolo <anthonytexdev@gmail.com>
Some PM cases were not handled correctly (missing default statement).
The error was caught by CI while doing other PM related work.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Since the addition of pinctrl the common folder is added to the Zephyr
include path. This can be re-used to place the soc_nrf_common.h header
in the common folder and include it directly, without the need of
relative paths.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add initial support for nRF pin controller driver. The implementation in
this patch does not yet support any peripheral. Only states
representation and basic driver functionality is introduced.
Note:
The nrf_pin_configure function has been marked as __unused since it may
not be used in certain scenarios until all peripherals are supported by
the pinctrl driver. For example, if only UART/E is supported but the
board does not enable UART, the function will never get called. However,
that board will likely have other peripherals that will gain support in
the future.
Thanks to Marti Bolivar for bindings documentation.
Co-authored-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add initial version for STM32 pinctrl driver. Driver has been written
re-using many of the already existing parts in
drivers/pinmux/pinmux_stm32.c.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The IDC driver was written for Tiger Lake era devices, but works fine
on the earlier hardware too. Make it selectable; if you don't
configure IPM_CAVS_IDC, then you get the new driver.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There was an attempt in the old code to express this as a formal
protocol with a proper field definitions, etc... But in fact no such
protocol really exists. This scheme is only used in one place to send
one specific message to code fixed in ROM on legacy devices that only
knows how to recognize this specific value. And 2.5 and later
hardware are moving away from it anyway.
Just express it directly, and explain in comments.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The CAVS_IDC_IPM driver happens to be used only on non-2.5 hardware,
but it's best to be clear in the conditional compilation when we're
talking about hardware-dependencies and when we mean software
configuration. This was mixed up in a few spots.
Also fix a warning that creeps in on non-default drivers choices about
an undeclared ipm function.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
While the linker scripts for these platforms had diverged in form, the
behavior remained compatible. Link all cAVS devices with the same
linker script included from the common directory (it's a verbatim copy
of the cavs_v25 script).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
While technically this file can change for any instantiation of Xtensa
hardware, in practice all these devices have identical interrupts
setups. These files were duplicates, so there's no value in keeping
them in per-sub-soc directories. (Really we should wire it up so that
the generator gets run automatically with the build, but that will
need to wait for a rework of interrupt entry).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
All the in-use contents of these files have now been moved to the
intel_adsp core, and they are configured via devicetree and kconfig.
Remove the legacy headers.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These two register blocks are defined in the platform layers, but
never change (except on 1.5 where they don't exist). I don't want to
write a full devicetree interface for them as I can't find good docs
currently. They are used only at system initialization, so move the
definitions to the single file where they're used. In the longer term
we will want to move at least the GPDMA setup into a driver anyway.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These registers were hardwired in the platform layer. Move to
devicetree, via a struct interface that looks like the pre-existing
shim layer.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These values (used to arrange the bootloader within IMR memory) are
mostly computed or fixed to values that don't chagne between
platforms. Only the manifest address and the location of the data
section change. Put those in kconfig, move the rest to the global
header.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The bootloader code on this SOC has its own cmake rules, which means
it doesn't get the Zephyr-specific magic from the toolchain layer and
the code needs to handle fixups manually. (Specifically: we have a
xcc_missing_defs.h header to provide gcc symbols that xcc doesn't
have, and assembly needs to be built with _ASMLANGUAGE so headers
don't include C syntax.)
Long term the right solution here is to build the bootloader as part
of the Zephyr binary.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The locations of the memory windows within the reserved SRAM region
was being construted via a bunch of magic numbers referencing
(potentially historical?) SOF usage of those areas. But Zephyr only
ever touches two of these windows, and only cares about the sizes and
offsets. The complexity was hurting and not helping (especially since
there was no attempt made to unify these values with the ones that are
actually live in the SOF tree).
Replace with kconfig variables that simply specify the offset. Only
one platform has a nonstandard layout anyway. That allows SOF to move
things around in a clean way if it wants. Ideally we should be
presenting a proper API for managing this region, though.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Same as for the HP-SRAM memory region. It's already exposed in
devicetree, so take the per-platform values out (including some dead
code on 2.5) and put them in a global header.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The platform layer (except cAVS 1.5, which computed it via alternate
means as an offset on other stuff) was specifying the entry point as
an explicit address needlessly. In fact the linker scripts already
are written to place the entry point at the first address of linkable
RAM, which is already available as the RAM_BASE symbol.
Unify.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These registers are identical on all platforms, the only difference
being that cAVS 1.5 places them at a different address.
Create a devicetree node to track the register block, and replace the
platform header code with a global API defined once (it works like the
pre-existing shim struct).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There is a diverged definition for SRAM_REG_FW_END, which exists to
prevent the Zephyr window initialization from changing values that
were already set by the ROM or bootloader (though this is incomplete,
as we're not ensuring the memory is actually the same space except by
convention; we also don't have any Zephyr-side visibility as to the
content of this struct).
That was silly; the only thing worse than one magic number is four
magic numbers in different files. Write a formula that works for all
the platforms and put it in the C file where it's used.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There was a divergent set of definitions for a "RAM" region for the
benefit of memory layout in the platform headers. In fact there was
only one platform dependence (cAVS 1.5 has 32k instead of 64k
reserved). Put that into kconfig in a single place, and add a warning
that this is a trap region with hidden dependencies in both Zephyr and
SOF. Good enough until we clean this up and make everything visible
to the linker.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There are multiple "fake" (not part of image) sections needless linked
to explicit addresses right now. This should be cleaned up, but in
the meantime let's at least put their definitions all in one place so
they aren't cut/pasted into every platform.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These macros (LPSRAM_MASK, SRAM_BANK_SIZE, HOST_PAGE_SIZE) never
change, and are always used in just one file.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The HP SRAM block address and size is specified in four different ways
(devicetree, "SRAM_*", "HP_SRAM_*" and "L2_SRAM_*" macros). Unify,
moving the C definition (which just fetches it from dts) to a single
header and out of the platform layer.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This was an abstraction layer without a purpose. All existing
platforms have the same (LXn core) layout. When we need to split this
out in the future, the right thing will be to use the values already
provided by the platform core-isa.h and not duplicate them anyway.
Think of this as a first step to an incoming rework of the Zephyr
Xtensa interrupt entry generation, which is long overdue.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The generic bootloader code used a per-device "platform.h" file
imported from SOF. These turn out to have very little actual content.
Move them to the core directory in a single header for now, pending
some rework to place the settings in devicetree.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The linker script (and a little bit of SOF) still has support for an
older mechanism for bootstrapping secondary cores by copying code into
lp-sram from a "manifest" emitted by the linker. This actually never
worked in Zephyr, and we've implemented a different scheme that uses a
small runtime-copied trampoline instead.
Remove.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Each platform was defining its own shim.h header, with slightly
variant field definitions, for a register block that is almost
completely compatible between versions. This is made worse by the
fact that these represent an API imported fairly early from SOF, the
upstream version of which has since diverged.
Move the existing shim struct into a header ("cavs-shim.h") of its
own, remove a bunch of unused symbols, fill in definitions for some
registers that were left out, correct naming to match the hardware
docs in a few places, make sure all hardware dependencies are source
from devicetree only, and modify existing usage to use the new API
exclusively.
Interestingly this leaves the older shim.h header in place, as it
turns out to contain definitions for a bunch of things that were never
part of the shim register block. Those will be unified in separate
patches.
Finally: note that the existing IPM_CAVS_IDC driver (soon to be
removed from all the intel_adsp soc's) is still using the old API, so
redeclare the minimal subset that it needs for the benefit of the
platforms in transition.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Reorganize the initialization code to cleanly separate the platforms
and clarify which code is common. The #if'ery was sort of a mess.
This is in preparation for an incoming patch that unifies the shim
register definitions across platform variants.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Misc cleanup, no non-trivial logic changes.
Swap in new ("rsr <reg>, REGISTER_NAME") syntax for Xtensa SR's in
place of inconsistent usage of the older one ("rsr.REGISTER_NAME
<reg>").
Remove the legacy handling of !KERNEL_COHERENCE cases for allocating
the cpu start record. That has long been a requirement of
multiprocessor code on this platform.
Remove the synchronous testing of the "alive" flag in
arch_start_cpu(). Nothign about that API is intended to be
synchronous, and in fact the Zephyr SMP layer is already doing the
same trick.
Remove some vestigial dead code at the end of z_mp_entry(). It was
apparently intended to handle the case where a CPU function returned,
but that's not legal anyway. And it was only enabled in the case
where there was only one CPU anyway, which was an impossible situation
(you can't evercall arch_start_cpu() successfully on a system with
only one core, for obvious reasons -- the only core is already
running!). Replace with an assertion.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The cAVS bootloader code (for... somewhat silly reasons) doesn't build
via the same paths as regular Zephyr object files, so it wasn't
getting the _ASMLANGUAGE define. That meant that Zephyr headers
defining BIT() were using syntax incompatible with some assemblers
(specifically the Cadence xcc assembly; current gas versions were
fine).
Not 100% sure this is the best spot to put this, but the root fix is
to get the bootloader building into the same link as the rest of
Zephyr anyway.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Program flow will behave incorrectly (memory and instruction fetches
return invalid data) if Flexspi is accessed by the Flexspi driver while
being used as XIP memory by the Cortex M7.
Set logging to disabled by when XIP mode is used in the memc and
flexspi drivers, and warn the user if they attempt to enable it.
Fixes#40133
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable pinctrl by default, since it is an essential component on almost
every firmware. Inclusion of series defconfig has also been guarded with
SoC availability (was missing).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add a pin control driver for GD32 SoCs using the AFIO model.
Thanks to Gerson Fernando Budke for testing and implementation
suggestions.
Co-authored-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
