Commit graph

503 commits

Author SHA1 Message Date
Kumar Gala
f2fa572561 entropy: remove Kconfig.defconfig* setting of entropy drivers
Now that entropy drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-09 23:37:33 -05:00
Kumar Gala
e31cba26be flash: remove Kconfig.defconfig* setting of flash drivers
Now that flash drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-09 12:27:28 +02:00
Gerard Marull-Paretas
736a1a9113 soc: riscv: remove usage of SOC_ERET
All SOC_ERET definitions expand to the mret instruction (used to return
from a trap: exception or interruption). The 'eret' instruction existed
in previous RISC-V privileged specs, but it doesn't seem to be used in
Zephyr (ref. RISC-V Privileged Architectures 3.2.2).

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-04 13:44:48 +02:00
Kumar Gala
6298b27725 watchdog: remove Kconfig.defconfig setting of watchdog drivers
Now that watchdog drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Typically the Kconfig.defconfig* will blindly enable a
watchdog and not respect the devicetree state of the watchdog.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-03 18:30:17 -05:00
Kevin Wang
25b4bd186d soc: riscv: riscv-privilege: andes_v5: ae350: MP_NUM_CPUS default value
Overlay zephyr kernel MP_NUM_CPUS from 1-8 (default 1-4)
for supporting 8 cpu cores.

Signed-off-by: Kevin Wang <yunkai@andestech.com>
2022-08-03 05:00:14 +01:00
Jimmy Zheng
4d00ee0738 soc: riscv: riscv-privilege: andes_v5: set default tick for XIP
Andes fpga base AE350(60M Hz) may fail in XIP because it causes hundreds
of cycles to fetch instructions, decreased tick rate to 100 if CONFIG_XIP.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2022-08-03 04:59:34 +01:00
Jimmy Zheng
47b6d33fd2 soc: riscv: riscv-privilege: andes_v5: added SMU register macros
Added Wake-Up Reset Status Register macros for hwinfo driver usage.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2022-08-03 04:59:34 +01:00
Jimmy Zheng
97fa8407cf soc: riscv: riscv-privilege: andes_v5: reworked Andes L2 cache
Detect the L2 cache at runtime and removed unused Kconfig
CONFIG_SOC_ANDES_V5_L2_CACHE.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2022-08-03 04:59:34 +01:00
Jimmy Zheng
500fafa921 soc: riscv: riscv-privilege: andes_v5: refined Andes PMA
Refined return value of pma_init() and skip PMA configuration if the region
size is 0.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2022-08-03 04:59:34 +01:00
Kumar Gala
7e8a312c6b adc: remove Kconfig.defconfig setting of ADC drivers
Now that ADC drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the ADC.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-02 15:51:43 -05:00
Gerard Marull-Paretas
741bfedeab soc: riscv: mpfs: remove unused definition
RISCV_MTIMECMP_BY_HART (machine timer related) is not used, so remove
it.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-02 09:12:31 +02:00
Gerard Marull-Paretas
418ad7d443 soc: riscv: remove unused RISCV_MTIME(CMP)_BASE and IRQ definitions
The RISC-V machine timer base addresses and IRQ are now obtained from
Devicetree.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-02 09:12:31 +02:00
Gerard Marull-Paretas
6de9fcf315 soc: riscv: gd32vf103: use nuclei,systimer compatible
After some analysis I found out that there's no machine timer provided
by the "riscv" vendor. There are some specs for the mtime/mtimecmp
registers (this is why we can have a single driver), but the actual
register layout or implementations differ amongst vendors. GD32 uses the
Nuclei implementation, named "system timer" in their documentation. This
patch aligns with vendor specs.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-02 09:12:31 +02:00
Kumar Gala
5c57a36f9d i2c: remove Kconfig.defconfig setting of I2C drivers
Now that I2C drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the I2C.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-01 18:01:44 +02:00
Gerard Marull-Paretas
1be9af6794 soc: riscv: remove unused RISCV_RAM_BASE|SIZE definitions
The definitions are not used anywhere in Zephyr nor in modules, so
delete them.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-07-28 20:51:31 +02:00
Gerard Marull-Paretas
98e5df0204 soc: riscv: sifive-freedom: remove unused 'always on domain' defines
The definitions under "Always ON Domain" are not used, remove them.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-07-28 20:50:57 +02:00
Gerard Marull-Paretas
307415664d soc: riscv: sifive-freedom: remove unused pinmux definitions
These definitions are now part of the pinctrl DT headers, remove them
from soc.h

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-07-28 20:50:57 +02:00
Gerard Marull-Paretas
a0bdb489a2 soc: riscv: miv: remove unused PRCI base address
Base address for PRCI is not used anywhere in the tree for this
platform. Again, if ever used, this needs to come from DT.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-07-28 20:50:57 +02:00
Gerard Marull-Paretas
5fb43647dd soc: riscv: miv: remove unused GPIO definitions
There is no GPIO driver for such platform, and if it existed, all this
information should be provided in Devicetree (as other platform drivers
like UART do).

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-07-28 20:50:57 +02:00
Gerard Marull-Paretas
a58035fbd1 soc: riscv: gd32vf103: remove unnecessary content from soc.h
- zephyr/toolchain.h is not needed
- gd32vf103.h is not needed (no CMSIS here)
- undefinition not needed, HAL is now patched with a prefix for this
  definition.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-07-28 20:50:57 +02:00
Gerard Marull-Paretas
93ba241b57 soc: riscv: gd32vf103: add missing include
SystemInit is declared in gd32vf103.h. Include it instead of relying on
indirect soc.h includes.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-07-28 20:50:57 +02:00
Carlo Caione
0d3c70ea97 arch: riscv: Remove useless functions declaration
We already have riscv_clic.h and riscv_plic.h, no need to have the same
declarations in soc_common.h as well.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-27 18:44:35 +02:00
Kumar Gala
65e1c6fb1e pwm: remove Kconfig.defconfig setting of PWM drivers
Now that PWM drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the PWM.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-27 18:43:54 +02:00
Kumar Gala
960f2f1a37 spi: remove Kconfig.defconfig setting of SPI drivers
Now that SPI drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the SPI.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-27 09:49:00 +02:00
Kumar Gala
9a501e0922 serial: remove Kconfig.defconfig setting of serial drivers
Now that serial drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the serial.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-26 09:29:24 -05:00
Kumar Gala
600d749cf3 gpio: remove Kconfig.defconfig setting of GPIO drivers
Now that gpio drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the GPIO.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-26 08:49:38 +02:00
Kumar Gala
df0c6d4c43 sensors: remove defconfig setting of sensor drivers
Now that sensor drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the sensor.
Additionally we can get problems with prj.conf/defconfig
as well getting incorrectly overridden.

Fixes #48198

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-25 09:40:14 +02:00
Ruibin Chang
32906a18ec ITE soc/it8xxx2: disable unused integrated cc module
ITE EC chip it81202 and it81302 both have embedded integrated
pd module (support two usbpd ports), this is different from
standalone TCPC. To prevent cc pins leakage, we disable not
active ITE USBPD port cc modules, then cc pins can be used
as gpio if needed.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2022-07-22 10:32:12 +02:00
Tim Lin
04c6d7569f ITE: drivers/i2c: Add command queue mode
Adding command queue mode can reduce the time between each byte to
improve the I2C bus clock stretching during I2C transaction.

I2C command queue mode of it8xxx2 can support I2C APIs including:
i2c_write(), i2c_read(), i2c_burst_read.

Test:
1. tests\drivers\i2c\i2c_api --> pass
2. Reading 16 bytes of data through i2c_burst_read() can reduce
   0.72ms(2.54ms->1.82ms) compared to the original pio mode when the
   frequency is 100KHz.
3. krabby platform can boot normally.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2022-07-13 10:15:32 +02:00
Carlo Caione
541024eb43 riscv: litex-vexriscv: Add missing header
soc.h is using sys_read* functions. Add the proper header for that.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-11 14:31:39 +02:00
Carlo Caione
5d104f20ab riscv: Introduce API for CLIC and PLIC
Introduce a new interface for CLIC and PLIC to be used by the drivers.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-11 14:31:39 +02:00
Carlo Caione
56466a14e1 riscv: Decouple CLIC and PLIC
Try to decouple CLIC and PLIC as much as possible.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-11 14:31:39 +02:00
Carlo Caione
31c5dc2230 Kconfig: Introduce RISCV_HAS_CLIC
Introduce a new RISCV_HAS_CLIC symbol for platforms using CLIC,
reorganize the Kconfigs and make the Nuclei ECLIC depending on the new
symbol.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-11 14:31:39 +02:00
Carlo Caione
fbe3436b36 esp32c3: Avoid circular header inclusion
Include arch.h from a different location to avoid missing symbol errors.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-07 10:00:20 +02:00
Carlo Caione
0e788b89a6 riscv: Use IRQ vector table for vectored mode
For vectored interrupts use the generated IRQ vector table instead of
relying on a custom-generated table.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-07 10:00:20 +02:00
Ruibin Chang
dc3f29f67f ITE tests/kernel/sleep: tune CONFIG_SYS_CLOCK_TICKS_PER_SEC down
We need more time to run codes because of the performance,
so I tune CONFIG_SYS_CLOCK_TICKS_PER_SEC down to reduce
the times of running k_usleep(1), then it can pass test_usleep().

Verified by follow test pattern:
west build -p always -b it8xxx2_evb tests/kernel/sleep

fixes #46208

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2022-07-05 11:29:43 +00:00
Glauber Maroto Ferreira
fb919a75ba soc: esp32/s2/c3: pinctrl: update pin init macros
Updates pin initialization macros to make use
of pin grouping.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2022-07-01 16:22:18 +00:00
Alex Kolosov
4a52bc22b6 soc: riscv: telink_b91: add dfu related configurations for b91 platform
Modify Telink b91 config files and linker script with necessary config
settings required for DFU.

Signed-off-by: Alex Kolosov <rikorsev@gmail.com>
2022-06-24 20:25:33 +02:00
Keith Packard
01187b92a2 soc/it8xxx2: Place arithmetic funcs in .text section
Placing these in the __ram_code section generates a relocation error when
building with toolchain version 0.14.1, moving them back to .text fixes
that (presumably with a performance penalty).

Signed-off-by: Keith Packard <keithp@keithp.com>
2022-06-22 13:15:55 +02:00
Sylvio Alves
54ca96f523 soc: esp32: opt to make device handles in dram
ESP32 linker loader needs all sections to be align correctly.
When MCUBoot is enabled, device handles provide by device-handles.ld
does not make the ALIGN(4) at the end, which breaks the loader
initialization. This PR make sure that this particular section
is placed in DRAM instead.

For now this is a workaround until this can be handled in loader script.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-06-22 12:27:43 +02:00
Sylvio Alves
8e04acab3b linker: esp32: fix flash linking reference
Referenced spi_flash_rom_patch.c object was wrongly
linked, which can cause crash due to flash cache disabled
operation.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-06-22 12:27:32 +02:00
Carlo Caione
741b9dc65d riscv: Rename __irq_wrapper to _isr_wrapper
For some reasons RISCV is the only arch where the vector table entry is
called __irq_wrapper instead of _isr_wrapper. This is not only a
cosmetic change but Zephyr expects the common ISR handler to be called
_isr_wrapper (for example when generating the IRQ vector table).

Change it.

find ./ -type f -exec sed -i 's/__irq_wrapper/_isr_wrapper/g' {} \;

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-06-21 20:27:20 -04:00
Dino Li
e1c5222afd soc: it8xxx2: add soc variants
Currently there are two soc variants (IT81202BX and IT81302BX) on
it8xxx2 series. The IT81202BX is 128-pin package (GPIO K and L groups
aren't bonding with pad).
This makes soc variant configurable and apply corresponding configuration
for a soc.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2022-06-20 10:25:08 +02:00
Krzysztof Chruscinski
c5f2cdef09 logging: Remove logging v1 from the logging
Remove v1 implementation from log_core and all references in the tree.
Remove modules used by v1: log_list and log_msg.
Remove Kconfig v1 specific options.
Remove Kconfig flags used for distinction between v1 and v2.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2022-06-16 10:51:15 -04:00
Gerard Marull-Paretas
e928300f90 soc: remove unused UART_DEFAULT_REG_INTERVAL definitions
Information is now provided in Devicetree by each ns16550 instance.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-15 16:59:02 -05:00
Gerard Marull-Paretas
5a565ece45 soc: riscv-ite: remove redundant <zephyr/zephyr.h> includes
Files including <zephyr/kernel.h> do not have to include
<zephyr/zephyr.h>, a shim to <zephyr/kernel.h>.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-15 09:13:11 +02:00
Dino Li
68fde3ceeb soc: it8xxx2: optimize __soc_handle_irq and __soc_is_irq functions
This reduces code size slightly.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2022-06-14 09:31:14 +02:00
Dino Li
86c45b7e12 soc: it8xxx2: The "M" extension is disabled by default
There is a mul instruction bug.
The bug may cause instructions of writing back CPU GPR (e.g mv a0,s2)
which following the mul instruction to fail.
This patch disables the 'M' extension and overwrite integer
multiplication and division arithmetic library routines with using
hardware multiplication and division and nop instructions.
This will ensure that there is no write back GPR instruction to follow
mul instruction to avoid the bug.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2022-06-08 12:43:51 +02:00
Yuriy Vynnychek
49d873603c soc: riscv: telink_b91: B91 BLE controller support (linker aes_data)
Introduced new aes_data linker section used by B91 BLE controller.

Signed-off-by: Yuriy Vynnychek <yura.vynnychek@telink-semi.com>
2022-06-05 14:45:10 +02:00
Carlo Caione
10061efdc4 riscv: Rework and cleanup Kconfig
This patch is doing several things:

- Core ISA and extension Kconfig symbols have now a formalized name
  (CONFIG_RISCV_ISA_* and CONFIG_RISCV_ISA_EXT_*)

- a new Kconfig.isa file was introduced with the full set of extensions
  currently supported by the v2.2 spec

- a new Kconfig.core file was introduced to host all the RISCV cores
  (currently only E31)

- ISA and extensions settings are moved to SoC configuration files

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-06-05 14:28:42 +02:00