Now that entropy drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that flash drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
All SOC_ERET definitions expand to the mret instruction (used to return
from a trap: exception or interruption). The 'eret' instruction existed
in previous RISC-V privileged specs, but it doesn't seem to be used in
Zephyr (ref. RISC-V Privileged Architectures 3.2.2).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Now that watchdog drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
watchdog and not respect the devicetree state of the watchdog.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Andes fpga base AE350(60M Hz) may fail in XIP because it causes hundreds
of cycles to fetch instructions, decreased tick rate to 100 if CONFIG_XIP.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Now that ADC drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the ADC.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
After some analysis I found out that there's no machine timer provided
by the "riscv" vendor. There are some specs for the mtime/mtimecmp
registers (this is why we can have a single driver), but the actual
register layout or implementations differ amongst vendors. GD32 uses the
Nuclei implementation, named "system timer" in their documentation. This
patch aligns with vendor specs.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Now that I2C drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the I2C.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Base address for PRCI is not used anywhere in the tree for this
platform. Again, if ever used, this needs to come from DT.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
There is no GPIO driver for such platform, and if it existed, all this
information should be provided in Devicetree (as other platform drivers
like UART do).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
- zephyr/toolchain.h is not needed
- gd32vf103.h is not needed (no CMSIS here)
- undefinition not needed, HAL is now patched with a prefix for this
definition.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
SystemInit is declared in gd32vf103.h. Include it instead of relying on
indirect soc.h includes.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
We already have riscv_clic.h and riscv_plic.h, no need to have the same
declarations in soc_common.h as well.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Now that PWM drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the PWM.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that SPI drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the SPI.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that serial drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the serial.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that gpio drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the GPIO.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that sensor drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the sensor.
Additionally we can get problems with prj.conf/defconfig
as well getting incorrectly overridden.
Fixes#48198
Signed-off-by: Kumar Gala <galak@kernel.org>
ITE EC chip it81202 and it81302 both have embedded integrated
pd module (support two usbpd ports), this is different from
standalone TCPC. To prevent cc pins leakage, we disable not
active ITE USBPD port cc modules, then cc pins can be used
as gpio if needed.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Adding command queue mode can reduce the time between each byte to
improve the I2C bus clock stretching during I2C transaction.
I2C command queue mode of it8xxx2 can support I2C APIs including:
i2c_write(), i2c_read(), i2c_burst_read.
Test:
1. tests\drivers\i2c\i2c_api --> pass
2. Reading 16 bytes of data through i2c_burst_read() can reduce
0.72ms(2.54ms->1.82ms) compared to the original pio mode when the
frequency is 100KHz.
3. krabby platform can boot normally.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Introduce a new RISCV_HAS_CLIC symbol for platforms using CLIC,
reorganize the Kconfigs and make the Nuclei ECLIC depending on the new
symbol.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
For vectored interrupts use the generated IRQ vector table instead of
relying on a custom-generated table.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
We need more time to run codes because of the performance,
so I tune CONFIG_SYS_CLOCK_TICKS_PER_SEC down to reduce
the times of running k_usleep(1), then it can pass test_usleep().
Verified by follow test pattern:
west build -p always -b it8xxx2_evb tests/kernel/sleep
fixes#46208
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Placing these in the __ram_code section generates a relocation error when
building with toolchain version 0.14.1, moving them back to .text fixes
that (presumably with a performance penalty).
Signed-off-by: Keith Packard <keithp@keithp.com>
ESP32 linker loader needs all sections to be align correctly.
When MCUBoot is enabled, device handles provide by device-handles.ld
does not make the ALIGN(4) at the end, which breaks the loader
initialization. This PR make sure that this particular section
is placed in DRAM instead.
For now this is a workaround until this can be handled in loader script.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Referenced spi_flash_rom_patch.c object was wrongly
linked, which can cause crash due to flash cache disabled
operation.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
For some reasons RISCV is the only arch where the vector table entry is
called __irq_wrapper instead of _isr_wrapper. This is not only a
cosmetic change but Zephyr expects the common ISR handler to be called
_isr_wrapper (for example when generating the IRQ vector table).
Change it.
find ./ -type f -exec sed -i 's/__irq_wrapper/_isr_wrapper/g' {} \;
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Currently there are two soc variants (IT81202BX and IT81302BX) on
it8xxx2 series. The IT81202BX is 128-pin package (GPIO K and L groups
aren't bonding with pad).
This makes soc variant configurable and apply corresponding configuration
for a soc.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Remove v1 implementation from log_core and all references in the tree.
Remove modules used by v1: log_list and log_msg.
Remove Kconfig v1 specific options.
Remove Kconfig flags used for distinction between v1 and v2.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Files including <zephyr/kernel.h> do not have to include
<zephyr/zephyr.h>, a shim to <zephyr/kernel.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
There is a mul instruction bug.
The bug may cause instructions of writing back CPU GPR (e.g mv a0,s2)
which following the mul instruction to fail.
This patch disables the 'M' extension and overwrite integer
multiplication and division arithmetic library routines with using
hardware multiplication and division and nop instructions.
This will ensure that there is no write back GPR instruction to follow
mul instruction to avoid the bug.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
This patch is doing several things:
- Core ISA and extension Kconfig symbols have now a formalized name
(CONFIG_RISCV_ISA_* and CONFIG_RISCV_ISA_EXT_*)
- a new Kconfig.isa file was introduced with the full set of extensions
currently supported by the v2.2 spec
- a new Kconfig.core file was introduced to host all the RISCV cores
(currently only E31)
- ISA and extensions settings are moved to SoC configuration files
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Update the new API to use K_USER as the flags for both
CONFIG_USERSPACE and CONFIG_TEST_USERSPACE. Also, fix the linker
script to properly include the suites, tests, and rules.
Fixes#44108
Signed-off-by: Yuval Peress <peress@google.com>
This commit introduces changes in three places in order to fix the
problem with timer-related tests on FE310-based boards:
* tests/kernel/sleep/kernel.common.timing
* tests/kernel/tickless/tickless_concept/kernel.tickless.concept
* tests/kernel/workq/work_queue/kernel.workqueue
The first change is the modification of the SYS_CLOCK_HW_CYCLES_PER_SEC
value back to 32768 Hz to match FE310's datasheet description.
The second change is CLINT frequency reduction in Renode simulation
model to 16 MHz to correspond with the oscillator frequency given by the
FE310's datasheet and the HiFive1 board schematic. This fixes the first
two tests.
The last change is reducing the MIN_DELAY define to 100. This causes the
RISC-V machine timer driver to update the mtimecmp register more often,
which in turn addresses the `work_queue/kernel.workqueue` problem with
work items finishing prematurely, causing the above-mentioned test to
fail.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
ARCH_HAS_USERSPACE and ARCH_HAS_STACK_PROTECTION are direct functions
of RISCV_PMP regardless of the SoC.
PMP_STACK_GUARD is a function of HW_STACK_PROTECTION (from
ARCH_HAS_STACK_PROTECTION) and not the other way around.
This allows for tests/kernel/fatal/exception to test protection against
various stack overflows based on the PMP stack guard functionality.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
PHY TX power configuration must be added into soc level.
It was previously hardcoded in hal_espressif, which was removed.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The GigaDevice HAL defines CAN_MODE_NORMAL, which conflicts with the
zephyr/drivers/can.h header definition. Undefine it in soc.h.
Fixes: #45611
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Current Espressif porting requires standard include as
part of hal implementation. compiler_flags.cmake checks for
variant name to keep those stdinc in build.
Instead of using variant name as check, use this new CONFIG
to make it clear and to allow having toolchain integrated
in zephyr-sdk package.
stdinc dependency in hal_espressif will be worked out and removed
soon.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Assembler files were not migrated with the new <zephyr/...> prefix.
Note that the conversion has been scripted, refer to #45388 for more
details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Linker files were not migrated with the new <zephyr/...> prefix. Note
that the conversion has been scripted, refer to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In order to bring consistency in-tree, migrate all soc code to the
new prefix <zephyr/...>. Note that the conversion has been scripted,
refer to zephyrproject-rtos#45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
<zephyr/zephyr/types.h> is no longer available, <zephyr/types.h> should
be used instead.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add OpenISA RV32M1 pinctrl header file to define SoC specific pinctrl_soc_t
structure. This is used to store pin configurations for the pinctrl driver.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This modification is required to enable flash encryption.
Using hal implementation of spi_flash calls maintains
compability amongs different socs while offering
latest esp-idf enhancements.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Changes signature so it takes uint32_t instead of pointer to a
register.
Later `sys_read*` and `sys_write*` functions are used, which cast
given address to volatile pointer anyway.
This required changing types of some fields in LiteX GPIO driver and
removal of two casts in clock control driver.
There was a weird assert from LiteX GPIO driver, which checked whether
size of first register in dts was a multiple of 4.
It didn't make much sense, so I removed it.
Previous dts was describing size of a register in terms of subregisters
used. New one uses size of register, so right now it is almost always
4 bytes.
Most drivers don't read register size from dts anyway, so only changes
had to be made in GPIO and clock control drivers.
Both use `litex_read` and `litex_write` to operate on `n`bytes.
Now GPIO driver calculates this `n` value in compile time from given
number of pins and stores it in `reg_size` field of config struct like
before.
Registe sizes in clock control driver are hardcoded, because they are
tied to LiteX wrapper anyway.
This makes it possible to have code, independent of CSR data width.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Adds LITEX_CSR_DATA_WIDTH option to Kconfig
Depending on its value appropriate read/write handling is used
for accessing CSR registers.
By using `>=` in preprocessor conditions it is somewhat future-proofed.
Doesn't touch `litex_read` and `litex_write` yet.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Add the appropriate hooks effectively replacing the old implementation
with the new one.
Also the stackguard wasn't properly enforced especially with the
usermode combination. This is now fixed.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This PR removes common-rom.ld section so that logging sections
can now be mapped into RAM area.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
CONFIG_RISCV_ATOMICS_ISA enables A extension.
CONFIG_RISCV_MUL_ISA enables M extension.
CONFIG_FLOAT_HARD enables F extension. (FPU)
Since we changed to use configuration options to enable extensions,
we no longer need to specify extensions using zephyr_compile_options.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
1.Declare the member type to match the kscan_it8xxx2_regs, so
we needn't to transform the local structure in the function.
2.Stop using DRV_CONFIG, DRV_DATA, DRV_REG macros.
3.Delete unused register defines.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
This reverts commit b1ad97bc26 since it
causes the following build failure:
cc1: error: requested ABI requires '-march' to subsume the 'F'
extension
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Rather than specify input clock for each peripheral individually, instead
specify the relevant clocks in DTS.
This will enable easier support for non-default coreclk on fe310 in a
follow-up CL.
Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
IT8xxx2 supports the standard 'F' extension for single-precision
floating point: select the relevant Kconfig option for the SoC so
users can build floating-point code.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: Ie6da1d38d5654061553cb1ce13b0a0a96aa71ce0
The autoconf.h header is not required because the definitions present in
the file are exposed using the compiler `-imacros` flag.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Don't leave idle state if soc isn't waked-up by an interrupt.
(We change to check interrupt controller register)
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
When run the test_mutex_lock_timeout(), we need more time (>300us)
for the testing thread to finish the job, or we will get a fail
(we didn't run the test before).
Because our event timer doesn't handle the float part, and 32768 is
divisible by 8192 which is closest to kernel tick default 10000, I add
CONFIG_SYS_CLOCK_TICKS_PER_SEC = 8192 for all board of it8xxx2 series.
If the CONFIG_SYS_CLOCK_TICKS_PER_SEC = 32768,
the 10 tick of timeout = 300us.
If the CONFIG_SYS_CLOCK_TICKS_PER_SEC = 8192,
the 10 tick of timeout = 1200us.
So we can get more time to finish the job.
Verified by follow test pattern:
west build -p auto -b it8xxx2_evb tests/kernel/sleep
west build -p auto -b it8xxx2_evb tests/subsys/portability/cmsis_rtos_v2
fixes#43513fixes#42847
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Customize busy wait timer for micro-seconds accuracy.
Verified by follow test pattern:
west build -p auto -b it8xxx2_evb tests/kernel/timer/timer_api
west build -p auto -b it8xxx2_evb tests/kernel/timer/timer_error_case
west build -p auto -b it8xxx2_evb tests/kernel/timer/timer_monotonic
west build -p auto -b it8xxx2_evb tests/kernel/timer/starve
west build -p auto -b it8xxx2_evb tests/kernel/context
west build -p auto -b it8xxx2_evb tests/drivers/adc/adc_api
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
This commit fixes the default value of SYS_CLOCK_HW_CYCLES_PER_SEC
option. The previous value of 32768 is not consistent with the
documentation of FE310 SoC. Only FE310-based boards rely on the default
value of this option; other boards from the Freedom series define it
themselves.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit makes the transition from the pinmux driver to the pinctrl
driver. It also modifies UART, SPI and I2C drivers used in FE310-based
boards to use the new pinctrl API.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
As mentioned in #42882, the I2C of IT8XXX2 is designed for two different
IP blocks, so this PR divides this I2C driver into two compatibles.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Using IRQ as source for interrupt values can
fail when installing irq_connect_dynamic, as
IRQ can previously be enabled. This updates
the logic to use source map and allows
default irq_enable() and irq_disable() to call
esp32c3 interrupt allocator implementation.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Enable support for mtvec vectored mode for privilege SOCs. This
is an optional feature and takes up addtional code space. It is
necessary to support this feature for privilege SOCs that only
support mtvec vectored mode.
Change was tested on qemu_riscv32 and qemu_riscv64 boards with
CONFIG_RISCV_MTVEC_VECTORED_MODE enabled.
Signed-off-by: William Patty <wpatty24@gmail.com>
According to Kconfig guidelines, boolean prompts must not start with
"Enable...". The following command has been used to automate the changes
in this patch:
sed -i "s/bool \"[Ee]nables\? \(\w\)/bool \"\U\1/g" **/Kconfig*
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The ADC driver of IT81302 chip can support channels 0-7 & 13-16.
This PR adds to implement ADC channels 13-16.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Use CLINT to send interrupts to another CPU. SMP support is kinda
incomplete without it.
This patch only enables it for riscv-privilege platforms - specifically,
"virt" one.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Secondary CPUs are now initialised and made available to the system. If
the system has more CPUs than configured via CONFIG_MP_NUM_CPUS, those
are still left looping as before.
Some implementations of `soc_interrupt_init` also changed to use
`arch_irq_lock` instead of `irq_lock`.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Aligning with the rest of PM API, replace pm_power_state_exit_post_ops
with pm_state_exit_post_ops.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This register is a pre-define hardware slave A and can be accessed
through I2C0. It is not currently used, so it can be disabled to
avoid illegal access.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Introduce a new "zephyr,memory-region" compatible to be used when a new
memory region must be created in the linker script from the devicetree
nodes using the compatible.
Remove also the LINKER_DT_REGION_FROM_NODE macro and add a new
LINKER_DT_REGIONS macro to cycle through all the compatible regions.
In the same PR modify the DTS files and the linker scripts.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This enables the below configuration so the AP and EC are able to
communicate over eSPI:
CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION
CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
This patch adds GPIO and 96board LS (Low Speed)iexpansion connector
support for SiFive HiFive Unleashed and also enables GPIO basic test.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
replacing usage of the ESPTOOLPY_FLASHSIZE config
by the equivalent dt property path
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Non-standard `jalr rd, rs` pseudo-instructions are used.
This commit changes them to `ret` for standard return pseudo-instruction
or `jalr rd, rs, 0` for no offset jump register and link.
Fixes#41100.
Signed-off-by: Henry Hsieh <r901042004@yahoo.com.tw>
This configures soc and flash size definition
using DTSI information instead of hardcoded
values.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This modifies esp32c3 SOC configuration to support MCUBoot.
CmakeLists is moved from board to soc specific. It also
includes MCUBoot changes.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This change creates XiP image handling and proper
LMA and VMA regions configurations.
This also adds common-ram.ld and common-rom.ld sections that
require explicit handling due to image sections limitation
in esptool.
Move additional drivers into IRAM to protect against
flash cache disable read/write operation.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
BBRAM content should be cleared when boot from cutoff. Compare magic
number to decide whether to clear entire BBRAM.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
For functions returning nothing, there is no need to document
with @return, as Doxgen complains about "documented empty
return type of ...".
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Many ARM SoCs included <devicetree.h> likely due to:
1. nvic.h not being self-contained
2. As a result of copy-paste
Some RISC-V SoCs had the same problem, in this case likely due to
copy-paste from ARM. The <devicetree.h> header has been removed using
the following command:
sed -i ':a;N;$!ba;s/#include <devicetree\.h>\n//g' soc/**/soc.h
soc.h files that make a legitimate usage of the API have not been
changed.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The header was not self-contained: it uses DT and utility macros but
<devicetree.h> and <sys/util_macro.h> were not included.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The default I2C channel 3 is used by alternate function of GPIO H1/H2
Krabby uses GPIO F2/F3 as I2C channel 3, so we need to add the
compatibility of the GPIO F2/F3.
TEST=test on it8xxx2_evb:
zmake configure -b zephyr/projects/it8xxx2_evb/
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Enable CONFIG_RISCV_PMP in qemu virt soc. Use this SoC as CI testing
platform of RISC-V PMP and Userspace.
Signed-off-by: Jim Shu <cwshu@andestech.com>
If there are no console messages input at an interval of 15
seconds, the system will be able to enter suspend mode.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Change the settings to support pinctrl on the GD32VF103.
- Split soc/arm/gigadevice/common/pinctrl_soc.h
and put it into include/dt-bindings.
- Leave some definitions that can't handle with device tree compiler
in pinctrl_soc.h.
- Remove dependency to SOC_FAMILY_GD32 because always enabled it
if GD32_HAS_AF(IO)_PINMAX was selected.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
GD32V processor core is used non-standard bitmask
for mcause register. Add option to configure the bitmask
to support GD32V.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
As memory region names are now derived purely from devicetree, remove
the `name` parameter from `DT_REGION_FROM_NODE_STATUS_OKAY`. Name is
`zephyr,linker-region` if it exists, otherwise the node path.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
IT8XXX2 uses shared ns16550.c driver which does not provide a power
management callback(pm_action_cb), so create driver to handle
IT8XXX2 specific UART features.
note: pm_action_cb(old name: pm_control_fn)
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Use i2c_hal functions to enable support for
multiple SoCs.
Use DT compat to enable I2C from device
tree configuration
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This joins all clock control handling to same source
by using hal clock functions. It also brings ESP32C3
clock support.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add the power state of deep doze. When system enters deep doze, the
clock of CPU and EC can be stopped to reduce power consumption. And
enable the UART Rx WUI before entering deep doze to wake up EC and
CPU.
Tested on it8xxx2_evb board. It will reduce 5.25mA when system enters
deep doze mode.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Use the shared CONFIG_SERIAL_INIT_PRIORITY for driver initialization
priority.
Override the default value for the NEORV32 SoC to ensure the serial
driver is initialized after the syscon driver by default.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Implement the CPU idle task. The system should enter this task when
there is no any task to ensure power saving.
Tested on it8xxx2_evb board. It will reduce 12.5mA when system enters
the CPU idle task.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
GPIO L/K groups:
On IT81202 (128-pins package), the pins of GPIO group K and L aren't
bonding with pad. So we configure these pins as internal pull-down
at default to prevent leakage current due to floating.
GPIOH7:
On IT81202/IT81302, the GPIOH7 isn't bonding with pad and is left
floating internally. We need to enable internal pull-down for the pin
to prevent leakage current, but IT81202/IT81302 doesn't have the
capability to pull it down. We can only set it as output low,
so we enable output low for it at initialization to prevent leakage.
After setting: power saving=2.26mA
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Code removed:
- IT8XXX2 doesn't support soc level software interrupt hence remove
them.
- To use common macro to access csr (control status register).
- To remove CONFIG_RISCV_HAS_PLIC related code. IT8XXX2 uses its own
interrupt controller code.
- To remove ite_write and ite_read. We don't use them anymore.
Code changed:
- Return true from arch_irq_is_enabled() when external interrupt-enable
bit, and SOC's IER are both true.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Fixes: #38591, #38207, #37861
The commit 65a2de84a9 aligned the data
linker symbol for sections and regions.
The data region symbol start has been placed outside the sections thus
being defined as the address of the region before alignment of the first
section in the data region, usually the `datas` section.
The symbol defining the start address of the data section is after
section alignment.
In most cases the address of the data region start and datas section
start will be identical, but not always.
The data region symbol is a new linker symbol and existing code has
been depending on the old data section start symbol.
Thus, the update to the use of the data region start symbol instead of
data ram start symbol thus results in a different address when the
section is aligned to a different address.
To ensure the original behavior in all cases, the data region start
address is now moved inside the data section.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Call __reset instead of directly calling __initialize from the common
RISC-V privileged SoC vectors __start. This allows injection of SoC
specific reset code just after setting up the machine trap vector.
RISC-V privilege SoCs without the need for custom reset code can set
CONFIG_INCLUDE_RESET_VECTOR=y to include a __reset stub which simply
calls __initialize.
Fixes: #38396
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Setting this bit will wake up CPU if it is in low power mode
and an interrupt is pending.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This patch adds support for SiFive Freedom U740 SoC.
First version is minimum only using UART, SPI and L2-LIM area.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
This patch adds support for SiFive Freedom U540 SoC.
First version is minimum only using UART, SPI and DDR memory area.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
The free run timer will be used to count before entering hibernate
mode. Move the related registers to the head file for accessing.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
PR #37938 aligns many linker symbols name like rom/rodata_regions ...,
but ae350 soc linker script doesn't update for that. Migrate all linker
symbols name to PR #37938 changes.
Signed-off-by: Jim Shu <cwshu@andestech.com>
This initial support of L2C driver only contains cache enable and HW
capability checking. Cache management operation isn't supported yet
in this driver.
Signed-off-by: Jim Shu <cwshu@andestech.com>
Andes V5 PMA can let SW programmably configure memory attribute of
physical memory region. This commit enable CONFIG_NOCACHE_MEMORY of
Andes V5 CPUs based on the PMA. Use PMA region 0 to set whole nocache
section as uncached memory.
Signed-off-by: Jim Shu <cwshu@andestech.com>
Support custom RISC-V CSR context switch for Andes V5 CPUs.
Both AndeStar V5 DSP and PowerBrake features have it's own CSR to be
saved for thread and ISR context, so adding these CSRs into the RISC-V
SOC context management framework (CONFIG_RISCV_SOC_CONTEXT_SAVE).
Signed-off-by: Jim Shu <cwshu@andestech.com>
Add andes_v5 SoC series and andes_ae350 SoC. It includes
soc initialization code, linker script, and custom CSR encoding.
Signed-off-by: Jim Shu <cwshu@andestech.com>
Cleanup and preparation commit for linker script generator.
Zephyr linker scripts provides start and end symbols for each larger
areas in the linker script.
The symbols _image_text_start and _image_text_end sometimes includes
linker/kobject-text.ld. This mean there must be both the regular
__text_start and __text_end symbols for the pure text section, as well
as <group>_start and <group>_end symbols.
The symbols describing the text region which covers more than just the
text section itself will thus be changed to:
_image_text_start -> __text_region_start
_image_text_end -> __text_region_end
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Cleanup and preparation commit for linker script generator.
Zephyr linker scripts provides start and end symbols for each larger
areas in the linker script.
The symbols _image_rom_start and _image_rom_end corresponds to the group
ROMABLE_REGION defined in the ld linker scripts.
The symbols _image_rodata_start and _image_rodata_end is not placed as
independent group but covers common-rom.ld, thread-local-storage.ld,
kobject-rom.ld and snippets-rodata.ld.
This commit align those names and prepares for generation of groups in
linker scripts.
The symbols describing the ROMABLE_REGION will be renamed to:
_image_rom_start -> __rom_region_start
_image_rom_end -> __rom_region_end
The rodata will also use the group symbol notation as:
_image_rodata_start -> __rodata_region_start
_image_rodata_end -> __rodata_region_end
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Cleanup and preparation commit for linker script generator.
Zephyr linker scripts provides start and end symbols for each section,
and sometimes even size and LMA start symbols.
Generally, start and end symbols uses the following pattern, as:
Section name: foo
Section start symbol: __foo_start
Section end symbol: __foo_end
However, this pattern is not followed consistently.
To allow for linker script generation and ensure consistent naming of
symbols then the following pattern is introduced consistently to allow
for cleaner linker script generation.
Section name: foo
Section start symbol: __foo_start
Section end symbol: __foo_end
Section size symbol: __foo_size
Section LMA start symbol: __foo_load_start
This commit aligns the symbols for _data_ram/rom to other symbols and in
such a way they follow consistent pattern which allows for linker script
and scatter file generation.
The symbols are named according to the section name they describe.
Section name is `data`
A new group named data_region is introduced which instead spans all the
input and output sections that was previously covered by
__data_ram_start, __data_ram_end, and __data_rom_start.
The following symbols are aligned in this commit:
- __data_ram_start -> __data_region_start
- __data_ram_end -> __data_region_end
- __data_rom_start -> __data_region_load_start
The following new symbols are introduced so that the data section is
aligned with other sections:
- __data_end
- __data_start
value identical to __data_region_start but describes start of
the section.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Define soc_interrupt_init as a weak symbol in the common RISC-V
privileged instruction set SoC support.
This allows overriding soc_interrupt_init for SoCs which are not fully
compliant with the RISC-V privileged specification.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Define __soc_handle_irq as a weak symbol in the common RISC-V privileged
instruction set SoC support.
This allows overriding __soc_handle_irq for SoCs which are not fully
compliant with the RISC-V privileged specification.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
esp32c3 has already supported RISC-V GP, just apply new kconfig option
to it. Forcely select CONFIG_RISCV_GP in esp32c3 at first because it
seems to be necessary in the esp32c3 SoC.
Signed-off-by: Jim Shu <cwshu@andestech.com>
Add norelax option before initializing GP at common entry point.
Remove __global_pointer$ symbol in the SoC linker script because it's
in the arch one. Remove -mno-relax when GP support is enabled.
Signed-off-by: Jim Shu <cwshu@andestech.com>
Initialize GP at common entry point of riscv-privilege SoCs so that
this commit add GP support of these SoCs at once.
As some privilege SoCs want to customize the entry point, they should
disable linker relaxation by `.norelax option` before entrying the
common entry point `__start`.
Signed-off-by: Jim Shu <cwshu@andestech.com>
Creating static libraries for drivers moves some symbols out of IRAM.
This change fixes it.
Signed-off-by: Shubham Kulkarni <shubham.kulkarni@espressif.com>
The delay will ensure last byte has been latched in before
This also change the method of reading status register from re-send
read status command on each read to read status register continuously.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
log and libc optimization default config are soc related
and should be moved out from board context.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This reverts commit 7b09d031fa. Because
context save of GP register is removed, we don't need to initialize GP
at thread init. GP will be a constant value so that it could only be
initialized at program start.
Signed-off-by: Jim Shu <cwshu@andestech.com>
Current location options for linker source files includes init and
noinit ram data, but only a noinit ram section. This makes it impossible
for application code to define an initialized RAM output section,
such as with the Z_ITERABLE_SECTION_RAM() helpers.
Adding a DATA_SECTIONS linker source option for this use case.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
esp32c3 SoC is an rv32imc, so it does not support the atomic builtin.
Since it relies in atomic instructions.
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
based on uart rom functions, also enable console driver
on top if this driver enabling logging
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
Create a shared macro to access the pinctrl_0 property. The pinctrl_0
property includes pinmux phandle, pin and alternate function.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
it8xxx2 supports 'm', 'a', and 'c' extensions.
Enable them to save flash space and also improve
latency of fetching code from flash.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Correct SYS_CLOCK_HW_CYCLES_PER_SEC and
SYS_CLOCK_TICKS_PER_SEC to match our real setting value
for precise timing.
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Save ra to caller saved register is wrong because it might get
overwritten after another function is called, so we fix this.
Remove clear mip register operation. (it8xxx2 supports machine-mode
only, and MEIP bit of mip is read-only).
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
For esp32c3 related ROM located functions instead
of esp32c3_rom.
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
The _PrepC() function is the standard risc-v way
of zephyr entry point, so let it call the z_cstart instead
of calling this function directly.
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
replaces the plain memcpy to zero the bss with
the standard zephyr function that does this task.
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
Plus added implementation for esp32c3 SoC.
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
by adding the soc specific files such: soc initialization code,
linker scripts and support for esp32c3 devkitm
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
rv32m1_vega don't boot due to device init ordering and changes with the
device model. The soc code is looking for a device pointer for the
intmux. Change to using DEVICE_DT_GET here as that will ensure we get
a valid pointer and by the time we need to utilize the pointer the
intmux driver will have been initialized and thus the device pointer
will be ready.
Also set BUILD_OUTPUT_HEX since we utilize openocd to flash and west
flash is looking for a hex file for openocd targets.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add flash driver for it8xxx2. The driver can implement
flash read, write and erase that will be mapped to the
ram section for executing.
TEST="flash write 0x80000 0x10 0x20 0x30 0x40 ..."
"flash read 0x80000 0x100"
"flash erase 0x80000 0x1000"
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Adding support for beagleV Starlight board based on Starfive JH7100
SoC. It's a base support, no drivers other than uart has been tested.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
Create the pinmux phandle to the ADC driver node in the
devicetree. When the pinmux_pin_set function in
adc_it8xxx2_channel_setup can refer to the setting of
this phandle. It is more flexible to use.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit fixes the ADC driver flow. And add internal
reference voltage to ADC driver API. And correct the
data buffer that only need to store raw data.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
We need to clear interrupt status, before we enable the interrupt.
So I let ite_intc_isr_clear() to be global function.
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Add register address including external timer and watchdog(ETWD),
general control(GCTRL), serial peripheral interface(SPI).
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This change enables A, C, D, E, G, H, I, J, K, and L groups,
and fix gpio interrupt function.
This change also pull (and rename) dt-bindings/irq.h to
dt-bindings/interrupt-controller/ite-intc.h, because it is
chip-specific.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: Ifee039981c2cc4cf5980e663702a9921e629fc1e
This commit is about the it8xxx2 analog to digital converter
driver. Support 8 channels ch0~ch7 and 10-bit resolution.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This patch adds weak sys_arch_reboot() function to avoid build error
with CONFIG_REBOOT=y. Some SoC has already had own reboot function
but others (Ex. qemu boards) faced buld error.
- openisa_rv32m1: Not change
- riscv-ite: Do nothing, remove and use arch/riscv function
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Add a simple pinctrl node for the IOF registers under the GPIO
controller node to be used by the pinmux driver.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The default frequency for this board in Renode is 66 MHz. This needs to
be even with `SYS_CLOCK_HW_CYCLES_PER_SEC` to avoid such problems as in
the #31726 issue.
Unfortunately, the difference in these values was helpful for some tests
that are failing with 66 MHz set in both places. It created artificial
boost in certain circumstances.
The frequencies in the default Renode platform description (`.repl`)
file for MI-V were overridden with 4 MHz value that seems to be better
tolerated based on testing. The `SYS_CLOCK_HW_CYCLES_PER_SEC` was
adjusted as well.
To solve the rest of the issues, `cpu PerformanceInMips` was set to 4.
It seems tests are completed faster with such a value.
This commit fixes#31726.
Signed-off-by: Adam Jeliński <ajelinski@antmicro.com>
The QEMU RISC-V VirtIO board is capable:
- 8 x CPU
- 256 MiB RAM
- PMP
- PCI
- ISA string: RVnnIMAFDCSU
- mul/div
- FPU with double precision
- MMU
- Compressed instructions
Devicetree was extracted from QEMU as described in virt.dtsi.
The same .dtsi SOC description is used for 32-bit and 64-bit.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
This commit is about the it8xxx2 i2c master driver which
includes six SMBus channels. The enhanced channel i2c3,
i2c4, i2c5 are controller which are designed to support
the I2C protocol.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The IRQ handler has had a major changes to manage syscall, reschedule
and interrupt from user thread and stack guard.
Add userspace support:
- Use a global variable to know if the current execution is user or
machine. The location of this variable is read only for all user
thread and read/write for kernel thread.
- Memory shared is supported.
- Use dynamic allocation to optimize PMP slot usage. If the area size
is a power of 2, only one PMP slot is used, else 2 are used.
Add stack guard support:
- Use MPRV bit to force PMP rules to machine mode execution.
- IRQ stack have a locked stack guard to avoid re-write PMP
configuration registers for each interruption and then win some
cycle.
- The IRQ stack is used as "temporary" stack at the beginning of IRQ
handler to save current ESF. That avoid to trigger write fault on
thread stack during store ESF which that call IRQ handler to
infinity.
- A stack guard is also setup for privileged stack of a user thread.
Thread:
- A PMP setup is specific to each thread. PMP setup are saved in each
thread structure to improve reschedule performance.
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: Nicolas Royer <nroyer@baylibre.com>
Adds the necessary bits to initialize TLS in the stack
area and sets up CPU registers during context switch.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Do not assume `reg_size` to be a multiple of 4 and
divide it on each call, expect the caller to provide
an already divided value instead.
This change require the LiteX GPIO driver to be modified,
which will come in the following commit.
Signed-off-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.
A coccinelle rule is used for this:
@r_const_dev_1
disable optional_qualifier
@
@@
-struct device *
+const struct device *
@r_const_dev_2
disable optional_qualifier
@
@@
-struct device * const
+const struct device *
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
unify how XIP is configured across architectures. Use imply instead of
setting defaults per architecture and imply XIP on riscv arch and remove
XIP configuration from individual defconfig files to match other
architectures.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The optional SOC_CONTEXT carries processor state registers that need to
be initialized properly to avoid uninitialized memory read as processor
state.
In particular on the RV32M1 the extra soc context stores a state for
special loop instructions, and loading non zero values will have the
core assume it is in a loop.
Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
Saving an extended context for RV32M1 should be optional, but it was
broken due to the offset calculation not taking the according option
into account.
Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
The `TEXT_SECTION_OFFSET` symbol is used to specify the offset between
the beginning of the ROM area and the address of the first ROM section.
This commit renames `TEXT_SECTION_OFFSET` to `ROM_START_OFFSET` because
the first ROM section is not always the `.text` section.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Remove Kconfig, linker script, and related bits associated with
CUSTOM_RODATA_LD, CUSTOM_RWDATA_LD, CUSTOM_SECTIONS_LD,
SOC_NOINIT_LD, SOC_RODATA_LD, and SOC_RWDATA_LD options that have been
deprecated since Zephyr 2.2.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This adds a helper function for reading LiteX 64-bit CSRs
to be used by LiteX drivers.
Signed-off-by: Jakub Cebulski <jcebulski@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Several reviewers agreed that DT_HAS_NODE_STATUS_OKAY(...) was an
undesirable API for the following reasons:
- it's inconsistent with the rest of the DT_NODE_HAS_FOO names
- DT_NODE_HAS_FOO_BAR_BAZ(node) was agreed upon as a shorthand
for macros which are equivalent to
DT_NODE_HAS_FOO(node) && DT_NODE_HAS_BAR(node) &&
- DT_NODE_HAS_BAZ(node), and DT_HAS_NODE_STATUS_OKAY is an odd duck
- DT_NODE_HAS_STATUS(..., okay) was viewed as more readable anyway
- it is seen as a somewhat aesthetically challenged name
Replace all users with DT_NODE_HAS_STATUS(..., okay), which is
semantically equivalent.
This is mostly done with sed, but a few remaining cases were done by
hand, along with whitespace, docs, and comment changes. These special
cases include the Nordic SOC static assert files.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
