Commit graph

2589 commits

Author SHA1 Message Date
Flavio Ceolin
78454e5e93 pm: Rename pm_power_state_exit_post_ops
Aligning with the rest of PM API, replace pm_power_state_exit_post_ops
with pm_state_exit_post_ops.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-02-23 07:33:46 -05:00
Flavio Ceolin
89fee61b43 pm: Rename pm_power_state_set
Aligning with the rest of PM API, replace pm_power_state_set with
pm_state_set.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-02-23 07:33:46 -05:00
Martí Bolívar
dcb0d9fc4a soc: nrf: remove use of NRF_GPIO_PIN_MAP
Commit 7cdd10bf89
("soc: arm: nordic: add NRF_DT_GPIOS_TO_PSEL_BY_IDX") added a use of
NRF_GPIO_PIN_MAP to soc_nrf_common.h without including the relevant
HAL header where it is defined, hal/nrf_gpio.h.

Unfortunately, including that header causes even more problems, since
it causes undefined NRFX_ASSERT() calls to appear elsewhere in the
tree.

It's not really worth bothering to use this macro. Just expand it
inline instead.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2022-02-22 20:55:53 -05:00
Jedrzej Ciupis
81c48c3e68 soc: arm: nordic: extend nRF5340 initialization
Extend initialization code for nRF5340 application core to iterate over
child nodes of GPIO pin forwarder node and pass control over detected
pins to the network core.

Signed-off-by: Jedrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
2022-02-22 15:00:35 -08:00
Jedrzej Ciupis
7cdd10bf89 soc: arm: nordic: add NRF_DT_GPIOS_TO_PSEL_BY_IDX
Add a macro that allows to retrieve pin's PSEL from its devicetree
representation taking into account its index into GPIO array.

Signed-off-by: Jedrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
2022-02-22 15:00:35 -08:00
Chris Trowbridge
52bee41bba drivers: ipm: Add support for NXP i.MX rev2 MU
With a number of the i.MX SoCs (e.g., the i.MX8M Plus), NXP has moved to
supporting the integrated Cortex-M cores with the MCUXpresso SDK (MCUX).
As a result, certain Zephyr drivers (such as the IPM driver) need to be
updated to utlize this new MCUX-based SDK.

This change adds support for the MCUX Messaging Unit driver pulled in by
this PR:
https://github.com/zephyrproject-rtos/hal_nxp/pull/130

Additionally, this change enables the new IPM_IMX_REV2 config for the
mimx8ml8_m7 SoC target which utilizes this new revision of the driver.

Signed-off-by: Chris Trowbridge <chris.trowbridge@lairdconnect.com>
2022-02-22 16:34:06 -06:00
Chris Trowbridge
f401be157f drivers: gpio: Add GPIO support for mimx8ml8_m7 (NXP i.MX8M Plus SoC)
The current MCUX IGPIO driver assumes that the target SoC supports
the DR_SET, DR_CLEAR, and DR_TOGGLE functionality, but some do not
(namely, the M7 core of the i.MX8M Plus SoC). Current releases of
the MCUXpresso SDK IGPIO driver contain utility functions to set,
clear, and toggle pins which include provisions to support SoCs
with and without DR_SET, DR_CLEAR, and DR_TOGGLE, and this change
switches to using these utility functions.

Additionally, this change enables GPIO support on the mimx8ml8_m7
target.

Signed-off-by: Chris Trowbridge <chris.trowbridge@lairdconnect.com>
2022-02-22 10:13:31 -08:00
Tomislav Milkovic
a0bc0672b8 soc: arm: stm32h7: add support for stm32h7b3xx and stm32h7b3xxq
Add SoC Kconfig configurations

Signed-off-by: Tomislav Milkovic <tomislav.milkovic95@gmail.com>
2022-02-22 10:34:56 -05:00
Carles Cufi
e83a13aabf kconfig: Rename the TEST_EXTRA stack size option to align with the rest
All stack sizes should end with STACK_SIZE.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2022-02-22 08:23:05 -05:00
Jun Lin
756babfa75 soc: npcx: add support for npcx9m7f
Add new SoC npcx9m7f support for npcx9 series.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2022-02-21 21:56:24 -05:00
Jun Lin
a6ce9b55c1 soc: npcx: guard psl-in related code by the status of vsby-psl-in-list
Do not include psl-in related code is the status of vsby-psl-in-list is
disabled, which can help reduce a little RAM/flash size.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2022-02-21 21:55:54 -05:00
Carlo Caione
c5894df5ec pm: Change parameters of pm_power_state_{set,exit_post_ops}
Just pass state and substate_id instead of the whole info structure
pointer.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-02-21 20:58:01 -05:00
Carlo Caione
11f1dd2370 pm: Reference pm_state_info only by pointer
It's unnecessary to move the pm_state_info around by value, just use a
pointer.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-02-21 20:58:01 -05:00
Jose Alberto Meza
0549428b55 soc: arm: mchp: Remove magic numbers
Add SoC MEC150x device ID macros.

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2022-02-21 20:55:48 -05:00
Gerard Marull-Paretas
b2aca68622 soc: arm: microchip_mec: remove re-defined Kconfig help
The help for MCHP_ECIA_XEC is defined in
drivers/interrupt_controller/Kconfig.xec. defconfig files must not
re-define prompts or help, just modify the default value.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-02-21 19:35:21 -05:00
Gerard Marull-Paretas
f866e796fb soc: arm: nuvoton_npcx: remove Kconfig help re-definitions in defconfig
The SoC Kconfig.defconfig.series files re-defined multiple Kconfig help
entries. The help for such symbols should only be present in places
where symbol is actually defined, not where the defaults are changed.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-02-21 19:35:21 -05:00
Attie Grande
24478c8a4d drivers: adc: adc_sam0: Change local variables to lower case
Local variables should not be in capitals.

Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
2022-02-04 10:49:09 +01:00
Attie Grande
e4d4eaca03 soc: atmel_sam0: Implement fixup.h for ADC driver
The ADC driver now supports three different implementations. To maintain
readability, this patch implements an adc_fixup.h that permits more
generic access to relevant registers.

This patch also introduces support for a new third shape ADC - as found
in the SAML21 for example.

Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
2022-02-04 10:49:09 +01:00
Daniel DeGrasse
5dfd3c3786 soc: rt10xx: Set divisor for sys pll (PLL2) PFD0
Divisor must be set to calculate SD host controller clock frequency in
clock driver.

Fixes #42380

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-02-02 16:59:30 +01:00
Yonatan Schachter
efa170f480 soc: rp2040: Added UF2 output file support
Added support for the UF2 file format for the RP2040 SoC

Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
2022-02-02 16:23:35 +01:00
Yonatan Schachter
fd59038312 drivers: pinctrl: Added pinctrl driver for RPi Pico
Added a pinctrl driver for the Raspberry Pi Pico series

Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
2022-02-02 16:23:35 +01:00
Yonatan Schachter
db5b2780bf soc: Added support for Raspberry Pi's RP2040 SoC
Added basic support for the RP2040 SoC. Support
includes booting and starting the kernel, on one
core only.

Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2022-02-02 16:23:35 +01:00
Joakim Andersson
aef46a8e51 soc: nrf53: Add handling of secure-only code in init with TFM enabled
Add handling of secure-only code with TF-M enabled that can only be done
from secure processing environment.

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2022-02-01 11:31:36 +01:00
Hake Huang
496dd79fdb soc: rt1xxx: fix build errors
remove LOG_ERR in soc init

fixing: #42179

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-01-28 10:06:53 +01:00
Hake Huang
de3518157c soc: nxp_rt: sai clock header include
add sai clock source name define header
update the clock marco for sai

fixing: #42179

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-01-28 10:06:53 +01:00
Alexander Mihajlovic
dafc4383fd soc: stm32l0: Clear LPSDSR when exiting STOP mode
Clear the LPSDSR bit of PWR_CR to restore the voltage regulator
mode when exiting from STOP mode. Leaving LPSDSR set can cause
cause stability issues because the MCU will enter low-power sleep mode
instead of normal sleep mode when the core idles and this is not what
the rest of the implementation expects.

Signed-off-by: Alexander Mihajlovic <a@abxy.se>
2022-01-28 10:06:13 +01:00
Hake Huang
a59e994322 soc: add auido clock init per soc
RT11xx and RT10xx have different audio clock settings
so add them in soc.c

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-01-21 11:26:45 -06:00
Hake Huang
8ae222641d config: soc: add i2s support in rt1170 soc
add HAS_MCUX_I2S in soc config

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-01-21 11:26:45 -06:00
Immo Birnbaum
dffcb1d6f9 soc: arm: xilinx_zynq7000: Re-organize SoC data and init code
Re-organize the SoC family/series/model configuration data so that:
* Board definitions can distinguish between the single-core (XC7ZxxxS)
and dual-core (XC7Zxxx) ARM Cortex-A9 models. Further descriptions
of on-chip resources, in particular relating to the programmable logic
capabilities if support of this functionality is to be implemented,
can be added at a later time.
* Separate SoC initialization code exists for the two series, so that
the init code of the XC7Zxxx series can consider SMP while the init
code of the single-core XC7ZxxxS series doesn't have to.
* Device drivers which don't have to distinguish between the single-
and double-core series of the SoC family can use a common configuration
item whenever the pre-processor is used to enable Zynq-7000-specific
code.

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@Weidmueller.com>
2022-01-21 11:34:09 -05:00
Mahesh Mahadevan
6f23f55e4b soc: mxrt10xx: Update the clock init code
1. Setup VDD_SOC with the appropriate setting
   depending on the SoC
2. Do not configure PLL_SYS and PLL_USB. These
   are already configured by the ROM code using
   the DCD
3. Fix setting for USDHC clock

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-01-21 08:36:09 -06:00
Jay Vasanth
4495f43dca soc arm: MEC172x soc.h - Include custom IRQn_Type
Fix for issue #41012 to allow compiler to treat
IRQn_Type to be more than 8-bit. This will ensure NVIC numbers
more than 127 (required for MEC172x device) will work
correctly with irq_enable() API

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-01-20 13:42:16 -05:00
Mahesh Mahadevan
a62ff8906d soc: Add support for MXRT595
Add support for MXRT595

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-01-19 13:35:09 -06:00
Benedikt Schmidt
03297084e5 soc: arm: stm32: activate LPTIM based upon PM
Activate LPTIM by default if PM is selected.

Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
2022-01-19 14:15:29 -05:00
Krzysztof Chruscinski
ff6b5d979f soc: arm: nordic_nrf: nrf53: Add Synchronized RTC
Add a module which is responsible for getting offset between RTCs
used for system clock on NET and APP cores. After getting an offset
between NET and APP clocks, it can be used for logging timestamping
on NET core to ensure that timestamping is in sync on both cores.

Synchronization is done using PPI, IPM task and events and RTC
capture feature.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2022-01-19 17:46:28 +01:00
Krzysztof Chruscinski
1f445b65fb soc: arm: nordic_nrf: nrf53: Add nrf53 series guards to Kconfig.soc
All options in Kconfig.soc are only for nrf53 series. Added file
wide guard instead of option specific options.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2022-01-19 17:46:28 +01:00
Daniel DeGrasse
19bb8e2ec8 soc: rt11xx: Enable power management for RT11xx series SOCs
Enables basic power management for the RT11xx series SOCs. The following
power saving measures are currently implemented:

- system reduces core voltage during sleep
- core clock can be gated in deep sleep

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-01-18 14:09:45 -05:00
Daniel DeGrasse
f5ebc30087 soc: imx_rt: Enable IMX.RT General Power Controller Driver
GPC driver is used for power management operations on RT series SoCs.
Enable inclusion of the driver into the build.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-01-18 14:09:45 -05:00
Yasushi SHOJI
611230f80e soc/arm/designstart: Make XIP optional
Arm Cortex-M3 DesignStart FPGA-Xilinx edition doesn't have to use XIP.
Our board doesn't need it.  Make it optional by replacing "select" with
"imply".

Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
2022-01-18 13:21:50 -05:00
Francois Ramu
1b8d2d3dad soc: arm: stm32 mcus should execute stm32_power_init in PRE_KERNEL_1
Change the stm32_power_init to be executed PRE_KERNEL_1
for all the devices with the low power mode (power.c)
When GPIO and UART are not yet up and running.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-01-18 13:17:39 -05:00
Daniel DeGrasse
0fddb3e458 soc: rt11xx: Enabled GPTP module clock
gPTP module clock is enabled for rt11xx. gPTP is not working correctly
on the RT10xx or RT11xx series, but this module clock needs to be
enabled

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-01-18 12:13:24 -05:00
Daniel DeGrasse
b3a148b22f soc: rt11xx: Enable ethernet clocks
Enable clocks for ethernet module.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-01-18 12:13:24 -05:00
Gerson Fernando Budke
58936e7639 soc: arm: atmel_sam: samv71: Fix SPI build dependency
The SAM spi driver depends on GPIO driver to work. It seems that this
dependency chain it is not handled. This select GPIO driver when SPI
driver is enabled. It rework GPIO and SPI Kconfig to select driver by
devicetree and drop entries at Kconfig.defconfig.series file.

Fixes #41525

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2022-01-18 12:12:52 -05:00
Julien Massot
feb6e2504e drivers: pinctrl: add Renesas RCar PFC driver
Introduce Pin Function Controller for Renesas R-Car family.
This first implementation support to set a given pin as gpio
or peripheral (GPSR), to set a peripheral function to a
pin (IPSR), to set pull-up, pull-down (PUEN, PUD).
In addition this driver allows to set driving capabilies(DRVCTRL).

Pins are identified thanks to the per SoC binding for
pin definition which also contains pin alternate function
parameters.

Some pins can also have driving capabilities, some have bias
capabilities.
In order to find the correct bias and drive registers pfc_r8a77951.c
describes the different registers.
Each SoCs or package will need to define getters
for these registers: pfc_rcar_get_bias_regs() and
pfc_rcar_get_drive_regs().

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2022-01-17 21:00:58 +01:00
Manojkumar Subramaniam
bd9415e6bf soc: arm: stm32h7: kconfig workaround to handle SoC H7A3XX-Q P/N
Set the correct soc string so that the correct CMSIS file
is being utilised.

Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
2022-01-17 11:45:21 -05:00
Manojkumar Subramaniam
881407be6e soc: arm: stm32h7: add stm32h7a3xxq
The Q variant is the same as non-Q, except the Q has SMPS built-in.
This symbol addition is to have the correct
SOC definition ("STM32H7A3XXQ")

Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
2022-01-17 11:45:21 -05:00
Manojkumar Subramaniam
a268d8b07e soc: arm: stm32h7: add stm32h7a3xx support
Basic kconfig config.

Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
2022-01-17 11:45:21 -05:00
Daniel Leung
aa20e081d2 arm: remove @return doc for void functions
For functions returning nothing, there is no need to document
with @return, as Doxgen complains about "documented empty
return type of ...".

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-01-12 16:02:16 -05:00
Christoffer Bask
2091c3752d pwm: Added MCUX_PWM support for MIMXRT1021
It has been tested and working on a custom MIMXRT1021-pcb.

Signed-off-by: Christoffer Bask <christoffer@softube.com>
2022-01-12 15:46:01 +01:00
Gerard Marull-Paretas
864888f2ce soc: arm: nuvoton_npcx: add missing include
The reg_def.h was not self-contained: it uses DT API but doesn't
include <devicetree.h>.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 10:03:54 -05:00
Gerard Marull-Paretas
e5e73a70e9 soc: remove unnecessary inclusions of devicetree.h
Many ARM SoCs included <devicetree.h> likely due to:

1. nvic.h not being self-contained
2. As a result of copy-paste

Some RISC-V SoCs had the same problem, in this case likely due to
copy-paste from ARM. The <devicetree.h> header has been removed using
the following command:

sed -i ':a;N;$!ba;s/#include <devicetree\.h>\n//g' soc/**/soc.h

soc.h files that make a legitimate usage of the API have not been
changed.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00