Split the common keyboard scanning code out of the ITE specific driver
and use the generic code instead.
Note that this changes few timing defaults, the change is not
significant though so I suspect there's no difference in practice.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
- added example of usage Infineon CAT1 i2c driver
- added note that pinctrl nodes need to be configured
as open-drain and input-enable.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Setting slew-rate property is not supported on Kinetis KE series
and the value will not have effect, so this property should not
be required.
We are also planning to reuse the Kinetis pin control binding and
associated driver for NXP S32K1xx devices, which doesn't support
setting the slew-rate rate as well.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Add Verdin iMX8M Plus board with i.MX8MP SoC and ARM Cortex-M7 processor.
Add two targets (DDR and ITCM) for the iMX8M Plus board.
Port and documentation are based on NXP MIMX8MM EVK board.
This code is intented to be used with the Cortex-M7.
Signed-off-by: Gabriel Freitas <gabriel.freitas@toradex.com>
Add support for UART1 usage by adding uart1 node and configuration
to the i.MX 8ML devicetree include.
Signed-off-by: Gabriel Freitas <gabriel.freitas@toradex.com>
Add Renesas rzt2m gpio driver with basic functionality.
It supports pin mode configuration and writing/reading to/from gpio ports.
Includes dts changes to build blinky sample.
Signed-off-by: Jakub Michalski <jmichalski@internships.antmicro.com>
This adds a new driver for Renesas RZ/T2M.
The driver allows configuration of pin direction,
pull up/down resistors, drive strength and slew rate,
and selection of function for a pin.
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
This adds a UART driver for the Renesas RZ/T2M
Serial Communication Interface.
The driver implements:
* Polling API,
* Interrupt-driven API.
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
This adds a new SoC: SOC_RENESAS_RZT2M
and a new board: rzt2m_startek_kit
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
Co-authored-by: Roman Dobrodii <rdobrodii@antmicro.com>
Change the row-count and col-count to be optional in the generic
binding, add a second pair of macro to allow the implementation to
specify the numbers from a different property.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
A configurable delay during regulator switch on is currently
only supported by the GPIO and fixed regulator drivers.
This functionality has been moved to the common driver, so it can
be easily added to any regulator driver.
Signed-off-by: Andy Sinclair <andy.sinclair@nordicsemi.no>
i.MX93 share similiar register layout with i.MX RT11xx. Change ccm driver
to align with i.MX RT11xx, and make it easier to enable other drivers.
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
The LPS22DF is an ultracompact, piezoresistive, absolute pressure sensor
that functions as a digital output barometer. The LPS22DF provides lower
power consumption, achieving lower pressure noise than its predecessor.
This driver is based on stmemsc HAL i/f v2.3
https://www.st.com/en/datasheet/lps22df.pdf
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The icmsg and icmsg_me backends has limitations in context of
concurrent access to single instance. Some limitations are:
* sending by more thread at the same time may cause -EBUSY
* allocating TX buffer will cause errors in other threads that want
to allocate before first thread sent the message,
* during no-copy receive, when RX buffer is on hold receiving is
totally blocked.
This backend resolves those limitations by adding dynamically allocated
buffers on shared memory next to ICmsg circular buffer. The data is
passed using those buffers, so concurrency is not a problem. The ICmsg
is used only to pass short 2-byte messages containing references to
those buffers. The backend also supports multiple endpoint.
The ipc/icmsg_me sample was modified to support this backend.
Signed-off-by: Dominik Kilian <Dominik.Kilian@nordicsemi.no>
Move all the generic code from the Nuvoton NPCX keyboard scanning driver
into input_kbd_matrix.c. While doing that convert few configs into
devicetree properties and tweak few other things to enable the generic
code to support multiple instances.
This is limited to 8 rows for now, and that's fine for all the current
in-tree drivers, the limit could be removed down the road but this
should be fine for now, added few generic build checks to make sure a
driver does not go over the limit, as well and some more implementation
specific checks.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Enable NXP FlexRAM in DTS and SOC code.
Do not configure flexram at runtime if the code is in the RAM.
Fix RT1060 DT to be more accurate.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The M4F subsystem has a dedicated GPIO controller with 24 available
pins. Add the node definition for the recently added driver.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Add pinctrl to the Davinci GPIO driver to allow muxing pins dirctly
in this driver.
Also aligned the macro backslashes as line continuation character at
the end of each line with each at the same position and removed the
GPIO_DAVINCI_DEVICE_INIT macro which seems to be not used.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
DW watchdog driver is not used on ACE,
Intel ADSP watchdog driver will be used in DTS when ready to use
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Convert the ITE keyboard scanning driver from kscan to input, add the
corresponding kscan compatibility node to the current board, build test
only.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Initialize the MDIO peripheral clock (normally done during GMAC
initialization) before trying any MDIO transfers, preventing startup
errors.
Signed-off-by: Nick Kraus <nick@nckraus.com>
Support NXP MRT on LPC55XXX SOC series, enable on
lpcxpresso55s69_cpu0, add test overlay to counter basic api test
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add binding for nxp,mrt and nxp,mrt-channel. MRT is
NXP multirate timer, a simple timer with multiple
independent channels.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit introduces all changes necessary for utilizing
the serial interface on i.MX8QM/QXP.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Since the LPUART peripheral DTS binding requires the
"interrupts" property be specified even if it's not going
to be used for now we need to add a dummy interrupt controller
node to make that possible. Logically speaking, this dummy
interrupt controller should be used by peripherals which
can assert interrupts directly routed to the DSP.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This commit enables clock control on the i.MX8QM and QXP boards.
This is achieved through the following changes:
1) The "reg" property is no longer marked as required
for the "nxp,imx-ccm" binding. This is necessary because
in the case of i.MX8QM and i.MX8QXP the clock management
is done through the SCFW, hence there's no need to access
CCM's MMIO space (not that you could anyways).
2) The DTS now contains a scu_mu node. This node refers
to the MU instance used by the DSP to communicate with
the SCFW.
3) The CCM driver needs to support the LPUART clocks
(which will be the only IP that's supported for now)
and needs to perform an initialization so that the
NXP HAL driver knows which MU to use to communicate
with the SCFW.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This patch set provides support for T1S ethernet device - LAN8651.
For SPI communication the implementation of Open Alliance TC6
specification is used.
The driver implementation focuses mostly on reducing memory footprint,
as the used SoC (STM32G491) for development has only 32 KiB RAM in total.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
NXP USB bindings were combined into one binding and using
a property corresponding to HAL enums which is improper use
of devicetree.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Generic GPIO enabled analog switch to isolate devices from an I2C bus
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
Signed-off-by: Ayush Singh <ayushdevel1325@gmail.com>
