This WDT is responsible for monitoring the external
32.728 Hz crystal connected to pins XTAL_32K_P and
XTAL_32K_N. If an oscillation failure is detected
the hardware automatically switch to RTC_RC_SLOW
clock source and triggers an interrupt.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Add a parameter to allow the configuration of the number of address
bytes used by the I2C master. This allows the driver to expose larger
buffer sizes.
Tested with standard linux at24 driver.
Signed-off-by: Bram Vlerick <bram.vlerick@openpixelsystems.org>
This commit should deal with optimizing device's
operation in terms of power consumption. In this
context:
1. Power and rail managers are enabled so that the
device can enter the sleep state and power
rails be set to the min. required levels.
2. Peripheral blocks should be enabled only when
there is need to do so.
3. Define the internal RCX oscillator as default
low power clock. RC32K should not be used as
it drifts significantly due to temperature and
voltage variations. Thus, affecting the whole
system stability regardless of its calibration.
4. PLL should be enabled only when requested and
on board level LP clock should be switched to
XTAL32K to avoid overhead due to RCX calibration.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Behavior of "force"-mode as described in datasheet cannot be achieved if
low-power mode is enabled. After triggering a sampling, the sensor will
not sample again for the period specified in measurement-time.
Signed-off-by: Juliane Schulze <juliane.schulze@deveritec.com>
Define CANPLL, an AUXPLL IP instance used by the CAN IP. PLL settings
are hardcoded in SoC files, as this PLL should not be configured by the
application. It is meant to always run at 80 MHz.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Define HFXO (High Frequency Crystal Oscillator). This clock is managed
by system controller, from an application point of view it is a fixed
clock.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Driver did not work on ESP32c3, by specifying pin to be output and
input solve the issue. Improve documentation, to highlight that driver
is requiring open-drain support.
Signed-off-by: Fredrik Gihl <fgihl@hotmail.com>
Rename nxp,kinetis-lptmr compat to nxp,lptmr.
Because of concerns over breaking downstream users,
keep support for the old compatible temporarily and
make it clear it should be changed.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Added ADI MAX series soc, first partnumber is MAX32690
The family structure will be
ADI_MAX
MAX32xxx
MAX32655
MAX32655EVKIT
MAX32655FTHR
MAX32666
MAX32666FTHR
MAX32666FTHR2
MAX32690
MAX32690EVKIT
MAX78xxx
MAX78000
MAX78002
...
When MAX32 MCUs goes to sleep mode debugger could not access it
and flashing fails, ARM_ON_ENTER_CPU_IDLE_HOOK prevent
the CPU from actually entering sleep
by skipping the WFE/WFI instruction.
Due to ARM_ON_ENTER_CPU_IDLE_HOOK is not configurable at the user
space, added a config wrapper as MAX32_ON_ENTER_CPU_IDLE_HOOK.
If MAX32_ON_ENTER_CPU_IDLE_HOOK config being defined (default y)
devicei will not goes to sleep mode in idle state.
To disable it add below line in your configuration file
CONFIG_MAX32_ON_ENTER_CPU_IDLE_HOOK=n
MAX32690 has two core Cortex-M4 and Risc-V this commit adds M4 core
support.
Co-authored-by: Jason Murphy <jason.murphy@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
This commit defines the bt-hci subnode under the bleif node on
Ambiq Apollo3 Blue and Apollo3 Blue Plus SOC.
Also add the default configurations for Bluetooth feature on Ambiq
apollo3_evb and apollo3p_evb.
Signed-off-by: Aaron Ye <aye@ambiq.com>
This commits add the BLEIF instance which is compatible with
"ambiq,spi-bleif" on Ambiq apollo3p_evb and apollo3_evb.
Also creates the default pinctrl for the defined instance.
Signed-off-by: Aaron Ye <aye@ambiq.com>
Some Ambiq Apollox Blue SOC (e.g. Apollo3 Blue) uses internal designed
BLEIF module which is different from the general IOM module for SPI
transceiver. The called HAL API will also be independent. This driver is
implemented for the BLEIF module usage scenarios.
Signed-off-by: Aaron Ye <aye@ambiq.com>
The RTC subsystem in espressif's SOCs, among other tasks
is responsible for clock selection for CPU and for low
power domain clocks such as RTC_SLOW and RTC_FAST.
This commit allows for proper clock source and rate
selection for CPU, using the espressif,riscv and
espressif,xtensa-lx6/7 bindings.
It also enables clock selection for RTC_FAST and RTC_SLOW,
that impacts some peripherals, such as rtc_timer.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
- Add initial version of CYW920829M2EVK-02 board
- [drivers: clock_control] Make it possible to set up both iho and imo
clocks instead of just one or the other
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Secondary cores are not allowed to be power gated on
runtime-idle. They have to explicitely set off by host command.
Remove this state from secondary CPUs so power management logic
does not need workarounds to enforce this behavior.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The MBOX driver interface expects a device tree property '#mbox-cells'
which is not known by the IPM driver. This causes build problems when
both drivers are given for a single shared DT node.
To fix this problem for this driver specifically, add a dummy
'#mbox-cells' property to the bindings of the STM32 HSEM IPM driver.
This does not affect any other IPM driver, and the STM32 HSEM IPM driver
is still functioning with this dummy property.
Signed-off-by: Celina Sophie Kalus <hello@celinakalus.de>
Add a device tree binding for the new driver. Since there already
exists an IPM driver using the unsharable hardware semaphore interrupt,
the new driver is not added to any boards or SOCs per default to avoid
compatibility problems. See #37300 for the IPM driver.
Signed-off-by: Celina Sophie Kalus <hello@celinakalus.de>
Add a definition of SUIT storage, so there will be a common source of
the SUIT storage location for both SDFW and scripts generating SUIT
storage areas, assigned to local domains.
Signed-off-by: Tomasz Chyrowicz <tomasz.chyrowicz@nordicsemi.no>
Add support for the memory controller by utilizing QSPIC2. The latter is
capable to drive both NOR and PSRAM memory devices. For this to work,
the RAM driving mode is enabled.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
This commit adds support for the I2C which
can be found in Apollo3 SoCs, it can work in
both DMA and non-DMA modes
Signed-off-by: Hao Luo <hluo@ambiq.com>
Add bindings for NXP MIPI CSI-2 Rx which is a MIPI CSI-2 receiver
connecting a camera sensor to the NXP CSI.
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
TLC59731 is a 3-Channel, 8-Bit, PWM LED Driver with
TI Single-Wire interface (EasySet) protocol.
Signed-off-by: Javad Rahimipetroudi <javad.rahimipetroudi@mind.be>
Convert the ST7735R display to use the MIPI DBI API. Boards and overlays
using this display are also updated.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
