Adding supporting soc files for the k32lx platforms and updating
soc.yaml.
Signed-off-by: Ishraq Ibne Ashraf <ishraq.i.ashraf@gmail.com>
soc: nxp: kinetis: k32lx: Use device tree provided value
This clock frequency value will be defined in the board device tree.
Signed-off-by: Ishraq Ibne Ashraf <ishraq.i.ashraf@gmail.com>
Strictly speaking not a problem for in-tree tooling, but better to
have all binding files follow the same naming convention.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Update the RaspberryPi CSI camera connector nexus gpio in order to only
expose the list of GPIO pins in order to support both 15-pin and 22-pin
connectors as well as 15-pin to 22-pin conversion cables.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Support added for power domain regulation using TISCI added for
devices using the binding ti,sci-pm-domain.
This driver relies on the TISCI layer to make calls to the
device manager core to perform power management.
Signed-off-by: Dave Joseph <d-joseph@ti.com>
Change license owner to Prevas due to initially wrong owner due to company
mix-up during co-development.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Add configurations for setting the pad drive strength and the
interrupt active high/low and od/pp.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Added new binding for macros of possible auxpll frequency settings.
Will be used in future products also.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
I2S driver support standard format, short/long sync, left/right justified.
Supporting 2 channels as a default.
Signed-off-by: Lewis Lee <llee@ambiq.com>
Add USB node to apollo510 qualifier, and apollo510_evb board to enable
USB support on the SoC and its EVB.
Signed-off-by: Chew Zeh Yang <zeon.chew@ambiq.com>
The CH32V003 has a 8 channel, 10 bit onboard ADC. Add an immediate
mode driver and the appropriate pinctrl bindings. Note that the
CH32V003 GPIO pins have both a floating input and an analogue input
mode, and the pinctrl is needed to put the pin in analogue mode.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Make axisram2 which is used in fsbl mode available as well to
chainloaded application in order not to loose 1M of RAM
In order to avoid conflicts with bootloader, verify that code + ro data
of the loaded application won't go further than bootloader start address.
This is done with a linker assert.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
The WCH External Trigger and Interrupt controller (EXTI) supports
between 8 and 22 lines where each line can trigger an interrupt on
rising edge, falling edge, or both edges. Lines are assigned to a
group, and each group has a separate interrupt. On the CH32V003/6,
there is one group of 8 lines, while on the CH32V208 there are
multiple groups with between one and six lines per group.
In the same way as the STM32 and GD32, define an EXTI driver that
configures the peripheral and an internal interface that can configure
individual lines.
Signed-off-by: Michael Hope <michaelh@juju.nz>
RA8P1 has 14 ports (from 0 to d) and 32 external irq while current
driver support 12 ports (0 to b) and 16 external irq.
This add addtional support for remain ports and external irq to be
able to work with RA8P1.
Fix the lack condition GPIO_RA_IOPORT for GPIO_RA_HAS_VBTICTLR
config
Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
STM32U0 specific changes to enable the PM feature.
Base on the power-related code from the STM32U5 target.
Signed-off-by: Mickael Bosch <mickael.bosch@linux.com>
Add support for trng, spi, pwm (gpt), counter (agt), i2c (iic_master),
adc and dac for RA2L1.
Add external interrupt for RA2L1.
Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
1. The edma version 5 share one driver with edma 4.
2. Edma5 tcd structure some difference, Use tcd type to distinguish,
and Edma5 uses 64 bytes for alignment instead of 32.
3. Some platforms have some address offsets for certain memory
when processing from a DMA perspective, such as imx95 cm7 TCM,
so add offset processing.
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
