The CH32V20x and CH32V30x SoCs have 16 pins per GPIO bank, but in the
devicetree, `ngpios` was incorrectly set to 8.
Fix the devicetrees by setting the correct value.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
- Add support for gpio interrupt on RX130.
- Add support for gpio-keys input subsys on RSK_RX130_512KB boards.
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
Add support for gating/ungating IMX8QM/IMX8QXP's ESAI clocks and the
AUD_PLL_DIV_CLK0 clock used as source for ESAI's EXTAL.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
The st,stm32-qspi compatible is defining the reg property
with the register address and size at first index
followed by the external mem base address and max allocated size.
For the stm32F412, stm32F7, stm32L4, stm32H7, stm32WB series.
qspi is addressing max 256 MBytes from 0x90000000.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Allow setting fifo-highres from DT, also unify the
naming of all registers and expand to a more complete list.
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Add initial support for i2c on Renesas RX MCU
This driver is controlling the RIIC HW of RX MCU for i2c bus
interface on Zephyr
Only master mode is supported
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Add nPM1304 device tree bindings. Extract the properties common to
nPM1300 and nPM1304 into npm13xx-common files.
Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
Device tree edits to add DMSC system controller support for
AM2434 EVM. This includes the addition system-controller and
secure-proxy mailbox nodes in arm46x_main.dtsi.
Signed-off-by: Dave Joseph <d-joseph@ti.com>
The cpurad_hsfll is not yet supported by the NRFS DVFS service,
disable it to prevent driver from being loaded.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Create and select the proper module device tree file which loads the
correct radio config for the MGM240P module.
Signed-off-by: Tamas Jozsi <tamas.jozsi@silabs.com>
This enables the clock_control driver build on bl60x.
It is currently deferred init, due to being incompatible
with current SDK-based boot, to avoid later giant PR.
Signed-off-by: Camille BAUD <mail@massdriver.space>
The st,stm32-ospi compatible is defining the reg property
with the register address and size at first index
followed by the external mem base address and max allocated size.
For the stm32H7, stm32L4plus, stm32L5, stm32U5 series.
ospi1 is addressing max 256 MBytes from 0x90000000
ospi2 is addressing max 256 MBytes from 0x70000000
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Update the description of the bindings to match the
xspi-nor-flash node properties: size in expressed in Bits
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Use the new and appropriate "st,stm32n6-pinctrl" compatible for the pinctrl
in DTSI for STM32N6 series.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Add a new binding for the pinctrl controller of STM32N6 series.
The specificity of this series is the "I/O retime" feature not present on
other series. This new binding exposes pinctrl properties to configure this
feature.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
This dts include file is for certain stm32 boards
such as the stm32l552zc,which have a memory size
of 256KB for both flash and RAM peripherals.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
