The uart driver for nRF54h20 doesn't call pm_device_runtime_enable().
During an uart driver init `pm_device_driver_init()` return early,
because the `pm_device_is_powered()` returns `false`. Power domains,
where uarts are instantiated, are disabled: `pm->domain->pm_base->state`
is not equal to `PM_DEVICE_STATE_ACTIVE`.
At the end of the day, an uart instance is left disabled.
This is a workaround to make the uart usable when CONFIG_PM,
CONFIG_PM_DEVICE and CONFIG_PM_DEVICE_RUNTIME are enabled.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
This follows change of ethos-u core driver (hal_ethos_u) which
removes cache flush/invalidate mask function ethosu_set_basep_cache_mask.
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
Remove the hash node from STM32755x SoC DTSI. The node was broken
(wrong node name and compatible property) and seems unused and moreover
most STM32H7xx have an HASH peripheral so a proper fix would rather
be to add the node to all relevant SoC. This will be done later, if
the need arises and after proper validation.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Create separate memory regions for each OFS register. With a single
region the linker will gap fill the load segment with zeros between
each option setting section that gets placed in the region when
generating the .elf file.
Signed-off-by: Jeremy Dick <jdick@pivotint.com>
Introduce nordic NRFS SWEXT power domain bindings and add it to
relevant SoC devicetree files.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add the option to specify an alternate ADC gain value to use if the
initial measurement saturates the range. This enables higher data
resolutions when the values are small compared to the maximum signal
values, while still supporting the maximum.
As a concrete example, measuring charge currents from a small solar
panel (0 - 50mA), while also supporting high USB charge currents
(up to 1A).
Signed-off-by: Jordan Yates <jordan@embeint.com>
Add a driver for the VIRTIO Ethernet device.
This is a minimal driver which sets a MAC address and transmits packets,
but does not support any extra features like the control channel or
checksum offloading.
Confirmed to work with the networking subsystem samples. For example, the
zperf sample shows a result of 85 Mbps download and 14 Mbps upload.
Signed-off-by: Jakub Klimczak <jklimczak@internships.antmicro.com>
Enables bbram driver for motorola, mc146818 under its MFD
to access the RAM of the RTC.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Enabled Motorola, mc146818 MFD, which implements RTC
read/write operations and prevents data corruption
by synchronizing these operations.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Bit 8 of AHB3 is reserved, there is no clock-enable bit for the flash
controller according to the Reference Manual.
Signed-off-by: Arthur Gay <arthur.gay@marshmallow.kids>
The MCU_M4FSS has a total of 256KB of SRAM divided into two banks: 192KB
of I-RAM, and 64KB of D-RAM. The I-RAM memory is intended mainly for M4F’s
instruction code, and D-RAM for M4F’s data. The M4F allows
concurrent fetch for instruction code and data via dedicated buses (I-Code
and D-Code, respectively).
The MCU_M4FSS supports unified memory for both banks (I-RAM and D-RAM),
which means instruction code and data can be placed in any bank. Since CM4
converts unaligned accesses into word-aligned accesses internally, cross
RAM access also work fine in unified memory mode.
By having a single parent node for SRAM, we allow both operating modes,
i.e. separate I-RAM and D-RAM and unified SRAM easily.
Also fixed the incorrect D-RAM address.
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Add gpio binding file for Microchip Port g1 IPs and
add gpio node in dtsi files.
Signed-off-by: Muhammed Asif <muhammed.asif@microchip.com>
Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
Adds common and SoC-specific .dtsi files for the Microchip
PIC32CM JH family. These files define core peripherals,
address maps, and interrupt controller structure shared
across the PIC32CM JH variants.
Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
