This fixes the following warnings:
> unit address and first address in 'reg' (0x40094000) don't match for
> /soc/peripheral@40000000/usbhs@144000
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Now that we support internally connected channels we should make the
pinctrl configuration optional.
Signed-off-by: Corey Wharton <xodus7@cwharton.com>
Add MCO device nodes to the STM32 boards.
The set of supported boards are chosen to replace what is currently
supported in Kconfig.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
Add clock sources that can be output by the MCO on the stm32f1x and
stm32f10 connectivity line devices.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
Add board support for eval board ganymed_bob, which
is a break-out-board for both soc variants.
Variants of the soc are GBM and GEN1.
Signed-off-by: Sven Ginka <s.ginka@sensry.de>
Indicate in the STM32WB0 power controller binding that the SMPS output
current limitation is a feature only available on STM32WB05 and STM32WB09.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
`-` is preferred over `_` in devicetree property names.
Since, change `clk_src`, `clk_div`, and `clk_out_div` to
`clk-src`, `clk-div`, and `clk-out-div`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
There is an issue on the SHI hardware peripheral to detect CS
rising/failing with bits CSnFE/CSnRE in the EVSTAT2 register in
npcx9m7fb chip. This commit workarounds it by using MIWU to detect the
CS rising and failing.
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
The internal flash size of npcx9m7fb is 512KB. Reduce the default
Code RAM size from 320KB to 256KB because the Code RAM size is limited
by FLASH_SIZE/2 in the Chromebook EC application.
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Add common default flash partition layout for nrf52840 as many boards
have used identical flash layouts.
The default flash layout was updated to remove scrach in 2022 (9a84258)
but almost all boards were still using the previous layout, so this
updates them to the new layout with allows for larger applications.
This commit also incorporates feeedback from @nordicjm in PR #77791 to
change slot0 to 0x00077000 and slot1 to 0x00075000: "If you use swap
using move, you need a sector for the data to be moved up by, and you
need space for the swap status fields, which is about a sector, so by
making the changes here you get the full 0x65000 for an image, without
these changes you get 0x64000.
Signed-off-by: Jacob Winther <jacob@9.nz>
Adds Device Tree include files for all MCUs in the STM32WB0 series.
These DTSI files only contain the supported peripherals for now.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Add timer instance in device tree
Add timer yaml file
Timer0/1/2/3 are common for MAX32xxx MCUs
MAX32655 has additional Timer4/5 which are low power timers
Co-authored-by: Mert Vatansever <mert.vatansever@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
Add information to the device tree if UARTE instance has a HW feature
which is the ENDTX_STOPTX short.
Add this property to all instances in nrf54hl15, nrf54l20, nrf9280
and nrf54h20.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
we have four i2C peripherals .
- three shared between stm32u031/73/83
- One between stm32u073/83
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
There are numbers of drivers for different PCA(L) series chip. They
share similiar register layout and control logic. This driver intends
to unify these drivers for PCA(L)xxxx series i2c gpio expanders.
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
Implement an option manual reset of the PCAL64XXA to allow the external
implementation of a retention of the port expander state.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
