Gives number of the Extended Interrupts and Event Controller (EXTI)
interrupt line connected to the RTC Alarm event.
Used on all series, except WBAX & U5X, where RTC Alarm interrupt is
routed directly to Nested Vectored Interrupt Controller (NVIC) and to
Power Control (PWR) wake-up pins.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Move the Domain IDs from `nrf54h20.dtsi` into its own header file.
Additionally, include another header with Owner IDs.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
This change allows to use DTR line driven from external serial port
that when active (low) will prevent UART device from going to sleep.
It will also wake up platform when DTR line becomes active.
DTR line is often activated in serial port connected to host computer
when operating system opens serial device like COMx for Windows
or /dev/ttyACMx /dev/ttyUSBx for Linux based systems.
DTR line (specified in device tree) will be used by WAKEUP and PDC
controllers (via GPIO driver) to handle DTR line changes.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
This change allows to wake up UART from sleep mode when
low level on inactive UART is detected during platform sleep.
Timeout can be specified for each UART separately in device tree.
If one of the UARTs is selected as console sleep timeout is taken
from Kconfig same way other platform configure same functionality
using CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
UART2 and UART3 (unlink UART) do support hardware flow control.
This simply add necessary flag that is already handled in the code.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Correction of the reg address of enet2 for nxp_rt1060.
Regression introduced at 537d5c310c
Signed-off-by: Matthias Alleman <matthias.alleman@basalte.be>
This commit adds flash controller instance for Ambiq Apollo3 Blue SOC
and Apollo3 Blue Plus SOC.
Also create the partitions on this flash controller node for apollo3_evb
and apollo3p_evb.
Signed-off-by: Aaron Ye <aye@ambiq.com>
If no HSFLL needs trimming, then `trim_hsfll()` should be compiled out.
This makes it easier to reuse the rest of `soc.c` out of tree.
Furthermore, some HSFLL instances can be trimmed before booting Zephyr,
so the FICR client properties in the DT binding should not be required.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
The emulated GNSS driver behaves like a GNSS, implementing
device pm and the GNSS APIs, using only kernel features (
zephyr work queue and uptime) making it buildable on all
zephyr targets.
The purpose of this device driver is to tailor and validate
the gnss api test suite.
Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
Add mfd_adp5585 and gpio_adp5585 driver. This driver enables ADP5585
as an GPIO expander.
This chip is used as an GPIO expander on i.MX93 EVK. GPIO pinctrl,
read/write and interrupt is supported.
Note that ADP5585 has 2 GPIO banks with 5 pins each. The driver combines
two group into a 16-bit port. Index 0~4 correspond to R0~R4 lines, index
8~12 correspond to C0~C4 lines. Index 5~7 is reserved unavailable.
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
The counter driver needs to know what is the maximum
counting frequency of each timer peripheral.
Let's add it to its DT.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add binding for adi SDP-120 connector and header file
with marcos to map signals using signal names.
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
Add driver for IS66WVQ8M4 PSRAM, using the MCUX FlexSPI interface to
write data to the PSRAM device.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Some instances of the FlexSPI IP support a different clock source being
used for port B of the FlexSPI instance. Add a devicetree property and
driver support to enable configuring this property of the hardware.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Added EXMIF peripheral DTS description and bindings.
The peripheral operates as an SPI device.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
In the <board>.dts file, the definition for usart0 was found to be
redundant as the same information is already provided in the included
.dtsi file. this commit removes the duplicate definition of usart0,
resulting in a cleaner and more maintainable device tree configuration.
Signed-off-by: Arunmani Alagarsamy <arunmani.a@capgemini.com>
Add support for similar adin1100 phy, boath are 10Base-T1L,
only difference is that adin1100 connects through r/mii.
Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
Add mdio node for h5 and h7 series.
Since MDIO registers are part of the same ETH hw IP, keeping mdio
node just as a child of mac/eth, cannot see as appropriate to assign
an adddress to it.
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
MDIO is part of the ETH IP, but some phy chip may need a
specific phy driver to set up certain vendor registers enabling
particular features.
Add support for stm32 mdio access.
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
Add Sequans GM02S modem binding using the sqn vendor prefix.
The modem has an active low reset signal.
Signed-off-by: Thibo Verheyde <thibo@dptechnics.com>
Intial driver adding intial script to receive only GGA, RMC and GSV
NMEA messages, configuring fix rate, setting enabled system and adding
power management with the module on-off pin.
Signed-off-by: Jeronimo Agullo <jeronimoagullo97@gmail.com>
Set RNG address to its non-secure alias.
See RM0493 STM32WBA5 Reference manual for details.
Using the secure alias (0x5..)instead of the non-secure alias (0x4..)
for this peripheral results in a SecureFault during kernel init if
TrustZone is activated, Zephyr is running as NSPE and RNG is
enabled.
Signed-off-by: Louis Feller <louis.feller@st.com>
Commit 246ea739bb ("dts/arm/st: wl: increase Sub-GHz SPI frequency to
12MHz") increased the Sub-GHz to 12 MHz. This matches the SX126x
datasheet, but there is no information about the maximum speed in the
STM32WL datasheet or reference.
This works fine when not using DMA. However with DMA activated (adding
entries to the device-tree and enabling CONFIG_SPI_STM32_DMA), I have
encountered some rare corruption. When it happens, the read from the
Sub-GHz device gets an extra 0x00 byte prepended, which confuses the
LoRaMac-node library and causes reception failures. Decreasing the
frequency to the next round number, that is 8 MHz (i.e. increasing the
prescaler from 4 to 6) fixes all the issues I encountered.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Spell checking tools do not recognize "iff", replace with "if and only if".
See https://en.wikipedia.org/wiki/If_and_only_if
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Convert the ht16k33 to use the input subsystem. This can still be used
with the kscan API with the zephyr,kscan-input driver, or use the
input-keymap one to generate input codes instead.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
1) Replace master/slave in API for new terms in eSPI spec 1.5
2) Reflect eSPI VW change and macro changes across eSPI drivers
3) Update terms in eSPI driver sample and eSPI test driver
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Update m2l31x.dtsi for adc support and update adc_numaker.c
to support acquisition time in 0~255 ADC ticks.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Add basic functionality of Renesas SD/MMC driver. It can be used
for both gen3 and gen4 R-car boards, but tested only with H3ULCB,
Salvator XS M3 and Spider boards. This driver working with SDHC
subsystem.
The driver supports regularal reading/writing throught SD/MMC
controller buffer, DMA mode w/o interrupts and timing tuning.
Add gpio5 and sd0 nodes to h3ulcb and salvator xs which are needed
for working with SD cards. The GPIO node is needed for switching
voltage on SD card through gpio regulator driver.
Notes:
* the driver doesn't support SPI mode;
* SCC tuning and DMA mode based on IRQs are enabled by default;
* an address of a data buffer has to be aligned to 128 bytes if it
is not, driver will use non-DMA mode automatically;
* Renesas MMC DMAC doesn't support 64-bit DMA addresses, so for
case when we have 64-bit xref data address we use non-DMA mode;
* SD/MMC controller supports block size between 512 and 1 with
a lot of restrictions, more details you can find in code;
* support of HS400 mode isn't implemented inside driver.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
This commit updates the device tree and memory header file
for the Intel MTPM 1.5 platform to define the LSBPM and
HSBPM registers.
Changes include:
- Added node definitions for 'lsbpm' and 'hsbpm' in
intel_adsp_ace15_mtpm.dtsi
- Updated adsp_memory.h
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
This commit updates the device tree and memory header file
for the Intel LNL 2.0 platform to define the LSBPM and
HSBPM registers.
Changes include:
- Added node definitions for 'lsbpm' and 'hsbpm' in
intel_adsp_ace20_lnl.dtsi
- Updated adsp_memory.h
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
This commit updates the device tree and memory header file
for the Intel cAVS 2.5 platform to define the LSBPM and
HSBPM registers.
Changes include:
- Added node definitions for 'lsbpm' and 'hsbpm' in
intel_adsp_cavs25.dtsi and intel_adsp_cavs25_tgph.dtsi
- Updated adsp_memory.h
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
