GPIO hardware in Microchip MEC parts is the same except for the MUX
field (number of alternate functions). We modify the old XEC PINCTRL
driver to work on all MEC parts and also be independent of HAL and
CMSIS register structures. During development we found a DT issue
with DT_ENUM_IDX_OR always inserting the default value. Worked around
by converting slew rate and drive strength to YAML integer type and
created defines for the values in the dt-bindings header.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Add device tree property to configure LPTMR free-running mode instead
of hardcoding it to disabled.
The freerunning property controls counter reset behavior:
- If false (default): Counter resets after compare match
- If true: Counter resets only on overflow, continues after compare
This allows per-instance configuration of the LPTMR timer mode based
on application requirements without code changes.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
mcxaxx6: mcxa266, mcxa346, mcxa366.
1. Add power state nodes for mcxaxx6, including
sleep, deepsleep and powerdown.
2. Add power management related peripheral nodes
for mcxaxx6, including spc, cmc, vbat and wuu.
3. Add 'zephyr,cortex-m-idle-timer' node in frdm_mcxaxx6.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
1. Add power state nodes for mcxa153, including
sleep, deepsleep and powerdown.
2. Add power management related peripheral nodes
for mcxa153, including spc, cmc, vbat and wuu.
3. Add 'zephyr,cortex-m-idle-timer' node in frdm_mcxa153.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
1. Add power state nodes for mcxa156, including
sleep, deepsleep and powerdown.
2. Add power management related peripheral nodes
for mcxa156, including spc, cmc, vbat and wuu.
3. Add 'zephyr,cortex-m-idle-timer' node in frdm_mcxa156.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
- Moves nxp,imx-gpt.yaml from the timer to the counter folder,
as this is the binding for the counter driver
drivers/counter/counter_mcux_gpt.c
- Fixes: #100947
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
This commit adds the main DTS configurations required
to enable MSPI/OSPI/QSPI support on STM32.
Signed-off-by: Sara Touqan <zephyr@exalt.ps>
Signed-off-by: Sarah Younis <zephyr@exalt.ps>
Signed-off-by: Mohammad Odeh <zephyr@exalt.ps>
Add the node I3C4 in non-secure context to dtsi. Others I3C nodes cannot
be added as they rely on EXTI1 interrupt lines that is not supported yet
for the STM32MP2.
Co-authored-by: Charles Wenger <charles.wenger@savoirfairelinux.com>
Signed-off-by: Tanguy Raufflet <tanguy.raufflet@savoirfairelinux.com>
Add property to enable eMIOS instances to reference a global timebase
provider, either from itself or another eMIOS instance, enabling
synchronized timing operations across multiple instances.
Signed-off-by: Ha Duong Quang <ha.duongquang@nxp.com>
1. Add power state nodes for mcxnx4x soc dtsi, including
sleep, deepsleep and powerdown.
2. Add power management related peripheral nodes
for mcxnx4x soc dtsi, including spc, cmc, vbat and wuu.
3. Add 'zephyr,cortex-m-idle-timer' node in mcx_nx4x_evk_cpu0.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
CS40L5x is a family (CS40L50/51/52/53) of haptics drivers designed
for trackpads, tablets, and automotive applications.
This PR provides basic functionality for ROM features and serves
as a starting point for the upstream driver. Notably, RAM firmware,
SPI, and certain CS40L51/52 features (e.g., diagnostics,
closed-loop algorithms) are excluded from this PR.
Tested with internal/external boost configurations. Tested I2C.
Tested all ROM features with each device variant (50/51/52/53),
including ROM playback, "buzz" playback and configuration, custom
haptics playback and configuration, trigger playback and configuration,
runtime haptics logging, and gain configuration.
Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
stm32h523/33Xe devices have different addresses than stm32h562/72/73xx
(RM0481 fig. 21).
Tested on a custom board with stm32h523cet6 where the board crashed when
accessing sram3.
Signed-off-by: Cezar Burlacu <cezar@embeddedp.ro>
PR #93198 introduced the support for the timer kernel
clock for most STM32 series.
it was missing for STM32WB0 serie.
These changes are required for the related timer tests/samples
to pass.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
1. Removed nxp,sensor-lpcmp.yaml and merged its
properties into nxp,lpcmp.yaml. Now a single
dt-binding (compatible: nxp,lpcmp) is shared
by two drivers: the sensor API-based LPCMP
driver and the comparator API-based LPCMP driver.
2. Updated the driver and samples accordingly.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Added a counter driver for the RPI Pico/RP2040 that implements
programmable interval timer (PIT) functionality using the PWM HAL.
Signed-off-by: Jan Behrens <jan.behrens@navimatix.de>
Add devicetree binding for the NXP LPC CRC controller
(compatible "nxp,lpc-crc") with required reg property.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Minimal board definition for the Elan em32f967 SOC:
- Includes DTS, YAML, and Kconfig files
- Provides board.cmake with misc-flasher for CI/build
- Actual flashing is not included in this PR
Signed-off-by: Johnny Chuang <johnny.chuang@emc.com.tw>
Add initial support for the Elan em32f967 SoC based on ARM Cortex-M4.
Minimal SoC definition for upstream:
- soc.h, Kconfig, and CMakeLists.txt provided for completeness
- This PR does not implement drivers or UART functionality
Signed-off-by: Johnny Chuang <johnny.chuang@emc.com.tw>
Add minimal DT binding headers and matching YAML files for the
Elan em32f967 SoC. The new definitions are required to build the
sample board and follow the upstream style.
Signed-off-by: Johnny Chuang <johnny.chuang@emc.com.tw>
There are cases where the device can operate by polling
without using interrupts, so `interrupts` are not mark as required.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Add adxl345_attr_set_range() to allow runtime config.
of the accelerometer's measurement range via the
SENSOR_ATTR_FULL_SCALE attribute.
The function maps the requested range to the nearest supported
ADXL345 range (±2g, ±4g, ±8g, or ±16g) and updates the device
configuration accordingly.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Add a new driver for the NXP TempSense temperature
sensor found in various NXP MCUs, such as the MCX
family. The driver reads temperature data from the
TempSense peripheral and provides it via the Zephyr
sensor API.
The TempSense peripheral details can be found in the
NXP MCXE31x reference manual chapter 78.
reference manual can be found at:
https://www.nxp.com/webapp/Download?colCode=MCXE31XRM
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
This commit enhances the SAR ADC driver by adding
support for clock frequency selection. The clock
frequency can now be configured via the devicetree,
allowing for better optimization of ADC performance
based on application requirements.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
This PR combines node content in the same file spread over multiple
node definitions.
This PR has not funtional changes to the boards
Signed-off-by: Kyle Bonnici <kylebonnici@hotmail.com>
Add the inter-processor interrupt (IPI) nodes to the device tree for the
Versal Gen2 platform, as per Versal Gen2 Technical Ref Manual (AM026)
Signed-off-by: Ajay Neeli <ajay.neeli@amd.com>
Add the inter-processor interrupt (IPI) nodes to the device tree for the
Versal-NET platform, as per Versal-NET Technical Reference Manual (TRM).
Signed-off-by: Ajay Neeli <ajay.neeli@amd.com>
Add device tree bindings for the AMD-Xilinx Inter Processor Interrupts
(IPI) mailbox.
The IPI architecture allows the passing of messages across the system
without the complications of autonomous read-write transactions and
polling inefficiency. The notification of the interrupt is also
possible without message buffers on some platforms. Some IPI channels
are hard-wired to particular core while others can be configured to
assign to any core on AMD-Xilinx heterogenous multiprocessor platform.
Signed-off-by: Ajay Neeli <ajay.neeli@amd.com>
Add CAN FD support for MCXN SOC family, including mcxn23x, mcxn94x
and mcxn54x.
Tested with tests/drivers/can.
Fixes#91138
Signed-off-by: William Tang <william.tang@nxp.com>
Fix incorrect LPTMR prescaler/glitch filter mapping that led to wrong
frequency calculation and wrong hardware configuration.
- Calculate effective counter frequency correctly:
* Time Counter mode: divide by 2^(value + 1)
* Pulse Counter mode: divide by 2^value
- Map prescale-glitch-filter directly to the HAL enum (no offset math)
- Add prescale-glitch-filter-bypass DT boolean (default false)
- Restrict prescale-glitch-filter to 0..15 and update bindings/DTS users
- Add build-time validation for Pulse mode (value 0 requires bypass)
Signed-off-by: Holt Sun <holt.sun@nxp.com>
