Counters configuration is missing in Devicetree for NXP MCX C series.
Add lptmr, rtc and pit configuration to Devicetree.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
If the `divider-int-0` or variations of these for each channel properties
are not specified, or if these is 0,
the driver dynamically configures the division ratio by specified cycles.
The driver will operate at the specified division ratio if a non-zero
value is specified for `divider-int-0`.
This is unchanged from previous behavior.
Please specify ``divider-int-0`` explicitly to make the same behavior as
before.
In addition, the default device tree properties related to the division
ratio have been removed.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
NXP mcxc series has boot source configured to ROM. ROM bootloader
waits 5 sec for active peripheral detection timeout before jumping
to application in flash which makes booting very slow.
Change configuration to boot from flash and allow boot source
selection by external pin.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
IAP is a reference to the method of software interaction with the flash
used in the current driver implementing support for this flash. The
DT compatible should not be named like this.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add a new `andestech,nceplic100` binding that inherits from the
`sifive,plic-1.0.0` binding. This is so that the Kconfig
`DT_HAS_ANDESTECH_NCEPLIC100_ENABLED` would be generated during
build.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
MAX14906 industrial 4 channel Input/Ouput GPIO expander with diagnostics.
Per channel diagnostics for open wire, over current.
Global diagnostic for power supply, communication and various fault
conditions.
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
Move the process of replacing numerical values with macros to
the header, and set the division ratio in a numeric without
using macros in the device tree.
Change `clk-div` defined in `renesas,ra-cgc-pclk.yaml` to `div`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
DeviceTree typically references the clock source using the `clocks`
property defined in `base.yaml`, so we'll change it to this.
Also delete the custom clock source definitions in
`renesas,ra-cgc-pclk-block.yaml`, `renesas,ra-cgc-pclk.yaml`, and
`renesas,ra-cgc-pll.yaml`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Changes the path name of a DTS node so that it can be used
as the stem of a BSP macro.
All nodes to be changed are referenced via labels,
so only the name is changed.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Having the lowest possible interrupt priority is causing the
tests\arch\arm\arm_irq_zero_latency_levels test to fail.
This test reserves 2 priority levels for the low latency interrupts.
Since CYW20829 supports 3 interrupt bits, 6 becomes an invalid
value when 2 levels are reserved for the low latency interrupts.
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Property "block-cycles" is required for node "zephyr,fstab,littlefs",
but source code did not get the value from dts file, now add it.
Additionally correct the wrong description of property "block-cycles"
in binding file.
Signed-off-by: Paul He <pawpawhe@gmail.com>
Update ADC bindings documentation to state that a domain clock is now
necessary if asynchronous clock is selected.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For STM32L1, U5 and WBA, the ADC always uses an asynchronous clock source,
so we add the default clock source in the clock node.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Some IBI TIR packets can be larger than the ibi data fifo size
which can prevent it from receiving the full packet. This adds
a data struct in to the driver data where data can be pushed
to as data is being transfered.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Enable support for 8 bit 8080 mode in the NXP LCDIC driver. Support
for programming the minimum duration of the write active/inactive signal
is also added, since this will be required to support high display
clocks in 8080 mode.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add mailbox node used for inter-process communication.
For DSP, we have a direct interrupt line to the core.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Change the STM32 Temperature Sensor bindings to accept the average slope
value in string form instead of integer. With this change, it is possible
to use the raw decimal value found in each MCU's datasheet instead of
needing to scale it (differently depending on series!). This also allows
regrouping the property in a single file to reduce duplication.
Also update all DTSI files affected by this change and the dietemp driver
to accept the property's new format.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Improve the STM32 dietemp sensor bindings by rewording the descriptions
of bindings and properties.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Reduce duplication in STM32 dietemp bindings by regrouping the 'ntc'
property declared in both "st,stm32-temp" and "st,stm32c0-temp-cal"
to the shared "st,stm32-temp-common" binding.
"st,stm32-temp-cal" is also modified to block 'ntc' property on include as
no dual-calibration sensors to date require it (this could be changed later
when need arises).
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Set the 'avgslope' property of 'st,stm32c0-temp-cal' to required, and
remove its default value, to ensure new series cannot be introduced without
setting the property to the correct value explicitly.
This change does not require any DTSI modification, because there are only
two files using this compatible (stm32f030.dtsi / stm32c0.dtsi), and both
of these already set 'avgslope' explicitly.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Set the 'avgslope' property of 'st,stm32-temp' to required, and remove its
default value, to ensure new series cannot be introduced without setting
the property to the correct value explicitly.
This change does not require any DTSI modification, because there are only
two files using this compatible (stm32f1.dtsi / stm32f2.dtsi), and both of
these already set 'avgslope' explicitly.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Set the 'v25' property of 'st,stm32-temp' to required, and remove its
default value, to ensure new series cannot be introduced without setting
the property to the correct value explicitly.
This change does not require any DTSI modification, because there are only
two files using this compatible (stm32f1.dtsi / stm32f2.dtsi), and both of
these already set 'v25' explicitly.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
The typical value for V25 is different on the STM32F100 line compared
to other STM32F1 MCUs. Update the DTS property to the correct value.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Add the missing 'avgslope' property to the DTSI for STM32F030/STM32F070.
This fixes improper results being returned by the driver: the correct
value for the average slope is 4.3mV/°C (4300 µV/°C), but the binding's
default value of 2.53mV/°C was used instead, since property was missing.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Remove the "Negative Temperature Coefficient" attribute from the STM32F2
die temperature sensor node, as it does not correspond to the hardware.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Add virtual Cortex R8 SoC. This target does not represent a real SoC,
but can be easily run in Renode.
This will allow to easily test basic architecture support.
Signed-off-by: Krzysztof Sychla <ksychla@antmicro.com>
Signed-off-by: Marek Slowinski <mslowinski@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
Add the <requires-ulbpr> property from the "jedec,spi-nor-common.yaml"
to the existing st,stm32-qspi-nor.yaml. So that external quad-NOR with
unlock the Global Block Protection (BPR) (opcode 0x98) is accepted.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
- Driver always initializes the device in the suspended state
- If CONFIG_PM_DEVICE_RUNTIME=n, device PM callback will be called with
RESUME action, thus setting up pins to default state and enabling the
peripheral
NOTE: when CONFIG_PM_DEVICE=n, the pinctrl sleep state will not be
available (-ENOENT) and so never applied, thus avoiding a pin
suspended->active transition.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add nodes for LPTMR. This is sufficient to enable their use as counter
devices when set to status okay.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add DT node and clocking of TPM peripherals, which are used for PWM.
Also change the soc clock enable code to not use preprocessor
conditionals.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add peripheral bridge definitions to DT, this also fixes the base
address of the GPIO peripherals which were faulting in the driver due to
the wrong reg address.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
