This commit includes the following changes:
1. Add top level CMakeLists.txt entry and Kconfig.
2. Add bindings for opamp-controller.
2. Add bindings for nxp,opamp and nxp,opamp_fast.
3. Implemented NXP opamp and opamp_fast device driver.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add optional fast-memory-region property to the Ethos-U driver. When
present in the devicetree, the driver passes the region base and size
to ethosu_init(), allowing platforms to use dedicated SRAM for improved
NPU performance.
If the property is not specified, the driver falls back to using NULL/0,
keeping existing behavior unchanged.
Signed-off-by: Johan Alfvén <johan.alfven@arm.com>
Added support for RTIO stream.
Also added sampling_period property to the DTS. This is for setting the
sampling period when streaming is used.
Hardware or kernel timer can be
used for this.
To use hardware timer you need to add it to the DTS. Example:
{
chosen {
zephyr,adc-clock = &counter0;
};
};
Signed-off-by: Vladislav Pejic <vladislav.pejic@orioninc.com>
Add nodes for the GPIO controller (controlling pins PA00-44). Naming is
a bit confusing. In some places you'll find HPSYS_GPIO, other GPIO1,
pins are named PA00-PA44... I've chosen "GPIOA". Because the Zephyr GPIO
API assumes a maximum of 32 pins per controller, we have to split the
controller into 32-bit wide blocks. In reality, the controller
internally works like that (see the `reg` addresses), however, the whole
block is clocked by a single RCC _switch_.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
SiFli SF32LB SoCs have a single GPIO controller block which manages all
pins (> 32). However, Zephyr API expects ports to have up to 32 pins. So
in order to make things compatible, we introduce a Zephyrism in
devicetree: a parent node with common properties (e.g. IRQ, RCC clock,
etc.) and children nodes for each 32 pin block. See upcoming devicetree
definition for more details.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
So we can reference later to any of the PAD_XX_YY registers from e.g.
GPIO nodes, where we need to write pad configs like pull-ups.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
add support for pca9538, pcal9539.
Add support for pcal6408 and pcal6416, which is originally supported
by pcal64xxa driver. These device has the same register layout as
pcal9538 and pcal9539 respectively, which means they can be seamlessly
supported by pca_series driver.
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
Add pinctrl dts node for PIC32CM JH family devices and
update binding file for Microchip Pinctrl Port G1 IP
Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
- Add a new counter driver implementation based on the PDL for
Infineon CAT1B devices. This enables support for hardware
counters on the PSC3M5 platform.
- Add IFX_TCPWM_Counter_DeInit and IFX_TCPWM_Counter_Init
macros to include/zephyr/drivers/timer/ifx_tcpwm.h
and sort all of the macros in that file
Signed-off-by: Yurii Lozynskyi <yurii.lozynskyi@infineon.com>
- It's not fully enabled.
- Chrome ISH cannot reach such deep low-power state for current scenarios.
- Chrome ISH's panic info mechanism needs SRAM content kept with ISH
reset, but D0i3 has whole SRAM banks power-off.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
- Add SOC interrupt properties and interrupt-names ("reset_prep", "pcidev",
"pmu2ioapic") to intel_ish5 DTS files so PM IRQs are discoverable via DT.
- Move SEDI PM initialization and IRQ setup into ISH SOC PM init:
- Remove the direct call to sedi_pm_init() from soc_early_init_hook in
soc.c.
Previously SEDI code has those IRQ numbers hard coded and calls Zephyr APIs
to connect IRQs, which should be avoided.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
1. Added siwx91x power domain node in siwg917.dtsi
2. Updated UART device nodes to reference the newly added power domain.
3. Implemented power domain driver to manage power domain transitions
for the SoC.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
PM and PM_DEVICE should be enabled, by default. The latter, require that
timer2 node be employed and reserved for the OS tick generation.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Add bindings for the SF32LB52X SoCs PINMUX peripheral. Note that
SF32LB56X SoCs contain a compatible IP (not others, where HPSYS_CFG is
not required), so if SF32LB56X support is added, binding could be
adjusted to reflect 52x/56x support.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This is defined as a subnode because RCC is a MFD device (clock and
reset controller), however, Zephyr does not allow >1 device per DT node!
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add bindings for the SiFli SF32LB PMUC. PMUC is a sort of "syscon" type
register block used to control multiple power-management related stuff.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Refer to Ch 2 "Clock and Reset" from reference manual. Some may require
specific bindings in the future if they can be configured (e.g. RC48).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
SiFli SF32LB AON module controls certain low-power or clocks, e.g.
enablement of HXT48 on different LP modes, etc.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
SiFli SoCs have a multi-purpose register set named HPSYS_CFG, which we
can treat as a "syscon".
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
SRAM is segmented as:
- RAM0: 128K (DTCM)
- RAM1: 128K
- RAM2: 256K
where:
- RAM0 can be accessed by all peripherals except PTC1/2.
- RAM1/RAM2 have its own port, so e.g. master 1 can access RAM1 while
master 2 can access RAM2.
Depending on the application, one may decide to just use the whole RAM
as a single block, split RAM0 (DTCM) and RAM1/2, etc. For now, provide 2
schemes:
- Use all SRAM as a single block
- Use RAM0 (DTCM) + RAM1/2
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
