Add bindings for nxp display interfaces. These bindings describe the 6
and 40 pin FPC connectors used for displays on several NXP EVKs using
gpio nexus nodes.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add devicetree node of stm32 PWR peripheral that controlls wake-up pins.
The new node includes child nodes for wake-up pins configuration.
We only add these nodes for STM32 SoC series that support Poweroff.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Add DT binding for stm32 PWR peripheral that controlls wake-up pins.
This binding primarily introduces wake-up pins configuration in
a unifed way that takes into consideration the variations between
STM32 SoC series & facilitates the association of GPIO pins with
their corresponding wake-up pins.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Deprecate the CAN controller bus-speed/bus-speed-data properties and rename
them to bitrate/bitrate-data to match the terminology used in other CAN
devicetree properties and the CAN subsystem API.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Make it possible to disble device power management individually per
power state. This allows targets tuning which states should
(and which should not) trigger device power management.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
I chose this approach instead of software rotation because I need it for
an ultra low power project.
Rotation in steps of 0, 90, 180, 270 degrees is done by changing
the data entry modes.
This commit removes the orientation-flipped property as it is redundant.
I made the assumption that the current driver implementation is right
about controller X/Y versus display width/height. The display controller X
parameter matches with the display height (dts) and display controller Y
parameter matches with the display width (dts). It looks like display
manufacturers choose to have it like this because a wider screen probably
makes more sense.
Tested on the reel_board with a 250x122 display (ssd1673 controller)
and a custom PCB with a 200x200 display (ssd1681 controller).
Also tested all orientations with various width/height dts overrides.
Signed-off-by: Sven Depoorter <svndepoorter@gmail.com>
- The MK22FN512VLH12 chip, installed on frdm_k22f,
has 512 KB of Program Flash and 128KB SRAM
according to the K22P121M120SF7RM.pdf manual (page 55).
- Fix the flash size to 512KB (was 1MB).
- Add nxp_k22fn512.dtsi with correct flash size value.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Add a digi_dietemp node for the STM32 Digital Temperature Sensor into
stm32h723.dtsi (used as a base for H723, H725, H730 and H735) and
stm32h7a3.dtsi (used as a base for H7A3, H7B0 and H7B3).
The sensor is not available on other H7 SoCs.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This add basic support for the STM32 Digital Temperature Sensor found
notably on the STM32H7 series. It work in interrupt mode and support
basic power device management.
It does not support the more advanced features like using the
temperature threshold, triggers from LPTIM or using the LSE clock in
during sleep or stop.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Improve the binding descriptions for the atmel,at24 and atmel,at25 EEPROM
compatibles. These compatibles work for a number of different EEPROM
families manufactured by vendors other than Atmel.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This commit refactors the Intel SSP DAI driver to support dynamic
management of SSP IP. This change additionally separates the
management of the DAI part from the management part of the SSP IP.
Key changes:
- Add new static functions to manage SSP IP power.
- Update the DAI SSP configuration functions to use the new management
approach.
- Update device tree bindings and instances to reflect the new SSP IP
management mechanism.
- ace30 (PTL) support.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
This commit adds definition of ACE 3.0 Panther Lake board.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This commit adds support for the SPI which
can be found in Apollo3 SoCs, it can work in
both DMA and non-DMA modes
Signed-off-by: Hao Luo <hluo@ambiq.com>
Fix a compilation error occurring when a prescaler was set for ADC on F1
and F3 family.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add support for the IS31FL3194 3-channel LED driver. This driver can be
configured to handle its outputs as either a single RGB LED or (up to)
three independent LEDs.
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
The native Linux CAN driver supports CAN FD. Change the binding to reflect
this. No functional changes.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The CAN loopback driver supports CAN FD. Change the binding to reflect
this. No functional changes.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Align interrupt numbering with RM0436 for STM32MP157.
This will allow EXTI interrupt for line 6, 7, 8, 9, 10 and 11.
Fixes: ff231fa20a ("dts: stm32: Populate new properties for exti nodes")
Signed-off-by: Sean Nyekjaer <sean@geanix.com>
This is a soc/board integration for the MediaTek Audio DSP device on
the MT8195 SOC, along with a Zephyr mtk_adsp soc integration that will
work to support similar 8186 and 8188 device shortly.
A python loader (similar to cavsload.py) is included that will run in
developer mode on current chromebooks (an HP x360 13b-ca000 was
tested) with an unmodified kernel.
Signed-off-by: Andy Ross <andyross@google.com>
Add an interrupt controller driver for this device. This is an
extremely simple second level controller with per-interrupt-bit
registers for "enable" and "status". There is no internal latching,
so no "clear/ACK" process is needed.
Signed-off-by: Andy Ross <andyross@google.com>
Included the nxp_ke1xz.dtsi file to use the same peripheral info,
and overwrite it for different peripherals
Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
Add DMA channels at SOC level for the LPC55S6x series SOCs, as the dma
requests are SOC specific properties and do not need to be modified at
the board level. Remove any DMA request definitions present at the board
level for the LPC55S69 evaluation board.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Refactored vendor-specific duplicates of uart tx/rx invert properties
into a common dts file uart-controller-pin-inversion.yaml
Signed-off-by: Anuj Pathak <anuj@croxel.com>
This WDT is responsible for monitoring the external
32.728 Hz crystal connected to pins XTAL_32K_P and
XTAL_32K_N. If an oscillation failure is detected
the hardware automatically switch to RTC_RC_SLOW
clock source and triggers an interrupt.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Add a parameter to allow the configuration of the number of address
bytes used by the I2C master. This allows the driver to expose larger
buffer sizes.
Tested with standard linux at24 driver.
Signed-off-by: Bram Vlerick <bram.vlerick@openpixelsystems.org>
This commit should deal with optimizing device's
operation in terms of power consumption. In this
context:
1. Power and rail managers are enabled so that the
device can enter the sleep state and power
rails be set to the min. required levels.
2. Peripheral blocks should be enabled only when
there is need to do so.
3. Define the internal RCX oscillator as default
low power clock. RC32K should not be used as
it drifts significantly due to temperature and
voltage variations. Thus, affecting the whole
system stability regardless of its calibration.
4. PLL should be enabled only when requested and
on board level LP clock should be switched to
XTAL32K to avoid overhead due to RCX calibration.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Behavior of "force"-mode as described in datasheet cannot be achieved if
low-power mode is enabled. After triggering a sampling, the sensor will
not sample again for the period specified in measurement-time.
Signed-off-by: Juliane Schulze <juliane.schulze@deveritec.com>
Define CANPLL, an AUXPLL IP instance used by the CAN IP. PLL settings
are hardcoded in SoC files, as this PLL should not be configured by the
application. It is meant to always run at 80 MHz.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
