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Commit graph zephyr/dts
Author SHA1 Message Date
Felix Wang
fe4f68504a dts: bindings: pwm: Add pwm-mode property 
Add pwm-mode device tree property to allow configuration of TPM PWM
operation mode. Supports edge-aligned (0) and center-aligned (1) PWM
modes. Defaults to edge-aligned PWM if not specified.

Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
 2026-01-28 16:13:11 +01:00
Peter van der Perk
23e314d187 imx95: Cortex-M7 add FlexCAN controllers 
Adds FlexCAN definitions and 80Mhz clock for correct timing

Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
 2026-01-28 14:42:21 +01:00
Jamie McCrae
b8ab27aa40 dts: Fix incorrect/invalid usage of RAM/NVM nodes for nRF54L* 
Fixes various issues with how these have been used:
- Reserved memory was wrongfully used to describe an RRAM area
  for a CPU
- Reserved memory was wrongfully used to describe an SRAM area
  for a CPU
- A partition described using reserved memory did not have the
  required NVM erase size and write size parameters set for it
- RRAM partitions were not correctly setting ranges properties
- RRAM validation wrongly took the "base flash controller" into
  considering because it was not using unit addresses
- RRAM partitions incorrect set up so that they collided with
  one another for different cores

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
 2026-01-28 10:18:57 +01:00
Henrik Brix Andersen
935373e918 dts: bindings: can: nxp: flexcan: fix clock configuration in examples 
Fix the clock configuration shown in the NXP FlexCAN devicetree binding
examples.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
 2026-01-28 08:33:55 +01:00
Pieter De Gendt
800ec66680 drivers: ethernet: eth_nxp_enet: Support MAC address configuration 
Add support for a MAC address from NVMEM memory.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
 2026-01-28 08:32:37 +01:00
Yasushi SHOJI
cecbbb09d3 dts: bindings: vendor-prefixes: Remove "The" from Zephyr Project 
Drop the leading article from the 'zephyr' vendor name in
vendor-prefixes.txt so vendor names sort more naturally in the Supported
Boards[1] lists.

[1]: https://docs.zephyrproject.org/latest/boards/index.html

Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
 2026-01-28 08:30:22 +01:00
TOKITA Hiroshi
6a53d5c63d tests: lib: devicetree: api: Add map property tests 
Add tests for map property related macros.

Add `native_sim/native/64` to allowed platforms.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
 2026-01-28 08:29:57 +01:00
TOKITA Hiroshi
e1b79aee17 dts: bindings: Add interrupt-nexus and io-channel-nexus base bindings 
Add a base binding for interrupt and io-channel nexus nodes.
This makes the implicit definitions explicit.
Replace existing individual map definitions with this.

This file does not define a specific `compatible` on its own,
So you should include this file before using it practically.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
 2026-01-28 08:29:57 +01:00
TOKITA Hiroshi
3245ee167b dts: bindings: Change *-map-mask and *-map-pass-thru as array type. 
They must be `array` type to match the existing `interrupt-map-mask`
and `interrupt-map-pass-thru`.

And also, updating descriptions.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
 2026-01-28 08:29:57 +01:00
Eran Gal
bcc8d963e1 drivers: i2c_dw: Add SDA_HOLD tx,rx config 
Adds an optional configuration for SDA_HOLD_TX and SDA_HOLD_RX in
the Designware I2C driver.

Signed-off-by: Eran Gal <erang@google.com>
 2026-01-27 15:20:51 -06:00
Benjamin Cabé
ec80c76c34 dts: bindings: sensor: move DTS snippets from description to examples 
Use the new `examples` property to provide example usage in a more
structured way.

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
 2026-01-27 15:18:36 -06:00
Carles Cufi
17af0d8c8c dts: nordic: Fix ngpios in gpio1 for nRF54L15 (and variants) 
This is a follow-up to commit 15716542c2.

See:
https://docs.nordicsemi.com/bundle/ps_nrf54L15/page/chapters/pin.html#ariaid-title6

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
 2026-01-27 15:16:33 -06:00
Bjarki Arge Andreasen
fe971ddeb4 dts: bindings: misc: add model for skyworks sky13348 antenna switch 
Add devicetree model for skyworks sky13348 antenna switch.

Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
 2026-01-27 08:40:15 -05:00
Michal Morsisko
1d5d73252e boards: st: added tsc peripheral to F0 series 
update stm32f0 and stm32f072b_disco for TSC
peripheral

Signed-off-by: Michal Morsisko <morsisko@gmail.com>
 2026-01-27 10:52:13 +00:00
Benjamin Cabé
fe52cf0cae dts: regulator: move DTS snippets from description to examples 
Use the new `examples` property to provide example usage in a more
structured way.

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
 2026-01-27 08:09:26 +01:00
Benjamin Cabé
d2e50b8861 dts: bindings: ethernet: move DTS snippets from description to examples 
Use the new `examples` property to provide example usage in a more
structured way.

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
 2026-01-27 08:09:14 +01:00
Pieter De Gendt
ee05e9e76e dts: arm: nxp: rt10xx: Add OCOTP node 
Add the OCOTP node to rt10xx SoCs.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
 2026-01-27 08:07:53 +01:00
Pieter De Gendt
941f1e6af5 drivers: otp: Add NXP MCUX OCOTP 
Introduce an OTP driver for NXP's MCUX OCOTP.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
 2026-01-27 08:07:53 +01:00
John Batch
58fea2a406 dts: infineon: adding new clk_dst binding for scb, timer, sdhc 
Adds a new clock destination binding to the Infineon scb and tcpwm
peripherals.  This field is used to connect the peripheral to a
peripheral clock.

Signed-off-by: John Batch <john.batch@infineon.com>
 2026-01-27 08:06:28 +01:00
Jacob Schloss
2b1ed4e1e3 dts: arm: st: h7: Add cryp to STM32H750 
Add cryp block to H750.

Signed-off-by: Jacob Schloss <jacob.schloss@suburbanmarine.io>
 2026-01-27 08:06:10 +01:00
Jacob Schloss
d98068116c dts: arm: st: h7: Add hash to STM32H7XX 
Add hash block to all H7xx SoCs that embed such an instance.

Signed-off-by: Jacob Schloss <jacob.schloss@suburbanmarine.io>
 2026-01-27 08:06:10 +01:00
Braeden Lane
5d7fa2621f dts: arm: infineon: Change TCPWM Base Register 
- Change base register for TCPWM to 0x40200000
  which controls the entire IP block.
- Enabling/Disabling counters and handling
  global interrupts.

Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
 2026-01-27 08:05:31 +01:00
Benjamin Cabé
f4163bbe2c dts: bindings: input: move DTS snippets from description to examples 
Use the new `examples` property to provide example usage in a more
structured way.

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
 2026-01-26 14:00:45 -06:00
Benjamin Cabé
879bfd7016 dts: bindings: stepper: move DTS snippets from description to examples 
Use the new `examples` property to provide example usage in a more
structured way.

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
 2026-01-26 14:00:19 -06:00
Benjamin Cabé
d619cc9b74 dts: bindings: mtd: move DTS snippets from description to examples 
Use the new `examples` property to provide example usage in a more
structured way.

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
 2026-01-26 13:59:44 -06:00
Enzo Vanhauwaert
6a5091cde0 nxp: mimxrt595_evk: enable USBD support 
Enable use of USB Next stack and UDC driver for mimxrt595_evk (imxrt5xx)

Signed-off-by: Enzo Vanhauwaert <enzo.vanhauwaert@hotmail.com>
 2026-01-26 13:56:44 -06:00
Appana Durga Kedareswara rao
7acd5813e9 soc: amd: Add initial support for Versal SoC APU 
Add initial support for the Versal SoC APU, which is based on
the Arm Cortex-A72 processor. It includes basic wiring for memory
regions, UART, interrupt controller, and timer.

This commit introduces the SoC definition and MMU configuration
required for APU-based development on the Versal platform.

Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
 2026-01-26 13:56:19 -06:00
Eric Ackermann
65d6752963 drivers: ethernet: Add Xilinx Axi Ethernet Lite 
This commit adds support for the Xilinx AXI Ethernet Lite device,
also known as the emaclite.
The emaclite is a light-weight 10/100 MII Ethernet device.
It foregoes a DMA to reduce chip area.
Instead, it uses memory-mapped transmit/receive buffers.
A selection of features can optionally be enabled:
- a second ("pong") RX/TX Buffer
- MDIO support
- Interrupt support
This driver handles the MAC functionality of the core;
a driver for the MDIO part is introduced separately
as an MDIO driver.

Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
 2026-01-26 13:54:32 -06:00
Eric Ackermann
bb8d46e9b7 drivers: mdio: Add Xilinx Axi Ethernet Lite driver 
This commit adds support for the Xilinx AXI Ethernet Lite device,
also known as the emaclite.
The emaclite is a light-weight 10/100 MII Ethernet device.
It can optionally be configured to include an MDIO.
The MMIO interface is controlled via MMIO registers and requires
the software to busy-wait until completion.

Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
 2026-01-26 13:54:32 -06:00
Hubert Miś
0f6bcc6491 drivers: led: sct2024 controller 
Initial implementation of SCT2024 LED controller driver

Signed-off-by: Hubert Miś <hubert.mis@gmail.com>
 2026-01-26 10:09:43 -06:00
Jérôme Pouiller
e6302b1b74 drivers: rng: siwx91x: Avoid direct access to the clock 
Currently, silabs,siwx91x-rng directly write clock hardware block. Change
that to properly rely on clock driver.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
 2026-01-26 14:16:31 +01:00
Afonso Oliveira
39b0d2b0b6 dts: bindings: riscv: add IMSIC binding 
Add devicetree binding for the RISC-V IMSIC (Incoming Message-Signaled
Interrupt Controller).

Signed-off-by: Afonso Oliveira <afonsoo@synopsys.com>
 2026-01-26 14:16:22 +01:00
Fin Maaß
8cc8239efa riscv: require riscv,isa-base and riscv,isa-extensions 
require `riscv,isa-base` and `riscv,isa-extensions` dt props
to be set.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2026-01-26 14:15:18 +01:00
Fin Maaß
204029f12c riscv: deprecate riscv,isa dt prop 
deprecate riscv,isa dt prop

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2026-01-26 14:15:18 +01:00
Fin Maaß
869845d6ab aesc: riscv: use riscv,isa-extensions dt prop 
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2026-01-26 14:15:18 +01:00
Fin Maaß
ed6a969849 andestech: riscv: use riscv,isa-extensions dt prop 
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2026-01-26 14:15:18 +01:00
Fin Maaß
01bc8b2351 egis: riscv: use riscv,isa-extensions dt prop 
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2026-01-26 14:15:18 +01:00
Fin Maaß
8f69f66059 gd: riscv: use riscv,isa-extensions dt prop 
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2026-01-26 14:15:18 +01:00
Fin Maaß
fb1aeeb346 intel: niosv: riscv: use riscv,isa-extensions dt prop 
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2026-01-26 14:15:18 +01:00
Fin Maaß
5b0a847098 ite: riscv: use riscv,isa-extensions dt prop 
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2026-01-26 14:15:18 +01:00
Fin Maaß
74e5e8fc13 lowriscv: riscv: use riscv,isa-extensions dt prop 
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2026-01-26 14:15:18 +01:00
Fin Maaß
1773d0538d microchip: riscv: use riscv,isa-extensions dt prop 
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2026-01-26 14:15:18 +01:00
Fin Maaß
bbb216584e openhwgroup: riscv: use riscv,isa-extensions dt prop 
use riscv,isa-extensions dt prop for riscv cpus.

also combines both SOC_CV64A6 variants

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2026-01-26 14:15:18 +01:00
Fin Maaß
6733437c95 openisa: riscv: use riscv,isa-extensions dt prop 
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2026-01-26 14:15:18 +01:00
Fin Maaß
9b570e90f2 raspberrypi: riscv: use riscv,isa-extensions dt prop 
use riscv,isa-extensions dt prop for
raspberrypi riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2026-01-26 14:15:18 +01:00
Fin Maaß
1c72c78d5f sensry: riscv: use riscv,isa-extensions dt prop 
use riscv,isa-extensions dt prop for
sensry riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2026-01-26 14:15:18 +01:00
Fin Maaß
30ff2d3cae bflb: riscv: use riscv,isa-extensions dt prop 
use riscv,isa-extensions dt prop for
bflb riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2026-01-26 14:15:18 +01:00
Fin Maaß
783ebd98bc sifive: riscv: use riscv,isa-extensions dt prop 
use riscv,isa-extensions dt prop for
sifive riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2026-01-26 14:15:18 +01:00
Fin Maaß
be7285c086 starfive: riscv: use riscv,isa-extensions dt prop 
use riscv,isa-extensions dt prop for
starfive riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2026-01-26 14:15:18 +01:00
Fin Maaß
72bd920bfa telink: riscv: use riscv,isa-extensions dt prop 
use riscv,isa-extensions dt prop for
telink riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2026-01-26 14:15:18 +01:00