drivers: Add MAX32690 uart driver
UART driver for MAX32690 Co-authored-by: Okan Sahin <okan.sahin@analog.com> Co-authored-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com> Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
This commit is contained in:
Sadik Ozer
Henrik Brix Andersen
parent
c121f405fe
commit
0480b2625b
5 changed files with 508 additions and 0 deletions
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@ -69,6 +69,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_EMUL uart_emul.c)
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zephyr_library_sources_ifdef(CONFIG_UART_NUMAKER uart_numaker.c)
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zephyr_library_sources_ifdef(CONFIG_UART_EFINIX_SAPPIHIRE uart_efinix_sapphire.c)
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zephyr_library_sources_ifdef(CONFIG_UART_SEDI uart_sedi.c)
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zephyr_library_sources_ifdef(CONFIG_UART_MAX32 uart_max32.c)
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zephyr_library_sources_ifdef(CONFIG_UART_BCM2711_MU uart_bcm2711.c)
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zephyr_library_sources_ifdef(CONFIG_UART_INTEL_LW uart_intel_lw.c)
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zephyr_library_sources_ifdef(CONFIG_UART_RENESAS_RA uart_renesas_ra.c)
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@ -266,6 +266,8 @@ source "drivers/serial/Kconfig.efinix_sapphire"
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source "drivers/serial/Kconfig.sedi"
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source "drivers/serial/Kconfig.max32"
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source "drivers/serial/Kconfig.bcm2711"
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source "drivers/serial/Kconfig.intel_lw"
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16
drivers/serial/Kconfig.max32
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16
drivers/serial/Kconfig.max32
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@ -0,0 +1,16 @@
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# MAX32 UART configuration
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# Copyright (c) 2023-2024 Analog Devices, Inc.
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# SPDX-License-Identifier: Apache-2.0
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config UART_MAX32
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bool "MAX32 MCU serial driver"
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default y
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depends on DT_HAS_ADI_MAX32_UART_ENABLED
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select SERIAL_HAS_DRIVER
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select SERIAL_SUPPORT_INTERRUPT
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select PINCTRL
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help
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This option enables the UART driver for MAX32 family of
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processors.
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Say y if you wish to use serial port on MAX32 MCU.
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453
drivers/serial/uart_max32.c
Normal file
453
drivers/serial/uart_max32.c
Normal file
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@ -0,0 +1,453 @@
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/*
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* Copyright (c) 2023-2024 Analog Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/uart.h>
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#include <zephyr/kernel.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/drivers/clock_control/adi_max32_clock_control.h>
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#include <wrap_max32_uart.h>
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#define DT_DRV_COMPAT adi_max32_uart
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LOG_MODULE_REGISTER(uart_max32, CONFIG_UART_LOG_LEVEL);
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struct max32_uart_config {
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mxc_uart_regs_t *regs;
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const struct pinctrl_dev_config *pctrl;
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const struct device *clock;
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struct max32_perclk perclk;
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struct uart_config uart_conf;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_config_func_t irq_config_func;
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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struct max32_uart_data {
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_callback_user_data_t cb; /* Interrupt callback */
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void *cb_data; /* Interrupt callback arg */
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uint32_t flags; /* Cached interrupt flags */
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uint32_t status; /* Cached status flags */
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#endif
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struct uart_config conf; /* baudrate, stopbits, ... */
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};
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static void uart_max32_isr(const struct device *dev);
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#endif
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static void api_poll_out(const struct device *dev, unsigned char c)
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{
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const struct max32_uart_config *cfg = dev->config;
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MXC_UART_WriteCharacter(cfg->regs, c);
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}
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static int api_poll_in(const struct device *dev, unsigned char *c)
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{
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int val;
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const struct max32_uart_config *cfg = dev->config;
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val = MXC_UART_ReadCharacterRaw(cfg->regs);
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if (val >= 0) {
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*c = (unsigned char)val;
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} else {
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return -1;
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}
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return 0;
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}
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static int api_err_check(const struct device *dev)
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{
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int err = 0;
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uint32_t flags;
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const struct max32_uart_config *cfg = dev->config;
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flags = MXC_UART_GetFlags(cfg->regs);
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if (flags & ADI_MAX32_UART_ERROR_FRAMING) {
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err |= UART_ERROR_FRAMING;
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}
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if (flags & ADI_MAX32_UART_ERROR_PARITY) {
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err |= UART_ERROR_PARITY;
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}
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if (flags & ADI_MAX32_UART_ERROR_OVERRUN) {
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err |= UART_ERROR_OVERRUN;
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}
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return err;
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}
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#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
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static int api_configure(const struct device *dev, const struct uart_config *uart_cfg)
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{
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int err;
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const struct max32_uart_config *const cfg = dev->config;
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mxc_uart_regs_t *regs = cfg->regs;
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struct max32_uart_data *data = dev->data;
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/*
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* Set parity
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*/
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if (data->conf.parity != uart_cfg->parity) {
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mxc_uart_parity_t mxc_parity;
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switch (uart_cfg->parity) {
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case UART_CFG_PARITY_NONE:
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mxc_parity = ADI_MAX32_UART_CFG_PARITY_NONE;
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break;
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case UART_CFG_PARITY_ODD:
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mxc_parity = ADI_MAX32_UART_CFG_PARITY_ODD;
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break;
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case UART_CFG_PARITY_EVEN:
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mxc_parity = ADI_MAX32_UART_CFG_PARITY_EVEN;
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break;
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case UART_CFG_PARITY_MARK:
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#if defined(ADI_MAX32_UART_CFG_PARITY_MARK)
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mxc_parity = ADI_MAX32_UART_CFG_PARITY_MARK;
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break;
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#else
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return -ENOTSUP;
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#endif
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case UART_CFG_PARITY_SPACE:
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#if defined(ADI_MAX32_UART_CFG_PARITY_SPACE)
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mxc_parity = ADI_MAX32_UART_CFG_PARITY_SPACE;
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break;
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#else
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return -ENOTSUP;
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#endif
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default:
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return -EINVAL;
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}
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err = MXC_UART_SetParity(regs, mxc_parity);
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if (err < 0) {
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return -ENOTSUP;
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}
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/* incase of success keep configuration */
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data->conf.parity = uart_cfg->parity;
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}
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/*
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* Set stop bit
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*/
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if (data->conf.stop_bits != uart_cfg->stop_bits) {
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if (uart_cfg->stop_bits == UART_CFG_STOP_BITS_1) {
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err = MXC_UART_SetStopBits(regs, MXC_UART_STOP_1);
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} else if (uart_cfg->stop_bits == UART_CFG_STOP_BITS_2) {
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err = MXC_UART_SetStopBits(regs, MXC_UART_STOP_2);
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} else {
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return -ENOTSUP;
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}
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if (err < 0) {
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return -ENOTSUP;
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}
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/* incase of success keep configuration */
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data->conf.stop_bits = uart_cfg->stop_bits;
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}
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/*
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* Set data bit
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* Valid data for MAX32 is 5-6-7-8
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* Valid data for Zepyhr is 0-1-2-3
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* Added +5 to index match.
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*/
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if (data->conf.data_bits != uart_cfg->data_bits) {
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err = MXC_UART_SetDataSize(regs, (5 + uart_cfg->data_bits));
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if (err < 0) {
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return -ENOTSUP;
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}
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/* incase of success keep configuration */
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data->conf.data_bits = uart_cfg->data_bits;
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}
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/*
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* Set flow control
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* Flow control not implemented yet so that only support no flow mode
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*/
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if (data->conf.flow_ctrl != uart_cfg->flow_ctrl) {
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if (uart_cfg->flow_ctrl != UART_CFG_FLOW_CTRL_NONE) {
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return -ENOTSUP;
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}
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data->conf.flow_ctrl = uart_cfg->flow_ctrl;
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}
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/*
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* Set baudrate
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*/
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if (data->conf.baudrate != uart_cfg->baudrate) {
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err = Wrap_MXC_UART_SetFrequency(regs, uart_cfg->baudrate, cfg->perclk.clk_src);
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if (err < 0) {
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return -ENOTSUP;
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}
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/* In case of success keep configuration */
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data->conf.baudrate = uart_cfg->baudrate;
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}
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return 0;
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}
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static int api_config_get(const struct device *dev, struct uart_config *uart_cfg)
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{
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struct max32_uart_data *data = dev->data;
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/* copy configs from global setting */
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*uart_cfg = data->conf;
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return 0;
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}
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#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
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static int uart_max32_init(const struct device *dev)
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{
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int ret;
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const struct max32_uart_config *const cfg = dev->config;
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mxc_uart_regs_t *regs = cfg->regs;
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if (!device_is_ready(cfg->clock)) {
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LOG_ERR("Clock control device not ready");
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return -ENODEV;
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}
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ret = MXC_UART_Shutdown(regs);
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if (ret) {
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return ret;
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}
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ret = clock_control_on(cfg->clock, (clock_control_subsys_t)&cfg->perclk);
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if (ret != 0) {
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LOG_ERR("Cannot enable UART clock");
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return ret;
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}
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ret = pinctrl_apply_state(cfg->pctrl, PINCTRL_STATE_DEFAULT);
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if (ret) {
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return ret;
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}
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ret = api_configure(dev, &cfg->uart_conf);
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if (ret) {
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return ret;
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}
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ret = Wrap_MXC_UART_Init(regs);
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if (ret) {
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return ret;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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/* Clear any pending UART RX/TX interrupts */
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MXC_UART_ClearFlags(regs, (ADI_MAX32_UART_INT_RX | ADI_MAX32_UART_INT_TX));
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cfg->irq_config_func(dev);
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#endif
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return ret;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static int api_fifo_fill(const struct device *dev, const uint8_t *tx_data, int size)
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{
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unsigned int num_tx = 0;
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const struct max32_uart_config *cfg = dev->config;
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num_tx = MXC_UART_WriteTXFIFO(cfg->regs, (unsigned char *)tx_data, size);
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return (int)num_tx;
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}
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static int api_fifo_read(const struct device *dev, uint8_t *rx_data, const int size)
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{
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unsigned int num_rx = 0;
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const struct max32_uart_config *cfg = dev->config;
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num_rx = MXC_UART_ReadRXFIFO(cfg->regs, (unsigned char *)rx_data, size);
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if (num_rx == 0) {
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MXC_UART_ClearFlags(cfg->regs, ADI_MAX32_UART_INT_RX);
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}
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return num_rx;
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}
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static void api_irq_tx_enable(const struct device *dev)
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{
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const struct max32_uart_config *cfg = dev->config;
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unsigned int key;
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MXC_UART_EnableInt(cfg->regs, ADI_MAX32_UART_INT_TX | ADI_MAX32_UART_INT_TX_OEM);
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key = irq_lock();
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uart_max32_isr(dev);
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irq_unlock(key);
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}
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static void api_irq_tx_disable(const struct device *dev)
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{
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const struct max32_uart_config *cfg = dev->config;
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MXC_UART_DisableInt(cfg->regs, ADI_MAX32_UART_INT_TX | ADI_MAX32_UART_INT_TX_OEM);
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}
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static int api_irq_tx_ready(const struct device *dev)
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{
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struct max32_uart_data *const data = dev->data;
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return ((data->flags & (ADI_MAX32_UART_INT_TX | ADI_MAX32_UART_INT_TX_OEM)) ||
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!(data->status & MXC_F_UART_STATUS_TX_FULL));
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}
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static void api_irq_rx_enable(const struct device *dev)
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{
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const struct max32_uart_config *cfg = dev->config;
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MXC_UART_EnableInt(cfg->regs, ADI_MAX32_UART_INT_RX);
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}
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static void api_irq_rx_disable(const struct device *dev)
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{
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const struct max32_uart_config *cfg = dev->config;
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MXC_UART_DisableInt(cfg->regs, ADI_MAX32_UART_INT_RX);
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}
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static int api_irq_tx_complete(const struct device *dev)
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{
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const struct max32_uart_config *cfg = dev->config;
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if (MXC_UART_GetActive(cfg->regs) == E_BUSY) {
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return 0;
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} else {
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return 1; /* transmission completed */
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}
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}
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static int api_irq_rx_ready(const struct device *dev)
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{
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struct max32_uart_data *const data = dev->data;
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return (data->flags & ADI_MAX32_UART_INT_RX);
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}
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static void api_irq_err_enable(const struct device *dev)
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{
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const struct max32_uart_config *cfg = dev->config;
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MXC_UART_EnableInt(cfg->regs, ADI_MAX32_UART_ERROR_INTERRUPTS);
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}
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static void api_irq_err_disable(const struct device *dev)
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{
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const struct max32_uart_config *cfg = dev->config;
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MXC_UART_DisableInt(cfg->regs, ADI_MAX32_UART_ERROR_INTERRUPTS);
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}
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static int api_irq_is_pending(const struct device *dev)
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{
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struct max32_uart_data *const data = dev->data;
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return (data->flags & (ADI_MAX32_UART_INT_RX | ADI_MAX32_UART_INT_TX));
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}
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static int api_irq_update(const struct device *dev)
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{
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struct max32_uart_data *const data = dev->data;
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const struct max32_uart_config *const cfg = dev->config;
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data->flags = MXC_UART_GetFlags(cfg->regs);
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data->status = MXC_UART_GetStatus(cfg->regs);
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MXC_UART_ClearFlags(cfg->regs, data->flags);
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return 1;
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}
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static void api_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb,
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void *cb_data)
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{
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struct max32_uart_data *const data = dev->data;
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data->cb = cb;
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data->cb_data = cb_data;
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}
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static void uart_max32_isr(const struct device *dev)
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{
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struct max32_uart_data *data = dev->data;
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if (data->cb) {
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data->cb(dev, data->cb_data);
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}
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}
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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static const struct uart_driver_api uart_max32_driver_api = {
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.poll_in = api_poll_in,
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.poll_out = api_poll_out,
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.err_check = api_err_check,
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#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
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.configure = api_configure,
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.config_get = api_config_get,
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#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.fifo_fill = api_fifo_fill,
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.fifo_read = api_fifo_read,
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.irq_tx_enable = api_irq_tx_enable,
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.irq_tx_disable = api_irq_tx_disable,
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.irq_tx_ready = api_irq_tx_ready,
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.irq_rx_enable = api_irq_rx_enable,
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.irq_rx_disable = api_irq_rx_disable,
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.irq_tx_complete = api_irq_tx_complete,
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.irq_rx_ready = api_irq_rx_ready,
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.irq_err_enable = api_irq_err_enable,
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.irq_err_disable = api_irq_err_disable,
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.irq_is_pending = api_irq_is_pending,
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.irq_update = api_irq_update,
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.irq_callback_set = api_irq_callback_set,
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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#define MAX32_UART_INIT(_num) \
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PINCTRL_DT_INST_DEFINE(_num); \
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IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, \
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(static void uart_max32_irq_init_##_num(const struct device *dev) \
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{ \
|
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IF_ENABLED( \
|
||||
CONFIG_UART_INTERRUPT_DRIVEN, \
|
||||
(IRQ_CONNECT(DT_INST_IRQN(_num), DT_INST_IRQ(_num, priority), \
|
||||
uart_max32_isr, DEVICE_DT_INST_GET(_num), 0); \
|
||||
irq_enable(DT_INST_IRQN(_num)))); \
|
||||
})); \
|
||||
static const struct max32_uart_config max32_uart_config_##_num = { \
|
||||
.regs = (mxc_uart_regs_t *)DT_INST_REG_ADDR(_num), \
|
||||
.pctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(_num), \
|
||||
.clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(_num)), \
|
||||
.perclk.bus = DT_INST_CLOCKS_CELL(_num, offset), \
|
||||
.perclk.bit = DT_INST_CLOCKS_CELL(_num, bit), \
|
||||
.perclk.clk_src = \
|
||||
DT_INST_PROP_OR(_num, clock_source, ADI_MAX32_PRPH_CLK_SRC_PCLK), \
|
||||
.uart_conf.baudrate = DT_INST_PROP(_num, current_speed), \
|
||||
.uart_conf.parity = DT_INST_ENUM_IDX_OR(_num, parity, UART_CFG_PARITY_NONE), \
|
||||
.uart_conf.data_bits = DT_INST_ENUM_IDX(_num, data_bits), \
|
||||
.uart_conf.stop_bits = DT_INST_ENUM_IDX_OR(_num, stop_bits, UART_CFG_STOP_BITS_1), \
|
||||
.uart_conf.flow_ctrl = \
|
||||
DT_INST_PROP_OR(_num, hw_flow_control, UART_CFG_FLOW_CTRL_NONE), \
|
||||
IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, \
|
||||
(.irq_config_func = uart_max32_irq_init_##_num,))}; \
|
||||
static struct max32_uart_data max32_uart_data##_num = { \
|
||||
IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, (.cb = NULL,))}; \
|
||||
DEVICE_DT_INST_DEFINE(_num, uart_max32_init, NULL, &max32_uart_data##_num, \
|
||||
&max32_uart_config_##_num, PRE_KERNEL_1, \
|
||||
CONFIG_SERIAL_INIT_PRIORITY, (void *)&uart_max32_driver_api);
|
||||
|
||||
DT_INST_FOREACH_STATUS_OKAY(MAX32_UART_INIT)
|
||||
36
dts/bindings/serial/adi,max32-uart.yaml
Normal file
36
dts/bindings/serial/adi,max32-uart.yaml
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
# Copyright (c) 2023-2024 Analog Devices, Inc.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: MAX32 UART
|
||||
|
||||
include: [uart-controller.yaml, pinctrl-device.yaml]
|
||||
|
||||
compatible: "adi,max32-uart"
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
clocks:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
pinctrl:
|
||||
type: phandles
|
||||
|
||||
clock-source:
|
||||
type: int
|
||||
enum: [0, 1, 2, 3, 4, 5]
|
||||
description: |
|
||||
Clock source to be used by the UART peripheral. The following options
|
||||
are available:
|
||||
- 0: "ADI_MAX32_PRPH_CLK_SRC_PCLK" Peripheral clock
|
||||
- 1: "ADI_MAX32_PRPH_CLK_SRC_EXTCLK" External Clock
|
||||
- 2: "ADI_MAX32_PRPH_CLK_SRC_IBRO" Internal Baud Rate Oscillator
|
||||
- 3: "ADI_MAX32_PRPH_CLK_SRC_ERFO" External Radio Frequency Oscillator
|
||||
- 4: "ADI_MAX32_PRPH_CLK_SRC_ERTCO" External Real-Time Clock Oscillator
|
||||
- 5: "ADI_MAX32_PRPH_CLK_SRC_INRO" Internal Ring Oscillator
|
||||
The target device might not support all option please take a look on
|
||||
target device user guide
|
||||
Loading…
Add table
Add a link
Reference in a new issue