This patch adds a new driver for the ADXL355 three-axis digital
accelerometer, implementing configuration, sampling,
and full-scale range controls according to the
ADXL355 datasheet (Analog Devices).
Features:
- I2C and SPI register access
- Sampling frequency (ODR) configuration
- Full-scale range selection (±2g/±4g/±8g)
- Standby/measure power modes
- Optional FIFO streaming support via RTIO
- Basic trigger and interrupt handling
Power management is supported via PM_DEVICE callbacks
to place the sensor in standby mode when suspended
and resume continuous measurement on resume.
References:
- ADXL354/ADXL355 Datasheet (Analog Devices)
https://www.analog.com/media/en/technical-documentation/data-sheets/adxl354_adxl355.pdf
Signed-off-by: Francis Roi Manabat <francisroi.manabat@analog.com>
Use a code spell-checking tool to detect and fix spelling errors in
`.yaml` files under `dts/bindings`.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Use the new and appropriate "st,stm32h5-pinctrl" compatible for the pinctrl
in DTSI for STM32H5 series.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Add a new binding for the pinctrl controller of STM32H5 series.
The specificity of this series is that the "High-Speed Low-Voltage" (HSLV)
feature is configured per pin. This feature allows to increase the maximum
speed of the IO pins at low voltage.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Introduce DT_FOREACH_REG and DT_INST_FOREACH_REG macros to enable
iteration over reg entries in devicetree nodes by invoking a user-
supplied macro per entry. Add support for macros accepting a
separator and variadic arguments with the new DT_FOREACH_REG_SEP,
DT_FOREACH_REG_VARGS, and DT_FOREACH_REG_SEP_VARGS macros, as well
as their DT_INST_ variants.
The DT_FOREACH_REG macro mirrors the behavior of the ranges property.
Update the devicetree macro generation logic in gen_defines.py to
emit the new macro variants. Document the additions by expanding the
Augmented Backus-Naur Form grammar in macros.bnf. Add detailed
comments with usage examples and parameter details for all new macros.
Expand test coverage with new overlay nodes and dedicated tests to
verify macro correctness and behavior, across various node scenarios
including multi-register, single-register, and nodes lacking reg
properties.
Signed-off-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
Signed-off-by: Svitlana Drozd <svitlana_drozd@epam.com>
This adds the soc files for the Synaptics SR100 SoC.
Signed-off-by: Łukasz Kędziora <lkedziora@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Andreas Weissel <andreas.weissel@synaptics.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This adds the pinctrl driver for Synaptics SR100-series SoCs.
Signed-off-by: Łukasz Kędziora <lkedziora@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Andreas Weissel <andreas.weissel@synaptics.com>
This adds the clock control driver for Synaptics SR100-series SoCs.
Signed-off-by: Łukasz Kędziora <lkedziora@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Andreas Weissel <andreas.weissel@synaptics.com>
Rename stm32h5e/h5f SRAMs node labels in the SoC DTSI files to better
match the SRAMs names in the literature.
Update stm32h5f5j_dk board accordingly.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Restore the UART9 node on the stm32h5e/f series.
The instance exists like on other stm32h5 devices.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
For all STM32 ADC instances that support the injected channel feature, add
the newly created property to indicate that.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add a property to the STM32 ADC bindings to indicate whether the ADC
instance supports the injected channel feature.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This adds support for Cadence SweRV S420 SoC which is similar
to S400 but with support for 2 threads.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The SweRV naming is under Cadence now so rename to have
a proper vendor prefix, and removes the EH1 naming as
this can be used for multiple family of SoCs.
The old compatible "swerv,pic" can still be used but
cannot be used together with "cdns,swerv-pic".
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add keyscan driver support for Realtek Bee series SoCs,
including RTL87x2G and RTL8752H.
This driver supports:
- Maximum 12 * 20 matrix keyboard scanning
- Ghost key detecting
- Manual/Auto scanning mode configuration
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Previously, nv-flash nodes were used as the flash controller and
contained APIs. But currently, to support mapped-partitions
and allow MCUboot to run on RA8x2 devices, this MRAM driver need
to correct the node that used for flash controller.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
- Define the HCI node in the SoC series' dtsi.
- Adjust main thread stack sizes and buffer counts required for
Bluetooth operation.
- Enable meta-irq to configure the bee-bt-controller thread as a
meta-irq thread.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Generalize the Hynitron CST816S touchscreen driver to support the
broader CST8xx controller family.
Changes include:
- Renaming the driver from input_cst816s.c to input_cst8xx.c
- Renaming drivers/input/Kconfig.cst816s to drivers/input/Kconfig.cst8xx
- Updating the Devicetree compatible from hynitron,cst816s to
hynitron,cst8xx
- Updating the Devicetree binding description and compatible field
- Updating board DTS files and test overlays to use the new compatible
These changes align the driver, Devicetree bindings, and compatible
strings with the actual hardware support, which covers the CST8xx
family rather than only the CST816S variant.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Use a gpio-nexus for the MAIN domain GPIO instances 0 and 1. This is needed
to allow accessing all pins instead of being limited to the first 32. For
the MCU domain instance 0 this isn't necessary since only 22 pins are
mapped out of the SoC.
Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
This patch adds support for the OpenRISC 1000 (or1k) architecture: a
MIPS-like open hardware ISA which was first introduced in 2000.
The thread switching implementation uses the modern Zephyr thread "switch"
architecture.
Signed-off-by: Joel Holdsworth <jholdsworth@nvidia.com>
Introduces DRP support to the USB-C subsystem, enabling dynamic
support for both Source and Sink power roles. Unattached devices
toggle between Source (Rp) and Sink (Rd) CC advertisements based
on the configured DRP period (tDRP) and duty cycle (dcSRC.DRP).
Once an attach is detected, the device enters the appropriate
Attached.SRC or Attached.SNK usbc_tc state and starts the
corresponding usbc_pe state machine to negotiate a power contract.
Signed-off-by: Nicholas Cadieux <ncadieux@qti.qualcomm.com>
Add zephyr,usb-c-pwrctrl binding to properly describe USB-C power
control hardware instead of using gpio-leds and pwm-leds bindings.
Also update the usb_c source sample to use the new binding.
Signed-off-by: Nicholas Cadieux <ncadieux@qti.qualcomm.com>
HX711 pulls DOUT low when data is ready. This commit enabled pin config
to switch from SPI to GPIO and set up GPIIO interrupts for the falling
edge.
The implementation is similar to the `infineon,airoc-wifi` driver, by
using pinctrl.
Signed-off-by: Terry Geng <terry@terriex.com>
HX711 is a specialized 24-bit ADC for load cell and strain gauge sensors.
It uses a two-wire (PD_SCK and DOUT) serial protocol that
- first 24 clock cycles reads out the sample
- last 1 to 3 clock cycles set the PGA gain for the next sample
The requirement of control the exact number of clock cycles makes the
SCK for SPI unsuitable for clocking HX711. Instead, in this commit, the
clock is implemented as a series of 0xAA on the MOSI.
Signed-off-by: Terry Geng <terry@terriex.com>
Fix a few typos and formatting issues in the DTS example of this binding to
be more in line with the project's DTS coding style.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Extend the STM32 VREFBUF regulator driver to support STM32WB devices.
Update the st,stm32-vrefbuf devicetree binding and add the VREFBUF
node to the STM32WB SoC dtsi so that applications can enable the
internal reference buffer on STM32WB.
Signed-off-by: Lubos Koudelka <lubos.koudelka@st.com>
Change stm32n6xx SoCs DTSI files to ease how a board can use the
secure or non-secure IOMEM and internal SRAMs address ranges depending
on whether the Zephyr application runs in secure or non-secure
world. This relies on use of the ranges DT property.
By default, the existing stm32n6xx SoC DTSI files define the secure
address mapping as prior this change, hence no functional changes.
Boards/platforms embedding a stm32n657X0 compliant SoC and expecting
to run in non-secure world can apply use the standard SoC DTSI file
and apply last stm32n657X0_ns.dtsi overlay file to select the non-secure
mapping address ranges.
For this purpose, use ranges DT properties and a node level for
peripherals and SRAMs:
- Insert axisram12@24000000 node level for the AXI SRAM1 and SRAM2 nodes
with a ranges property to define the address range of these
internal RAMS.
- Add a ranges property in ramcfg@* nodes to define the address ranges
for the AXI SRAMs they each define.
- Insert peripherals@40000000 node level with a ranges property for the
peripherals in soc node and its subnode to define the address ranges
applied.
Update stm32n6x ram_check.ld linker script to consider address ranges
instead of the reg property raw value.
Update the HAL reference that bring pinctrl DTSI files that must be
consistent with the SoC DTSI files regarding pinctrl node path change.
Sync on a MCUboot repo change to consider ranges in stm32n6 memory DT
node properties.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Implement a MAX32 mbox driver with the semaphore peripheral.
Tweak the mbox test to allow testing with only one TX/RX channel pair
available.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
