boards: nordic: ipc: added dcache alignement
The nRF54 and nRF92 chips has data cache, which means the ICMsg and ICBMsg must be configured to follow required cache alignment of the shared memory. The `dcache-alignement` needs to be defined for that. Signed-off-by: Dominik Kilian <Dominik.Kilian@nordicsemi.no>
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10 changed files with 29 additions and 3 deletions
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@ -24,6 +24,7 @@
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cpuapp_cpurad_ipc: ipc-2-3 {
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compatible = "zephyr,ipc-icbmsg";
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dcache-alignment = <32>;
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status = "disabled";
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mboxes = <&cpuapp_bellboard 18>,
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<&cpurad_bellboard 12>;
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@ -24,6 +24,7 @@
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cpuapp_cpurad_ipc: ipc-2-3 {
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compatible = "zephyr,ipc-icbmsg";
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dcache-alignment = <32>;
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status = "disabled";
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mboxes = <&cpuapp_bellboard 18>,
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<&cpurad_bellboard 12>;
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@ -40,12 +40,21 @@ Configuration
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The backend is configured using Kconfig and devicetree.
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When configuring the backend, do the following:
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* If at least one of the cores uses data cache on shared memory, set the ``dcache-alignment`` value.
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This must be the largest value of the invalidation or the write-back size for both sides of the communication.
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You can skip it if none of the communication sides is using data cache on shared memory.
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* Define two memory regions and assign them to ``tx-region`` and ``rx-region`` of an instance.
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Ensure that the memory regions used for data exchange are unique (not overlapping any other region) and accessible by both domains (or CPUs).
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* Define the number of allocable blocks for each region with ``tx-blocks`` and ``rx-blocks``.
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* Define MBOX devices for sending a signal that informs the other domain (or CPU) of the written data.
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Ensure that the other domain (or CPU) can receive the signal.
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.. caution::
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Make sure that you set correct value of the ``dcache-alignment``.
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At first, wrong value may not show any signs, which may give a false impression that everything works.
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Unstable behavior will appear sooner or later.
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See the following configuration example for one of the instances:
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.. code-block:: devicetree
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@ -63,6 +72,7 @@ See the following configuration example for one of the instances:
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ipc {
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ipc0: ipc0 {
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compatible = "zephyr,ipc-icbmsg";
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dcache-alignment = <32>;
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tx-region = <&tx>;
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rx-region = <&rx>;
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tx-blocks = <16>;
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@ -24,6 +24,9 @@ Configuration
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The backend is configured via Kconfig and devicetree.
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When configuring the backend, do the following:
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* If at least one of the cores uses data cache on shared memory, set the ``dcache-alignment`` value.
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This must be the largest value of the invalidation or the write-back size for both sides of the communication.
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You can skip it if none of the communication sides is using data cache on shared memory.
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* Define two memory regions and assign them to ``tx-region`` and ``rx-region``
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of an instance. Ensure that the memory regions used for data exchange are
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unique (not overlapping any other region) and accessible by both domains
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@ -32,6 +35,12 @@ When configuring the backend, do the following:
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domain (or CPU) that data has been written. Ensure that the other domain
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(or CPU) is able to receive the signal.
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.. caution::
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Make sure that you set correct value of the ``dcache-alignment``.
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At first, wrong value may not show any signs, which may give a false impression that everything works.
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Unstable behavior will appear sooner or later.
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See the following configuration example for one of the instances:
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.. code-block:: devicetree
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@ -49,6 +58,7 @@ See the following configuration example for one of the instances:
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ipc {
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ipc0: ipc0 {
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compatible = "zephyr,ipc-icmsg";
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dcache-alignment = <32>;
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tx-region = <&tx>;
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rx-region = <&rx>;
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mboxes = <&mbox 0>, <&mbox 1>;
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@ -32,7 +32,7 @@ properties:
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For example:
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Side A: no data cache
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Side B: 32 Bytes write-back size, 16 Bytes invalidation size
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dcache-alignment = 32; for both
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dcache-alignment = <32>; for both
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mboxes:
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description: phandle to the MBOX controller (TX and RX are required)
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@ -23,6 +23,7 @@
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ipc {
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ipc0: ipc0 {
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compatible = "zephyr,ipc-icmsg";
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dcache-alignment = <32>;
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tx-region = <&sram_tx>;
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rx-region = <&sram_rx>;
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mboxes = <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_tx 21>;
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@ -23,6 +23,7 @@
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ipc {
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ipc0: ipc0 {
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compatible = "zephyr,ipc-icbmsg";
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dcache-alignment = <32>;
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tx-region = <&sram_tx>;
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rx-region = <&sram_rx>;
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tx-blocks = <16>;
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@ -23,6 +23,7 @@
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ipc {
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ipc0: ipc0 {
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compatible = "zephyr,ipc-icmsg";
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dcache-alignment = <32>;
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tx-region = <&sram_tx>;
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rx-region = <&sram_rx>;
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mboxes = <&cpuflpr_vevif_rx 21>, <&cpuflpr_vevif_tx 20>;
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@ -23,6 +23,7 @@
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ipc {
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ipc0: ipc0 {
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compatible = "zephyr,ipc-icbmsg";
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dcache-alignment = <32>;
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tx-region = <&sram_tx>;
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rx-region = <&sram_rx>;
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tx-blocks = <18>;
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@ -1434,11 +1434,11 @@ const static struct ipc_service_backend backend_ops = {
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}; \
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BUILD_ASSERT(IS_POWER_OF_TWO(GET_CACHE_ALIGNMENT(i)), \
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"This module supports only power of two cache alignment"); \
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BUILD_ASSERT((GET_BLOCK_SIZE_INST(i, tx, rx) > GET_CACHE_ALIGNMENT(i)) && \
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BUILD_ASSERT((GET_BLOCK_SIZE_INST(i, tx, rx) >= GET_CACHE_ALIGNMENT(i)) && \
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(GET_BLOCK_SIZE_INST(i, tx, rx) < \
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GET_MEM_SIZE_INST(i, tx)), \
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"TX region is too small for provided number of blocks"); \
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BUILD_ASSERT((GET_BLOCK_SIZE_INST(i, rx, tx) > GET_CACHE_ALIGNMENT(i)) && \
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BUILD_ASSERT((GET_BLOCK_SIZE_INST(i, rx, tx) >= GET_CACHE_ALIGNMENT(i)) && \
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(GET_BLOCK_SIZE_INST(i, rx, tx) < \
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GET_MEM_SIZE_INST(i, rx)), \
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"RX region is too small for provided number of blocks"); \
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