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include: dt-bindings: stm32g0_clock: add mco macros

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Adds macros to be able to use the microcontroller clock output (MCO) on the
STM32G0 microcontroller.

Signed-off-by: Andreas Schuster <andreas.schuster@schuam.de>
This commit is contained in:
Andreas Schuster 2025-06-01 12:29:32 +02:00 • committed by Benjamin Cabé
commit 41c6257046
4 changed files with 50 additions and 0 deletions
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1
dts/arm/st/g0/stm32g0b1.dtsi
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@ -6,6 +6,7 @@
*/
#include <st/g0/stm32g071.dtsi>
#include <zephyr/dt-bindings/clock/stm32g0_b1x_c1x_clock.h>
/ {

1
dts/arm/st/g0/stm32g0c1.dtsi
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@ -6,6 +6,7 @@
#include <st/g0/stm32g0b1.dtsi>
#include <st/g0/stm32g0_crypt.dtsi>
#include <zephyr/dt-bindings/clock/stm32g0_b1x_c1x_clock.h>
/ {
soc {

22
include/zephyr/dt-bindings/clock/stm32g0_b1x_c1x_clock.h Normal file
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@ -0,0 +1,22 @@
/*
* Copyright (c) 2025 Andreas Schuster <andreas.schuster@schuam.de>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_B1X_C1X_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_B1X_C1X_CLOCK_H_
/* MCO prescaler : division factor */
#define MCO_PRE_DIV_256 8
#define MCO_PRE_DIV_512 9
#define MCO_PRE_DIV_1024 10
/* MCO clock output */
#define MCO_SEL_HSI48 2
#define MCO_SEL_PLLPCLK 8
#define MCO_SEL_PLLQCLK 9
#define MCO_SEL_RTCCLK 10
#define MCO_SEL_RTCWAKEUP 11
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_B1X_C1X_CLOCK_H_ */

26
include/zephyr/dt-bindings/clock/stm32g0_clock.h
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@ -35,6 +35,9 @@
#define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1)
#define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1)
/** @brief RCC_CFGR register offset */
#define CFGR_REG 0x08
/** @brief RCC_CCIPR register offset */
#define CCIPR_REG 0x54
#define CCIPR2_REG 0x58
@ -43,6 +46,11 @@
#define BDCR_REG 0x5C
/** @brief Device domain clocks selection helpers */
/** CFGR devices */
#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 24, CFGR_REG)
#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 15, 28, CFGR_REG)
#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 16, CFGR_REG)
#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 15, 20, CFGR_REG)
/** CCIPR devices */
#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG)
#define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG)
@ -66,4 +74,22 @@
/** BDCR devices */
#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
/* MCO prescaler : division factor */
#define MCO_PRE_DIV_1 0
#define MCO_PRE_DIV_2 1
#define MCO_PRE_DIV_4 2
#define MCO_PRE_DIV_8 3
#define MCO_PRE_DIV_16 4
#define MCO_PRE_DIV_32 5
#define MCO_PRE_DIV_64 6
#define MCO_PRE_DIV_128 7
/* MCO clock output */
#define MCO_SEL_SYSCLK 1
#define MCO_SEL_HSI16 3
#define MCO_SEL_HSE 4
#define MCO_SEL_PLLRCLK 5
#define MCO_SEL_LSI 6
#define MCO_SEL_LSE 7
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_ */