This change adds basic target mode support for STM32 products.
Controller writes to target, and reading from the target, is supported.
Signed-off-by: James Growden <jgrowden@tenstorrent.com>
Add devicetree binding for the Xilinx Zynq Ultrascale+ MPSoC Real Time
Clock (xlnx,zynqmp-rtc) as a counter device.
The binding describes the RTC hardware block which provides a seconds
counter with alarm and seconds-tick interrupts.
Signed-off-by: Harini T <harini.t@amd.com>
Add ADMA (DMA controller) device tree nodes for the VersalNet
APU (Cortex-A78) subsystem. Eight ADMA channels (adma0-adma7) are
defined at their respective MMIO addresses with GIC SPI interrupts.
Signed-off-by: Abin Joseph <abin.joseph@amd.com>
Add ADMA (DMA controller) device tree nodes for the Versal Gen 2
APU (Cortex-A78) subsystem. Eight ADMA channels (adma0–adma7) are
defined at their respective MMIO addresses with GIC SPI interrupts.
Signed-off-by: Abin Joseph <abin.joseph@amd.com>
Xilinx general purpose DMA is designed to support memory to memory
transfer, memory to device and device to memory transfer.
ZynqMP Ultrascale has two instance of DMA . One located in FPD
(full power domain) is GDMA and the other located in LPD (low power domain)
is ADMA.
Versal and Versal Gen 2 have one instance of this DMA located in
LPD (low power domain) called ADMA with 8 channels.
The controller includes an AXI4 interface to read and
write memory with 16 word transfers for 64 bytes per transaction.
Introduce two yaml files to support two different devices.
Signed-off-by: Abin Joseph <abin.joseph@amd.com>
Complete cmu_N nodes including:
- Add interrupts
- Add clocks and clock-names per the clock tree reference
- cmu_3 / cmu_4 / cmu_5 use nxp,fault-reaction = "reset",
has no interrupt.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
This driver supports CLOCK_MONITOR_MODE_MEASURE:
configure programs REF_CNT from the user's window_ns and the
reference clock rate queried via clock_control; start() triggers a
single measurement whose completion is delivered through the
configure-time callback, with the device auto-disarmed before the
callback runs so the callback may restart the next measurement from
ISR context. get_rate() returns the most recent completed result.
stop() is ISR-safe and aborts an in-flight measurement; a transient
CONFIGURING state guards configure()'s unlocked clock query and HAL
init against concurrent start().
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
This driver supports CLOCK_MONITOR_MODE_WINDOW:
configure programs HFREF and LFREF from the user's expected_hz +
tolerance_ppm (auto-derived from the monitored clock via
clock_control when expected_hz is 0), start begins the background
comparison and stop disables it.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Switch boards da14695_dk_usb and da1469x_dk_pro from
fixed-partition to zephyr,mapped-partition
Signed-off-by: Ioannis Damigos <ioannis.damigos.uj@renesas.com>
The E4, E6 and E8 SoCs share a set of peripherals that are
additional to the minimum subset defined in ensemble_common.dtsi.
Introduce an ensemble_e4_e6_e8.dtsi resource layer (and matching
_nvic_irq/_gic_irq routing layers) to hold these, sitting between
the common layer and the per-SoC files. Rewire the E4/E6/E8 SoC
and interrupt dtsi to include the new layer instead of the common
one. E1C keeps including the common layer directly.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add the uid node to the shared MCXE31x devicetree, describing the
unique chip identifier in the NXP OTP flash memory area via the
nxp,otp-uid binding. The node is left disabled so it has no effect
until a board enables it.
The address and size come from the MCXE31xx Reference Manual UTEST
memory map (8-byte UID at 0x1B000040, programmed by NXP).
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Add a hwinfo device-id backend that reads the unique chip identifier
stored in an NXP OTP flash memory area, as documented in the MCXE31xx
Reference Manual UTEST memory map. Add the nxp,otp-uid devicetree
binding that describes the identifier, and read it directly as memory
(8 bytes, most-significant byte first).
The hwinfo subsystem exposes its z_impl_hwinfo_* entry points as weak
symbols, so this backend implements only hwinfo_get_device_id() and
coexists with a separate reset-cause backend on the same SoC.
The backend is selected only when a node with the nxp,otp-uid
compatible is enabled, so it has no effect on its own; it is build
tested through tests/drivers/hwinfo/api once a board enables the node
(done later in this series).
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
- Change compatible from st,stm32-xspi to st,stm32-xspi-controller.
- Set op-mode to MSPI_OP_MODE_CONTROLLER.
- Set clock-frequency to 50 MHz, as st,stm32-xspi-controller.yaml
specifies it as required (may be moved to board configuration in
the future).
Signed-off-by: Filip Stojanovic <filipembedded@gmail.com>
Add the st,m2-memory-connector DT binding and the corresponding
dt-bindings header defining GPIO pin identifiers for the M2
serial memory connector interface.
Signed-off-by: Filip Stojanovic <filipembedded@gmail.com>
Add a common disabled xspi1 controller node for STM32U3 SoCs.
This provides the XSPI controller description needed by boards
that expose external XSPI memories.
Signed-off-by: Filip Stojanovic <filipembedded@gmail.com>
This adds the XMC4800 BGA196 in 1M/200k and 2M/352k flash/ram variants.
Interrupt controller is untouched at present, the existing XMC4700 and
XMC4800 share a reference manual, and are identical in this regard.
Primary difference to the existing XMC4xxx in the smaller packages is the
addition of extra gpio ports 7, 8 and 9.
Pin control file is added, with basic usic and can pins only. Ports
7/8/9 are mostly for ethercat, but that is out of scope at this point.
Tested with private boards using leds on port 9.
Signed-off-by: Karl Palsson <karl.palsson@marel.com>
The unit address of the node was correct, but not its `reg` properties
(and thus not its `ranges` property either). Fix the latter two.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add WWDT (Windowed WatchDog Timer) support for all LPC55Sxx variants
(LPC55S06/S16/S28/S36/S69):
DTS / board changes:
- Add wwdt0 node (compatible = "nxp,lpc-wwdt", reg = 0xc000) and
watchdog0 alias to nxp_lpc55S0x/S1x/S3x_common.dtsi
- Enable wwdt0 and add watchdog to supported features on
lpcxpresso55s06, lpcxpresso55s16, lpcxpresso55s36 boards
SoC / clock:
- soc.c: call CLOCK_SetClkDiv(kCLOCK_DivWdtClk, 1U, true) when
wwdt0 is enabled, alongside the existing FRO1MHz enable
Driver hardening (per hakehuang review):
- Add `bool started` flag to mcux_wwdt_data to track post-setup state
- Set started=true in mcux_wwdt_setup(), clear in mcux_wwdt_disable()
and PM_DEVICE_ACTION_TURN_OFF
- Guard mcux_wwdt_isr() with early return when !started, preventing
spurious callbacks from warm-reset stale WWDT status on LPC55S36
- Clear WWDT status flags + NVIC pending bit before irq_enable() in
the IRQ init macro
Tests:
- Add per-board .conf files for wdt_basic_api; lpcxpresso55s06/s16
use SRAMX noinit section to survive TrustZone NS Boot ROM clears;
all boards enable WDT_MCUX_WWDT_WARNING_INTERRUPT_CFG=10
- Update testcase.yaml filter to allow SOC_SERIES_LPC55XXX and
exclude lpcxpresso55s69 NS variant
Tested with tests/drivers/watchdog/wdt_basic_api on lpcxpresso55s36:
SUITE PASS 100% [wdt_basic_test_suite]: pass=1, fail=0, skip=0
Signed-off-by: Peter Wang <chaoyi.wang@nxp.com>
The dmas property in flexcomm1-7 and hs_lspi nodes was using an
invalid phandle-array format, missing the required comma separator
between entries:
dmas = <&dma0 6 &dma0 7>; /* incorrect */
Correct it to use the valid comma-separated form, consistent with
flexcomm0 which already had the right format:
dmas = <&dma0 6>, <&dma0 7>; /* correct */
Affected nodes: flexcomm1, flexcomm2, flexcomm3, flexcomm4,
flexcomm5, flexcomm6, flexcomm7, and hs_lspi.
Build-tested with tests/drivers/dma/loop_transfer,
tests/drivers/i2s/i2s_api, and samples/drivers/i2s/i2s_codec
on lpcxpresso55s69/lpc55s69/cpu0.
Signed-off-by: Peter Wang <chaoyi.wang@nxp.com>
Add single-core and SMP RISC-V AIA APLIC+IMSIC board variants as
nested variants of the qemu_virt_riscv32 SoC, mirroring the
qemu_riscv64 'smode' variant precedent.
The APLIC+IMSIC variants:
qemu_riscv32/qemu_virt_riscv32/aia-imsic
qemu_riscv32/qemu_virt_riscv32/aia-imsic/smp
These variants select a common APLIC topology include and add the IMSIC
nodes and properties needed for MSI delivery. They override the per-cpu
riscv,isa-extensions list to advertise smcsrind, which the RISC-V
indirect-CSR (Smcsrind) extension uses to access AIA external-interrupt
CSRs.
The board Kconfig selects RISCV_HAS_AIA on the APLIC+IMSIC variants,
which flips the SoC-level PLIC default off (see the prior commit). The
QEMU command line gates -machine virt,aia=aplic-imsic on the same flag.
The bare qemu_riscv32 identifier is preserved unchanged so existing
downstream platform_allow entries keep resolving.
The APLIC+IMSIC variant yamls intentionally do not set
testing.default=true: interrupt-driven UART through APLIC+IMSIC is not
yet routed for the generic shell/perf/pytest samples, so leaving them as
default would schedule those samples onto a target where they cannot
reach the shell prompt. Tests that explicitly cover the AIA path opt in
via platform_allow / integration_platforms.
Signed-off-by: Afonso Oliveira <afonso.oliveira707@gmail.com>
Assisted-by: Codex:GPT-5.5
Assisted-by: Claude:Fable-5
Move the PLIC node and PLIC-specific interrupt wiring out of the shared
virt-riscv include.
Add them to a QEMU PLIC topology include used by the board files that
still use PLIC. This leaves the shared QEMU virt include interrupt
controller neutral, so AIA variants can select their own topology without
deleting or overriding inherited PLIC nodes and interrupt maps.
Signed-off-by: Afonso Oliveira <afonso.oliveira707@gmail.com>
Assisted-by: Codex:GPT-5.5
Add and modify nodes to feature the new SF controller
Update boards to use the new controller,
significantly increase performance for a lot of them
Allow effectively truly representing the flash,
Allow setting the flash offset via ranges
use ranges properly
Signed-off-by: Camille BAUD <mail@massdriver.space>
Handle necessary code relocation better,
clearly delimiting what is required and what is not
Also group RAM together
Signed-off-by: Camille BAUD <mail@massdriver.space>
BFLB flash driver is updated:
- Add support for bank 2
- Add support for SFDP
- Add ability to use writable devices (MRAM, PSRAM, FRAM) via bank2 mapping
- Improve overall organization
- Add QPI and continous read support
Signed-off-by: Camille BAUD <mail@massdriver.space>
- add a `title` to the binding
- add description for the `interrupts` property indicating expected use
- rework description to be simpler and mention the LPDMA/GPDMA/HPDMA
controller names explicitly
- simplify cells description, refering to the dedicated header instead
of repeating the information for `channel-config`
- make examples proper snippets instead of being in the description
(and make them use named constants from stm32_dma.h)
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
UART5 had incorrect unit address and reg value set.
Replace both with correct address as stated in RM0522.
Signed-off-by: Marin Jurjević <marinjurjevic@outlook.com>
Add basic description for the STM32 Chrom-ART (DMA2D).
For the time being description is kept to the minimum since
DMA2D is only used from within the LVGL framework and the node
is used in order to check the IRQ informations.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Keep the RT1170 MICFIL Audio PLL initialization in the CCM clock
control path, but stop rewriting the MIC root clock while serving
PDM rate queries.
Reprogramming the MIC root caused RT1170 regressions during runtime.
It broke the i2s_codec sample and led to MICFIL capture starvation in
dmic_api. This keeps the safe Audio PLL bring-up while preserving the
working MIC root configuration used by the board.
The RT1170 dmic_api overlay and testcase enablement are included so the
test covers the board directly.
Assisted-by: GitHub Copilot:GPT-5.4
Signed-off-by: Tomas Barak <tomas.barak@nxp.com>
The message_ram reg entry for the stm32l5 fdcan1 node had a type-o
digit (0x400ac000), placing it outside the peripheral memory map. The
correct SRAMCAN base is 0x4000ac00 (APB1PERIPH_BASE + 0xAC00) per the
STM32L5 reference manual and HAL, and it matches the identical fdcan
nodes on the U3/U5/H5 SoCs that share the same m_can base at 0x4000a400.
The Bosch M_CAN driver derives the message RAM address from this reg
entry and zeroes the region during init (can_mcan_sys_clear_mram), so
the wrong address triggers a fault before main() on any STM32L5 board
with FDCAN enabled.
Fixes: 4866cfcc9d ("dts: arm: st: l5: update dtsi file with fdcan node")
Signed-off-by: Chris Desjardins <chris@arch-embedded.com>
The nRF7120 exposes its external MSPI NOR flash through 2 memory-mapped
windows: an uncached window at 0x6000_0000 (512 MB) usable by both the
CM33 and the VPR, and a cached window at 0x0200_0000 (224 MB) reachable
only by the CM33.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
The QingKe V2A, V2C, and V4C have a Debug Module with two data
registers `data0` and `data1`. These can be used with SDI compatible
debuggers such as `minichlink` to send console data to the host.
Add a console driver communicates with the host and fails gracefully
if the driver is enabled but the debugger is not connected.
Compared to the UART console, the debug console uses 916 bytes less
flash and frees up a UART.
Tested on the ch32v006evt and bluepillplus_ch32v203. To test, add
`&sdiconsole { status = "okay"; };` to the board Devicetree, set
`zephyr,console = &sdiconsole`, and enable the driver.
Signed-off-by: Michael Hope <michaelh@juju.nz>
use DT_INST_ENUM_HAS_VALUE for
phy_connection_type, that way we don't have to do
string operations.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
