Moves the MPU6050 accel/gyro scale settings from KConfig to Devicetree.
Adds a new setting for the MPU6050 sample rate divider register and
transmits it to the sensor upon initialization.
This helps to reduce the interrupt firing rate when combined with the
data ready trigger.
A default division factor is provided which ensures compatibility with
existing applications.
The MPU6050 sample application is extended and used for hardware tests.
Signed-off-by: Tilmann Unte <unte@es-augsburg.de>
Add support for setting the sample frequency via `attr_set` and the
output data rate from device tree source.
Signed-off-by: Fredrik Gihl <fgihl@hotmail.com>
This commit to add i2c device node to support i2c sci-b driver
on Renesas RA SoCs
Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
First commit to add support for Renesas RA i2c sci-b driver
Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
The Messaging Unit 7 peripheral is made available for
use with IPC such as OpenAMP/RpMsg. MU7 connects
to the A55 core
Signed-off-by: Andre Heinemans <andre.heinemans@nxp.com>
This commit changes to use ambiq hal power control APIs
to replace the previous register settings to power on
ambiq drivers.
Signed-off-by: Hao Luo <hluo@ambiq.com>
The Xilinx AXI Ethernet subsystem is commonly found in FPGA designs.
This patch adds a driver and device tree bindings for the Ethernet MAC
core and its MDIO controller.
The driver was tested on a RISC-V softcore in an FPGA design, with an
RGMII phy and Ethernet subsystem version 7.2 Rev. 14. Device tree
bindings match the device tree generated by Vitis hsi. Note that Vitis
generates one of the two included compatible strings depending on
version.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
It is defined as spis120 rather than spi120,
because spi120 is already used for SPIM120 hardware instance,
but their base address is different.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Change pinctrl-0 dts prop as optional in case DSI display is used
Add these APIs support: set_brightness, set_contrast, get_framebuffer
Add a new config to select frame buffer section
Signed-off-by: Danh Doan <danh.doan.ue@bp.renesas.com>
Add support for the LCD-PAR display to communicate over
the SPI bus which is available on the PMOD connection interface.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Remove deprecated nxp,kinetis-lptmr compatible string
which is superseded by nxp,lptmr compatible due to
removing family specific name.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The DesignWare I2C driver has already implemented supporting reset device
behavior.
However, the support is incomplete because the `snps,designware-i2c.yaml`,
does not contain a `reset-device.yaml`.
Add include directive to `snps,designware-i2c.yaml` to including
`reset-device.yaml` to complete the support for reset device.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
The flash size is the second part (size) of the first reg value, not the
first part (address) of a nonexistent second reg value.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Extend support in dt bindings and in the driver to allow use of
AIN8 to AIN13 analog inputs.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add GPIO driver support for RZ/A3UL
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
This is the initial commit to support UART driver for Renesas RZ/A3UL.
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
This is the initial commit to support pinctrl driver for Renesas RZ/A3UL
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com>
Currently, siwx917 have three instances of uart: ulpuart, uart1 and
uart2. However:
- The other drivers on siwx91x (i2c, dma, i2s, etc...) rather use
'ulp', '0' and '1'.
- The reference manual also uses 'ulp', '0' and '1'.
The source of the confusion probably come from the clock driver in
WiseConnect which use clocks USART1 and USART2. However, this probably
not expected.
So, this patch renames uart1 and uart2 in uart0 and uart1. This change
also impacts the names of pins and the names of the clocks.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
