Commit 9945d20760 migrated the ft9001_eval partitions to the
zephyr,mapped-partition binding, but the SoC flash controller and flash
nodes were never given the `ranges` properties that the binding requires
to map partition offsets into the CPU address space.
Without them the offsets are no longer translated onto the 0x10000000
flash base, so the code partition (offset 0x1000) links at 0x1000
instead of 0x10001000 and the image no longer matches the flash the SoC
executes from.
Signed-off-by: Patryk Koscik <pkoscik@antmicro.com>
Add missing "package" DTSI file for STM32F777 SoCs which configures the
flash size to the appropriate value.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Refactor RV3032 initialization by configuring Vbackup config in MFD.
Assign PMU/BSM bit at init.
Move trickle-resistor-ohms / trickle-charger-mode to MFD dts node.
Add semaphore lock to mfd_rv3032_update_status since it is a RMW.
Poll EEBUSY at startup to allow for fast start when it is not a POR.
Check EEF flag after EEPROM write.
Adjust I2C poll times for all-byte update and single byte update.
Add function to write single eeprom reg to allow faster poll time.
Use single byte eeprom update for PMU and clock out to skip writing
eeprom when current settings are correct.
Add a k_sem around eeprom operations to protect a future case where
several MFD children are accessing eeprom at same time.
Signed-off-by: Jacob Schloss <jacob.schloss@suburbanmarine.io>
Add a binding for the Microchip IGLOO2 eNVM controller so that
the memory-mapped eNVM can be represented as a child soc-nv-flash
node.
This binding only describes the controller topology and does not
enable a flash controller driver yet.
Signed-off-by: Takumi Ando <takumi@spacecubics.com>
Remove any properties from the Xilinx GEM DT node specification and the
associated header in dt-bindings that relate to the legacy MDIO/PHY
support.
Consistently remove all instances of these properties from the DTs of the
Zynq-7000 and ZynqMP SoCs and from the DT of the qemu_cortex_a9 board.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
As PHY-less use cases such as the GEM being connected to an
Ethernet switch IP core in the FPGA part of the SoC can be
facilitated by declaring a fixed link instead of an actual PHY
in the target board's DT, declare the phy-handle property as
required in the GEM MAC's DT binding in order to prevent
undefined link states and incomplete link speed configuration
in the NWCFG register.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Separate the MDIO functionality from the Xilinx GEM MAC driver
into a separate driver conforming with the standard MDIO API.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Add reg-names property for each GEM controller to enable compatibility with
the DEVICE_MMIO facilities.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Add reg-names property for each GEM controller to enable compatibility with
the DEVICE_MMIO facilities.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Fix configuration of GEM0, GEM1:
- AMBA AHB burst length changed from SINGLE to INCR16
- RX/TX packet buffers in the DMA now fit a full Ethernet frame
This prevents DMA errors and issues with frames that are spread across
multiple buffers.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Fix configuration of GEM0, GEM1:
- AMBA AHB burst length changed from SINGLE to INCR16
- RX/TX packet buffers in the DMA now fit a full Ethernet frame
This prevents DMA errors and issues with frames that are spread across
multiple buffers.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
AXISRAM3/4/5/6 are grandchildren of `peripherals` because they are
subnodes of their corresponding RAMCFG, which is in the peripherals
address range (and thus under `peripherals`). Each RAMCFG node used
a `ranges` property to remap these SRAMs to the correct alias, but
this is quite heavyweight and can be simplified.
By using an empty `ranges;` property on the RAMCFG nodes, but adding
an entry to the top-level `ranges` (i.e., on the `peripherals` node),
the entire hardware "SRAM" region can be remapped to the proper alias
in a much simpler way.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The DMA2D node was outside `peripherals`, so it did not get remapped
when using that to change between secure and non-secure aliases. As
a result, the DMA2D node effectively always retained its secure alias
address, even when building in non-secure context.
Move the DMA2D node in the `peripherals` group to enable its usage in
both secure and non-secure contexts.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
To allow switching addresses of RAM and peripherals between the secure
and non-secure aliases, commit 1d38a4ac04
replaced the `reg` and unit address of all nodes with a "zero-based"
value. This was necessary because the child-bus-address of the added
`ranges` property was zero... but an arbitrary value can be used!
By updating the `ranges` properties, it becomes possible to use "real"
addresses in `reg` and unit addresses of every node which makes the
DTSI much more readable, while still allowing to easily switch between
the secure and non-secure aliases (only the child-bus-address differs).
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Increase the size of the MMIO region covered by the `pin-controller`
so that all children nodes fall into it. The previous value of 0x2000
did not cover all ports up to GPIOQ (starting at offset 0x4000, ending
at 0x43FF).
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add the STM32MP13 RTC devicetree node and enable it for the
STM32MP135F-DK board.
The RTC is configured to use LSE as its clock source. LSE remains
available in low-power modes and in the backup domain when VBAT is
present, allowing the RTC to keep running and wake the system from
standby.
Tested on STM32MP135F-DK hardware.
Signed-off-by: Mohammed Achraf TAMZIT <mohammed.achraftamzit@gmail.com>
Add devicetree clock nodes for the STM32MP13 internal low-speed
oscillator (LSI) and external low-speed oscillator (LSE).
These nodes allow board devicetrees to reference and enable the
available low-speed clock sources as needed.
Signed-off-by: Mohammed Achraf TAMZIT <mohammed.achraftamzit@gmail.com>
Add a CAN driver for the Espressif TWAI-FD controller used on the
ESP32-C5. The driver implements the full can_driver_api,
supporting Classic CAN and CAN-FD frames.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The ESP32-C5 has TWAI-FD capable controllers that support both
Classic CAN and CAN-FD frames. Update the SoC dtsi to use the new
espressif,esp32-twaifd compatible so the new TWAI-FD driver binds with
it.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add the nxp,iap-fmc84x compatible, clock and flash access time
properties to the LPC84x IAP flash controller node.
Signed-off-by: Dilip Raman <dilipr@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
- Add Devicetree nodes for the Switch Matrix (SWM) and
IOCON peripherals.
- Add UART0 to UART4 peripherals nodes with register,
clock, and interrupt properties.
Signed-off-by: Surya Prakash T <suryat@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Co-authored-by: Dilip Raman <dilipr@aerlync.com>
- Add LPC84x clock control node and associated configuration required
for system clock initialization.
Signed-off-by: Deepika R <deepika@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Co-authored-by: Dilip Raman <dilipr@aerlync.com>
Add the YAML binding definitions for the LPC84x I/O Configuration (IOCON)
and Switch Matrix (SWM) peripherals to support the new pinctrl driver.
Signed-off-by: Surya Prakash T <suryat@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Co-authored-by: Dilip Raman <dilipr@aerlync.com>
- Add Devicetree binding describing initialization properties for the
LPC84x clock control driver, including configuration of FRO mode.
Signed-off-by: Deepika R <deepika@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Co-authored-by: Dilip Raman <dilipr@aerlync.com>
Add SoC support for the NXP LPC84x (LPC845) series microcontroller.
This commit introduces:
- SoC device tree binding (nxp_lpc845.dtsi & nxp_lpc84x.dtsi)
- Kconfig configuration for LPC84x series
- Minimal SoC initialization (soc.c/soc.h)
- Build system integration (CMakeLists.txt)
Signed-off-by: Vignesh Pandian <vignesh@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Co-authored-by: Dilip Raman <dilipr@aerlync.com>
The ti,clk-divider, auto-powerdown and vref properties were declared
without a description, leaving their semantics unclear when writing
devicetree nodes. Add descriptions explaining the clock divider's
effect on the sample clock, the manual vs. automatic power-down
behaviour, and how the vref phandle is used to derive the reference
voltage in millivolts.
This is a documentation-only change; no functional behaviour is
affected.
Signed-off-by: Florian Schuele <florian@schuele-embedded.de>
The main goal of this change is being able to use counter_gecko_rtcc.c and
leuart_gecko.c on boards without an LFXO. This is the case for tyzs3.
The main changes are in soc/silabs/common, the rest is just to migrate all
of the boards.
This uses the device tree for clock-initialization only. I did not
implement a clock_control driver, because I don't see a need for that. The
drivers use CMU_ClockEnable, which abstracts away SoC differences already.
The config SOC_GECKO_HAS_HFRCO_FREQRANGE was removed, because:
- This can be detected via macros provided by gecko_sdk.
- There is an alternative to that API which wasn't implemented previously,
but is now (cmuHFRCOBand_*).
I don't own any of the boards except for tuya tyzs3, but did my best to
avoid mistakes. That being said, I found several issues, which were present
in some of the boards already:
- sltb004a: This board has a 38.4MHz HFXO crystal, but it was configured to
40MHz. I fixed that.
- tomu: This board uses HFRCO as it's HF clock, even though the SoC does
not support SOC_GECKO_HAS_HFRCO_FREQRANGE. So it was probably running at
the initial 14MHz instead.
- Many boards enabled leuart and rtcc (counter) peripherals, which need(ed)
LFXO, without ever enabling LFXO. These peripherals were probably not
working before this change.
Noteworthy finds:
- slwrb4321a: This board uses HFRCO as it's HF clock, but has a board.c
where it enables HFXO to use it as the RMII reference clock. I'm not sure
if it's okay to do that without calling CMU_HFXOInit first. I did not
modify that code to not change behavior that I don't understand.
Signed-off-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
Remove the deprecated counter-based Maxim DS3231 driver and its
dedicated API, binding, sample, and test coverage.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add a memory node of size 0x400 at address 0. This region will be
configured in MPU for NULL pointer dereference detection.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Generic MSPI driver for the ISSI IS66/67WV Serial PSRAM family
(both wrapped-burst WVS and continuous WVR variants).
Implements MEMC read/write for bus-transaction access via MSPI.
When CONFIG_MSPI_XIP=y and xip-config is present in DT with
enable=true, also implements get_mem_base so the memcpy path
is used automatically on controllers with a memory-mapped
aperture.
Signed-off-by: Dhanoo Surasarang <dhanoo.surasarang@nordicsemi.no>
The external memory device was updated instead of the internal
memory device which has the bootable partitions, this recfities it
to be the internal flash which is set to use mapped partitions
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Change calibration process to handle differential calibration
Configure channel 10 to differential for Nucleo N657X0-Q and
STM32N6570-DK in `adc_api` test
Pin PA10 (Arduino A2) is shared as positive input for channel 11
and negative input for channel 10, allowing to keep default pin
configuration to test single and differential input.
Signed-off-by: Basile GRUNER <basile.gruner@smile.fr>
Add a GPIO expander driver for the Raspberry Pi BCM283x, using
the VideoCore firmware property interface.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Add nor flash drivers for Realtek Bee family SoCs (RTL8752H and RTL87x2G).
Supports read, write, erase operations with page layout support.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Add YAML binding for the Realtek Bee nor flash, including
properties for supported flash bit modes (2-bit, 4-bit, and 4-bit DTR).
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Implement device runtime power management for the SiWx91x
entropy driver. This ensures that the RNG is automatically
reenabled after deep sleep.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
VexiiRiscv is a RISC-V CPU core written in SpinalHDL, the successor
to VexRiscv. It features a configurable pipeline architecture and
stretches from very small RV32 to large RV64 dual issue cores.
https://github.com/SpinalHDL/VexiiRiscv
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
